TI's J784S4 SoC has two x4 Lane and two x2 Lane Gen3 PCIe Controllers.
This series adds the device-tree nodes for all 4 PCIe instances in the
SoC file (k3-j784s4-main.dtsi). The J784S4-EVM board has only PCIe0 and
PCIe1 instances of PCIe brought out while the AM69-SK board has PCIe0,
PCIe1 and PCIe3 instances of PCIe brought out. The device-tree overlay
to enable PCIe0 and PCIe1 in Endpoint mode of operation on J784S4-EVM is
also included in this series.
v3:
https://lore.kernel.org/r/[email protected]/
Changes since v3:
- Rebased on linux-next tagged next-20240528.
- Added ranges for PCIe2 and PCIe3 in k3-j784s4.dtsi which was missed in
v3 series.
- Added new patch in this series for enabling PCIe on AM69-SK board.
v2:
https://lore.kernel.org/r/[email protected]/
Changes since v2:
- Rebased on linux-next tagged next-20240523.
- Based on feedback from Francesco Dolcini <[email protected]> at:
https://lore.kernel.org/r/20240521200909.GA3707@francesco-nb/
the device-tree nodes for PCIe2 and PCIe3 instances of PCIe have been
added.
v1:
https://lore.kernel.org/r/[email protected]
Changes since v1:
- Rebased series on linux-next tagged next-20240520.
- All dependencies mentioned in v1 series have been met. This series has
no further dependencies for functionality.
- Added "pcie0_ctrl" and "pcie1_ctrl" nodes within the System Controller
node (scm_conf). This enables reusing the existing
"ti,syscon-pcie-ctrl" property without having to map the entire System
Controller region for configuring the PCIe specific registers within
"scm_conf". This change is also done in the "overlay" file in patch
3/3 w.r.t. providing the phandle to the pcie0_ctrl and pcie1_ctrl
nodes to the "ti,syscon-pcie-ctrl" property in the overlay.
Test Logs:
1. J784S4-EVM PCIe0 and PCIe1 in RC Mode with NVMe SSD connected to PCIe0:
https://gist.github.com/Siddharth-Vadapalli-at-TI/af94b2da5dd0613de8a238e37f70eb7e
2. J784S4-EVM PCIe0 as Endpoint and AM69-SK PCIe0 acting as RC:
https://gist.github.com/Siddharth-Vadapalli-at-TI/1d305c5145bdc34975615e15fe0f433c
3. J784S4-EVM PCIe1 as Endpoint and AM69-SK PCIe0 acting as RC:
https://gist.github.com/Siddharth-Vadapalli-at-TI/3129da32c9984f4f02351ca03105e49e
4. AM69-SK PCIe0, PCIe1 and PCIe3 in RC Mode with NVMe SSD connected to
PCIe0:
https://gist.github.com/Siddharth-Vadapalli-at-TI/5571eb0a0273501fcc214519beab6713
Regards,
Siddharth.
Dasnavis Sabiya (1):
arm64: dts: ti: k3-am69-sk: Add PCIe support
Siddharth Vadapalli (3):
arm64: dts: ti: k3-j784s4-main: Add PCIe nodes
arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode
arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode
arch/arm64/boot/dts/ti/Makefile | 7 +-
arch/arm64/boot/dts/ti/k3-am69-sk.dts | 60 ++++++++
.../dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso | 79 ++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 46 ++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 136 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 10 +-
6 files changed, 336 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-pcie0-pcie1-ep.dtso
--
2.40.1
TI's J784S4 SoC has four instances of Gen3 PCIe Controllers namely
PCIe0, PCIe1, PCIe2 and PCIe3. PCIe0 and PCIe1 are 4-Lane controllers
while PCIe2 and PCIe3 are 2-Lane controllers.
Add support for the Root Complex Mode of operation of these PCIe instances.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
v3:
https://lore.kernel.org/r/[email protected]/
Changes since v3:
- Added ranges for PCIe2 and PCIe3 in k3-j784s4.dtsi which was missed in
v3 series.
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 136 +++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 10 +-
2 files changed, 145 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 6a4554c6c9c1..7f89f8dc24df 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -48,6 +48,26 @@ scm_conf: bus@100000 {
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
+ pcie0_ctrl: pcie0-ctrl@4070 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4070 0x4>;
+ };
+
+ pcie1_ctrl: pcie1-ctrl@4074 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4074 0x4>;
+ };
+
+ pcie2_ctrl: pcie2-ctrl@4078 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4078 0x4>;
+ };
+
+ pcie3_ctrl: pcie3-ctrl@407c {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x407c 0x4>;
+ };
+
serdes_ln_ctrl: mux-controller@4080 {
compatible = "reg-mux";
reg = <0x00004080 0x30>;
@@ -907,6 +927,122 @@ main_sdhci1: mmc@4fb0000 {
status = "disabled";
};
+ pcie0_rc: pcie@2900000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02900000 0x00 0x1000>,
+ <0x00 0x02907000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x10000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 332 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 333 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x10000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
+ pcie2_rc: pcie@2920000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02920000 0x00 0x1000>,
+ <0x00 0x02927000 0x00 0x400>,
+ <0x00 0x0e000000 0x00 0x00800000>,
+ <0x44 0x00000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 334 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 334 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x20000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
+ pcie3_rc: pcie@2930000 {
+ compatible = "ti,j784s4-pcie-host";
+ reg = <0x00 0x02930000 0x00 0x1000>,
+ <0x00 0x02937000 0x00 0x400>,
+ <0x00 0x0e800000 0x00 0x00800000>,
+ <0x44 0x10000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>;
+ max-link-speed = <3>;
+ num-lanes = <2>;
+ power-domains = <&k3_pds 335 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 335 0>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb012>;
+ msi-map = <0x0 &gic_its 0x30000 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ status = "disabled";
+ };
+
serdes_wiz0: wiz@5060000 {
compatible = "ti,j784s4-wiz-10g";
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
index da7368ed6b52..73cc3c1fec08 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
@@ -238,7 +238,10 @@ cbass_main: bus@100000 {
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
<0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
<0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
- <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
+ <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
+ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/
+ <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/
<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
@@ -248,7 +251,12 @@ cbass_main: bus@100000 {
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
+ <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */
+ <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */
+ <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */
+ <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
/* MCUSS_WKUP Range */
--
2.40.1
Enable PCIe0 and PCIe1 instances of PCIe in Root Complex mode of
operation on J784S4 EVM. The lanes of PCIe0 are connected to Serdes1
instance of Serdes while the lanes of PCIe1 are connected to Serdes0
instance of Serdes in J784S4 SoC. Despite both PCIe instances supporting
up to 4 Lanes, since the physical connections to the PCIe connector
corresponding to the PCIe1 instance of PCIe are limited to 2 Lanes on
the J784S4 EVM, update the "num-lanes" property of PCIe1 accordingly.
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
v3:
https://lore.kernel.org/r/[email protected]/
No changes since v3.
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 46 ++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index d511b25d62e3..31e88a6445f4 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -1105,3 +1105,49 @@ dp0_out: endpoint {
};
};
};
+
+&serdes0 {
+ status = "okay";
+ serdes0_pcie1_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <4>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>,
+ <&serdes_wiz0 3>, <&serdes_wiz0 4>;
+ };
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&pcie1_rc {
+ status = "okay";
+ num-lanes = <2>;
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie1_link>;
+ phy-names = "pcie-phy";
+};
+
+&serdes1 {
+ status = "okay";
+ serdes1_pcie0_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&serdes_wiz1 {
+ status = "okay";
+};
+
+&pcie0_rc {
+ status = "okay";
+ reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes1_pcie0_link>;
+ phy-names = "pcie-phy";
+};
--
2.40.1
Hi Siddharth Vadapalli,
On Wed, 29 May 2024 13:52:55 +0530, Siddharth Vadapalli wrote:
> TI's J784S4 SoC has two x4 Lane and two x2 Lane Gen3 PCIe Controllers.
> This series adds the device-tree nodes for all 4 PCIe instances in the
> SoC file (k3-j784s4-main.dtsi). The J784S4-EVM board has only PCIe0 and
> PCIe1 instances of PCIe brought out while the AM69-SK board has PCIe0,
> PCIe1 and PCIe3 instances of PCIe brought out. The device-tree overlay
> to enable PCIe0 and PCIe1 in Endpoint mode of operation on J784S4-EVM is
> also included in this series.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/4] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes
commit: 8e05ce691af29db0c7f0d468c8d7c6e13273a9e6
[2/4] arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode
commit: 27ce26fe52d4dcb5bf58cdf5527e2f3a498c1fdf
[3/4] arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode
commit: 7c4270de2806f80c06dc80c2cf2c8d6eb7c44c59
[4/4] arm64: dts: ti: k3-am69-sk: Add PCIe support
commit: 2f79e7408ac1b22ce8abc4a22b92793a57a3077d
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh