From: Nikita Shubin <[email protected]>
From: Nikita Shubin <[email protected]>
This series aims to provide matching vendor SoC with corresponded JSON bindings.
The ID string is proposed to be in form of MVENDORID-MARCHID-MIMPID, for example
for Sifive Unmatched the corresponding string will be:
0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
Where MIMPID can vary as all impl supported the same number of events, this might not
be true for all future SoC however.
Also added SBI firmware events pretty names, as any firmware that supports SBI PMU
should also support firmare events [1].
Series depends on patch by Anup Patel, exposing mvendor, marchid and mimpid
to "/proc/cpuinfo" [2].
[1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
[2] https://lkml.org/lkml/2022/6/20/498
Link to previous version:
https://patchwork.kernel.org/project/linux-riscv/list/?series=653649
See original cover letter by João Mário Domingos:
https://patchwork.kernel.org/project/linux-riscv/cover/[email protected]/
Tested with the following OpenSBI device tree bindings:
```
pmu {
compatible = "riscv,pmu";
riscv,event-to-mhpmcounters =
<0x03 0x06 0x18
0x10001 0x10002 0x18
0x10009 0x10009 0x18
0x10011 0x10011 0x18
0x10019 0x10019 0x18
0x10021 0x10021 0x18>;
riscv,event-to-mhpmevent =
<0x03 0x00000000 0x1801
0x04 0x00000000 0x0302
0x05 0x00000000 0x4000
0x06 0x00000000 0x6001
0x10001 0x00000000 0x0202
0x10002 0x00000000 0x0402
0x10009 0x00000000 0x0102
0x10011 0x00000000 0x2002
0x10019 0x00000000 0x1002
0x10021 0x00000000 0x0802>;
riscv,raw-event-to-mhpmcounters =
<0x00000000 0x03ffff00 0x0 0x0 0x18
0x00000000 0x0007ff01 0x0 0x1 0x18
0x00000000 0x00003f02 0x0 0x2 0x18>;
};
```
---
v4->v5:
Atish Patra:
- dropped cycle, time instret std arch events
- format config is now 48-bit wide
Arnaldo Carvalho de Melo:
- fixed cpuid leakage
- no "if" before free
Will Deacon:
- simply use "config:63"
---
Nikita Shubin (4):
drivers/perf: riscv_pmu_sbi: perf format
perf tools riscv: Add support for get_cpuid_str function
perf arch events: riscv sbi firmware std event files
perf vendor events riscv: add Sifive U74 JSON file
drivers/perf/riscv_pmu_sbi.c | 20 +++
tools/perf/arch/riscv/util/Build | 1 +
tools/perf/arch/riscv/util/header.c | 106 ++++++++++++++
tools/perf/pmu-events/arch/riscv/mapfile.csv | 17 +++
.../arch/riscv/riscv-sbi-firmware.json | 134 ++++++++++++++++++
.../arch/riscv/sifive/u74/firmware.json | 68 +++++++++
.../arch/riscv/sifive/u74/instructions.json | 92 ++++++++++++
.../arch/riscv/sifive/u74/memory.json | 32 +++++
.../arch/riscv/sifive/u74/microarch.json | 57 ++++++++
9 files changed, 527 insertions(+)
create mode 100644 tools/perf/arch/riscv/util/header.c
create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
--
2.30.2
From: Nikita Shubin <[email protected]>
Firmware events are defined by "RISC-V Supervisor Binary Interface
Specification", which means they should be always available as long as
firmware supports >= 0.3.0 SBI.
Expose them to arch std events, so they can be reused by particular
PMU bindings.
Signed-off-by: Nikita Shubin <[email protected]>
---
v4->v5:
- changed EventCode to ConfigCode, as 63 bit exceeds event code format
---
.../arch/riscv/riscv-sbi-firmware.json | 134 ++++++++++++++++++
1 file changed, 134 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
new file mode 100644
index 000000000000..b9d305f1ada8
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
@@ -0,0 +1,134 @@
+[
+ {
+ "PublicDescription": "Misaligned load trap",
+ "ConfigCode": "0x8000000000000000",
+ "EventName": "FW_MISALIGNED_LOAD",
+ "BriefDescription": "Misaligned load trap event"
+ },
+ {
+ "PublicDescription": "Misaligned store trap",
+ "ConfigCode": "0x8000000000000001",
+ "EventName": "FW_MISALIGNED_STORE",
+ "BriefDescription": "Misaligned store trap event"
+ },
+ {
+ "PublicDescription": "Load access trap",
+ "ConfigCode": "0x8000000000000002",
+ "EventName": "FW_ACCESS_LOAD",
+ "BriefDescription": "Load access trap event"
+ },
+ {
+ "PublicDescription": "Store access trap",
+ "ConfigCode": "0x8000000000000003",
+ "EventName": "FW_ACCESS_STORE",
+ "BriefDescription": "Store access trap event"
+ },
+ {
+ "PublicDescription": "Illegal instruction trap",
+ "ConfigCode": "0x8000000000000004",
+ "EventName": "FW_ILLEGAL_INSN",
+ "BriefDescription": "Illegal instruction trap event"
+ },
+ {
+ "PublicDescription": "Set timer event",
+ "ConfigCode": "0x8000000000000005",
+ "EventName": "FW_SET_TIMER",
+ "BriefDescription": "Set timer event"
+ },
+ {
+ "PublicDescription": "Sent IPI to other HART event",
+ "ConfigCode": "0x8000000000000006",
+ "EventName": "FW_IPI_SENT",
+ "BriefDescription": "Sent IPI to other HART event"
+ },
+ {
+ "PublicDescription": "Received IPI from other HART event",
+ "ConfigCode": "0x8000000000000007",
+ "EventName": "FW_IPI_RECEIVED",
+ "BriefDescription": "Received IPI from other HART event"
+ },
+ {
+ "PublicDescription": "Sent FENCE.I request to other HART event",
+ "ConfigCode": "0x8000000000000008",
+ "EventName": "FW_FENCE_I_SENT",
+ "BriefDescription": "Sent FENCE.I request to other HART event"
+ },
+ {
+ "PublicDescription": "Received FENCE.I request from other HART event",
+ "ConfigCode": "0x8000000000000009",
+ "EventName": "FW_FENCE_I_RECEIVED",
+ "BriefDescription": "Received FENCE.I request from other HART event"
+ },
+ {
+ "PublicDescription": "Sent SFENCE.VMA request to other HART event",
+ "ConfigCode": "0x80000000000000a",
+ "EventName": "FW_SFENCE_VMA_SENT",
+ "BriefDescription": "Sent SFENCE.VMA request to other HART event"
+ },
+ {
+ "PublicDescription": "Received SFENCE.VMA request from other HART event",
+ "ConfigCode": "0x800000000000000b",
+ "EventName": "FW_SFENCE_VMA_RECEIVED",
+ "BriefDescription": "Received SFENCE.VMA request from other HART event"
+ },
+ {
+ "PublicDescription": "Sent SFENCE.VMA with ASID request to other HART event",
+ "ConfigCode": "0x800000000000000c",
+ "EventName": "FW_SFENCE_VMA_RECEIVED",
+ "BriefDescription": "Sent SFENCE.VMA with ASID request to other HART event"
+ },
+ {
+ "PublicDescription": "Received SFENCE.VMA with ASID request from other HART event",
+ "ConfigCode": "0x800000000000000d",
+ "EventName": "FW_SFENCE_VMA_ASID_RECEIVED",
+ "BriefDescription": "Received SFENCE.VMA with ASID request from other HART event"
+ },
+ {
+ "PublicDescription": "Sent HFENCE.GVMA request to other HART event",
+ "ConfigCode": "0x800000000000000e",
+ "EventName": "FW_HFENCE_GVMA_SENT",
+ "BriefDescription": "Sent HFENCE.GVMA request to other HART event"
+ },
+ {
+ "PublicDescription": "Received HFENCE.GVMA request from other HART event",
+ "ConfigCode": "0x800000000000000f",
+ "EventName": "FW_HFENCE_GVMA_RECEIVED",
+ "BriefDescription": "Received HFENCE.GVMA request from other HART event"
+ },
+ {
+ "PublicDescription": "Sent HFENCE.GVMA with VMID request to other HART event",
+ "ConfigCode": "0x8000000000000010",
+ "EventName": "FW_HFENCE_GVMA_VMID_SENT",
+ "BriefDescription": "Sent HFENCE.GVMA with VMID request to other HART event"
+ },
+ {
+ "PublicDescription": "Received HFENCE.GVMA with VMID request from other HART event",
+ "ConfigCode": "0x8000000000000011",
+ "EventName": "FW_HFENCE_GVMA_VMID_RECEIVED",
+ "BriefDescription": "Received HFENCE.GVMA with VMID request from other HART event"
+ },
+ {
+ "PublicDescription": "Sent HFENCE.VVMA request to other HART event",
+ "ConfigCode": "0x8000000000000012",
+ "EventName": "FW_HFENCE_VVMA_SENT",
+ "BriefDescription": "Sent HFENCE.VVMA request to other HART event"
+ },
+ {
+ "PublicDescription": "Received HFENCE.VVMA request from other HART event",
+ "ConfigCode": "0x8000000000000013",
+ "EventName": "FW_HFENCE_VVMA_RECEIVED",
+ "BriefDescription": "Received HFENCE.VVMA request from other HART event"
+ },
+ {
+ "PublicDescription": "Sent HFENCE.VVMA with ASID request to other HART event",
+ "ConfigCode": "0x8000000000000014",
+ "EventName": "FW_HFENCE_VVMA_ASID_SENT",
+ "BriefDescription": "Sent HFENCE.VVMA with ASID request to other HART event"
+ },
+ {
+ "PublicDescription": "Received HFENCE.VVMA with ASID request from other HART event",
+ "ConfigCode": "0x8000000000000015",
+ "EventName": "FW_HFENCE_VVMA_ASID_RECEIVED",
+ "BriefDescription": "Received HFENCE.VVMA with ASID request from other HART event"
+ }
+]
--
2.30.2
From: Nikita Shubin <[email protected]>
This patch add the Sifive U74 JSON file.
Derived-from-code-by: João Mário Domingos <[email protected]>
Signed-off-by: Nikita Shubin <[email protected]>
Link: https://sifive.cdn.prismic.io/sifive/ad5577a0-9a00-45c9-a5d0-424a3d586060_u74_core_complex_manual_21G3.pdf
---
v4->v5:
- dropped cycle, time, instret ArchStdEvent bindings
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 17 ++++
.../arch/riscv/sifive/u74/firmware.json | 68 ++++++++++++++
.../arch/riscv/sifive/u74/instructions.json | 92 +++++++++++++++++++
.../arch/riscv/sifive/u74/memory.json | 32 +++++++
.../arch/riscv/sifive/u74/microarch.json | 57 ++++++++++++
5 files changed, 266 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
new file mode 100644
index 000000000000..c61b3d6ef616
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -0,0 +1,17 @@
+# Format:
+# MVENDORID-MARCHID-MIMPID,Version,JSON/file/pathname,Type
+#
+# where
+# MVENDORID JEDEC code of the core provider
+# MARCHID base microarchitecture of the hart
+# MIMPID unique encoding of the version
+# of the processor implementation
+# Version could be used to track version of JSON file
+# but currently unused.
+# JSON/file/pathname is the path to JSON file, relative
+# to tools/perf/pmu-events/arch/riscv/.
+# Type is core, uncore etc
+#
+#
+#MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
+0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
new file mode 100644
index 000000000000..9b4a032186a7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/firmware.json
@@ -0,0 +1,68 @@
+[
+ {
+ "ArchStdEvent": "FW_MISALIGNED_LOAD"
+ },
+ {
+ "ArchStdEvent": "FW_MISALIGNED_STORE"
+ },
+ {
+ "ArchStdEvent": "FW_ACCESS_LOAD"
+ },
+ {
+ "ArchStdEvent": "FW_ACCESS_STORE"
+ },
+ {
+ "ArchStdEvent": "FW_ILLEGAL_INSN"
+ },
+ {
+ "ArchStdEvent": "FW_SET_TIMER"
+ },
+ {
+ "ArchStdEvent": "FW_IPI_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_IPI_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_FENCE_I_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_FENCE_I_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
new file mode 100644
index 000000000000..5eab718c9256
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
@@ -0,0 +1,92 @@
+[
+ {
+ "EventName": "EXCEPTION_TAKEN",
+ "EventCode": "0x0000100",
+ "BriefDescription": "Exception taken"
+ },
+ {
+ "EventName": "INTEGER_LOAD_RETIRED",
+ "EventCode": "0x0000200",
+ "BriefDescription": "Integer load instruction retired"
+ },
+ {
+ "EventName": "INTEGER_STORE_RETIRED",
+ "EventCode": "0x0000400",
+ "BriefDescription": "Integer store instruction retired"
+ },
+ {
+ "EventName": "ATOMIC_MEMORY_RETIRED",
+ "EventCode": "0x0000800",
+ "BriefDescription": "Atomic memory operation retired"
+ },
+ {
+ "EventName": "SYSTEM_INSTRUCTION_RETIRED",
+ "EventCode": "0x0001000",
+ "BriefDescription": "System instruction retired"
+ },
+ {
+ "EventName": "INTEGER_ARITHMETIC_RETIRED",
+ "EventCode": "0x0002000",
+ "BriefDescription": "Integer arithmetic instruction retired"
+ },
+ {
+ "EventName": "CONDITIONAL_BRANCH_RETIRED",
+ "EventCode": "0x0004000",
+ "BriefDescription": "Conditional branch retired"
+ },
+ {
+ "EventName": "JAL_INSTRUCTION_RETIRED",
+ "EventCode": "0x0008000",
+ "BriefDescription": "JAL instruction retired"
+ },
+ {
+ "EventName": "JALR_INSTRUCTION_RETIRED",
+ "EventCode": "0x0010000",
+ "BriefDescription": "JALR instruction retired"
+ },
+ {
+ "EventName": "INTEGER_MULTIPLICATION_RETIRED",
+ "EventCode": "0x0020000",
+ "BriefDescription": "Integer multiplication instruction retired"
+ },
+ {
+ "EventName": "INTEGER_DIVISION_RETIRED",
+ "EventCode": "0x0040000",
+ "BriefDescription": "Integer division instruction retired"
+ },
+ {
+ "EventName": "FP_LOAD_RETIRED",
+ "EventCode": "0x0080000",
+ "BriefDescription": "Floating-point load instruction retired"
+ },
+ {
+ "EventName": "FP_STORE_RETIRED",
+ "EventCode": "0x0100000",
+ "BriefDescription": "Floating-point store instruction retired"
+ },
+ {
+ "EventName": "FP_ADDITION_RETIRED",
+ "EventCode": "0x0200000",
+ "BriefDescription": "Floating-point addition retired"
+ },
+ {
+ "EventName": "FP_MULTIPLICATION_RETIRED",
+ "EventCode": "0x0400000",
+ "BriefDescription": "Floating-point multiplication retired"
+ },
+ {
+ "EventName": "FP_FUSEDMADD_RETIRED",
+ "EventCode": "0x0800000",
+ "BriefDescription": "Floating-point fused multiply-add retired"
+ },
+ {
+ "EventName": "FP_DIV_SQRT_RETIRED",
+ "EventCode": "0x1000000",
+ "BriefDescription": "Floating-point division or square-root retired"
+ },
+ {
+ "EventName": "OTHER_FP_RETIRED",
+ "EventCode": "0x2000000",
+ "BriefDescription": "Other floating-point instruction retired"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
new file mode 100644
index 000000000000..be1a46312ac3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
@@ -0,0 +1,32 @@
+[
+ {
+ "EventName": "ICACHE_RETIRED",
+ "EventCode": "0x0000102",
+ "BriefDescription": "Instruction cache miss"
+ },
+ {
+ "EventName": "DCACHE_MISS_MMIO_ACCESSES",
+ "EventCode": "0x0000202",
+ "BriefDescription": "Data cache miss or memory-mapped I/O access"
+ },
+ {
+ "EventName": "DCACHE_WRITEBACK",
+ "EventCode": "0x0000402",
+ "BriefDescription": "Data cache write-back"
+ },
+ {
+ "EventName": "INST_TLB_MISS",
+ "EventCode": "0x0000802",
+ "BriefDescription": "Instruction TLB miss"
+ },
+ {
+ "EventName": "DATA_TLB_MISS",
+ "EventCode": "0x0001002",
+ "BriefDescription": "Data TLB miss"
+ },
+ {
+ "EventName": "UTLB_MISS",
+ "EventCode": "0x0002002",
+ "BriefDescription": "UTLB miss"
+ }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
new file mode 100644
index 000000000000..50ffa55418cb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
@@ -0,0 +1,57 @@
+[
+ {
+ "EventName": "ADDRESSGEN_INTERLOCK",
+ "EventCode": "0x0000101",
+ "BriefDescription": "Address-generation interlock"
+ },
+ {
+ "EventName": "LONGLAT_INTERLOCK",
+ "EventCode": "0x0000201",
+ "BriefDescription": "Long-latency interlock"
+ },
+ {
+ "EventName": "CSR_READ_INTERLOCK",
+ "EventCode": "0x0000401",
+ "BriefDescription": "CSR read interlock"
+ },
+ {
+ "EventName": "ICACHE_ITIM_BUSY",
+ "EventCode": "0x0000801",
+ "BriefDescription": "Instruction cache/ITIM busy"
+ },
+ {
+ "EventName": "DCACHE_DTIM_BUSY",
+ "EventCode": "0x0001001",
+ "BriefDescription": "Data cache/DTIM busy"
+ },
+ {
+ "EventName": "BRANCH_DIRECTION_MISPREDICTION",
+ "EventCode": "0x0002001",
+ "BriefDescription": "Branch direction misprediction"
+ },
+ {
+ "EventName": "BRANCH_TARGET_MISPREDICTION",
+ "EventCode": "0x0004001",
+ "BriefDescription": "Branch/jump target misprediction"
+ },
+ {
+ "EventName": "PIPE_FLUSH_CSR_WRITE",
+ "EventCode": "0x0008001",
+ "BriefDescription": "Pipeline flush from CSR write"
+ },
+ {
+ "EventName": "PIPE_FLUSH_OTHER_EVENT",
+ "EventCode": "0x0010001",
+ "BriefDescription": "Pipeline flush from other event"
+ },
+ {
+ "EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
+ "EventCode": "0x0020001",
+ "BriefDescription": "Integer multiplication interlock"
+ },
+ {
+ "EventName": "FP_INTERLOCK",
+ "EventCode": "0x0040001",
+ "BriefDescription": "Floating-point interlock"
+ }
+]
\ No newline at end of file
--
2.30.2
On Tue, 28 Jun 2022 14:45:54 +0300, Nikita Shubin wrote:
> From: Nikita Shubin <[email protected]>
>
> From: Nikita Shubin <[email protected]>
>
> This series aims to provide matching vendor SoC with corresponded JSON bindings.
>
> The ID string is proposed to be in form of MVENDORID-MARCHID-MIMPID, for example
> for Sifive Unmatched the corresponding string will be:
>
> [...]
Applied first patch only to will (for-next/perf), thanks!
[1/4] drivers/perf: riscv_pmu_sbi: perf format
https://git.kernel.org/will/c/26fabd6d2ffc
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
On Tue, 2022-06-28 at 14:45 +0300, Nikita Shubin wrote:
> From: Nikita Shubin <[email protected]>
>
> Firmware events are defined by "RISC-V Supervisor Binary Interface
> Specification", which means they should be always available as long
> as
> firmware supports >= 0.3.0 SBI.
>
> Expose them to arch std events, so they can be reused by particular
> PMU bindings.
>
> Signed-off-by: Nikita Shubin <[email protected]>
> ---
> v4->v5:
> - changed EventCode to ConfigCode, as 63 bit exceeds event code
> format
> ---
> .../arch/riscv/riscv-sbi-firmware.json | 134
> ++++++++++++++++++
> 1 file changed, 134 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-
> firmware.json
>
> diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> new file mode 100644
> index 000000000000..b9d305f1ada8
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> @@ -0,0 +1,134 @@
> +[
> + {
> + "PublicDescription": "Misaligned load trap",
> + "ConfigCode": "0x8000000000000000",
> + "EventName": "FW_MISALIGNED_LOAD",
> + "BriefDescription": "Misaligned load trap event"
> + },
> + {
> + "PublicDescription": "Misaligned store trap",
> + "ConfigCode": "0x8000000000000001",
> + "EventName": "FW_MISALIGNED_STORE",
> + "BriefDescription": "Misaligned store trap event"
> + },
> + {
> + "PublicDescription": "Load access trap",
> + "ConfigCode": "0x8000000000000002",
> + "EventName": "FW_ACCESS_LOAD",
> + "BriefDescription": "Load access trap event"
> + },
> + {
> + "PublicDescription": "Store access trap",
> + "ConfigCode": "0x8000000000000003",
> + "EventName": "FW_ACCESS_STORE",
> + "BriefDescription": "Store access trap event"
> + },
> + {
> + "PublicDescription": "Illegal instruction trap",
> + "ConfigCode": "0x8000000000000004",
> + "EventName": "FW_ILLEGAL_INSN",
> + "BriefDescription": "Illegal instruction trap event"
> + },
> + {
> + "PublicDescription": "Set timer event",
> + "ConfigCode": "0x8000000000000005",
> + "EventName": "FW_SET_TIMER",
> + "BriefDescription": "Set timer event"
> + },
> + {
> + "PublicDescription": "Sent IPI to other HART event",
> + "ConfigCode": "0x8000000000000006",
> + "EventName": "FW_IPI_SENT",
> + "BriefDescription": "Sent IPI to other HART event"
> + },
> + {
> + "PublicDescription": "Received IPI from other HART event",
> + "ConfigCode": "0x8000000000000007",
> + "EventName": "FW_IPI_RECEIVED",
> + "BriefDescription": "Received IPI from other HART event"
> + },
> + {
> + "PublicDescription": "Sent FENCE.I request to other HART event",
> + "ConfigCode": "0x8000000000000008",
> + "EventName": "FW_FENCE_I_SENT",
> + "BriefDescription": "Sent FENCE.I request to other HART event"
> + },
> + {
> + "PublicDescription": "Received FENCE.I request from other HART
> event",
> + "ConfigCode": "0x8000000000000009",
> + "EventName": "FW_FENCE_I_RECEIVED",
> + "BriefDescription": "Received FENCE.I request from other HART
> event"
> + },
> + {
> + "PublicDescription": "Sent SFENCE.VMA request to other HART
> event",
> + "ConfigCode": "0x80000000000000a",
> + "EventName": "FW_SFENCE_VMA_SENT",
> + "BriefDescription": "Sent SFENCE.VMA request to other HART
> event"
> + },
> + {
> + "PublicDescription": "Received SFENCE.VMA request from other
> HART event",
> + "ConfigCode": "0x800000000000000b",
> + "EventName": "FW_SFENCE_VMA_RECEIVED",
> + "BriefDescription": "Received SFENCE.VMA request from other HART
> event"
> + },
> + {
> + "PublicDescription": "Sent SFENCE.VMA with ASID request to other
> HART event",
> + "ConfigCode": "0x800000000000000c",
> + "EventName": "FW_SFENCE_VMA_RECEIVED",
> + "BriefDescription": "Sent SFENCE.VMA with ASID request to other
> HART event"
> + },
> + {
> + "PublicDescription": "Received SFENCE.VMA with ASID request from
> other HART event",
> + "ConfigCode": "0x800000000000000d",
> + "EventName": "FW_SFENCE_VMA_ASID_RECEIVED",
> + "BriefDescription": "Received SFENCE.VMA with ASID request from
> other HART event"
> + },
> + {
> + "PublicDescription": "Sent HFENCE.GVMA request to other HART
> event",
> + "ConfigCode": "0x800000000000000e",
> + "EventName": "FW_HFENCE_GVMA_SENT",
> + "BriefDescription": "Sent HFENCE.GVMA request to other HART
> event"
> + },
> + {
> + "PublicDescription": "Received HFENCE.GVMA request from other
> HART event",
> + "ConfigCode": "0x800000000000000f",
> + "EventName": "FW_HFENCE_GVMA_RECEIVED",
> + "BriefDescription": "Received HFENCE.GVMA request from other
> HART event"
> + },
> + {
> + "PublicDescription": "Sent HFENCE.GVMA with VMID request to
> other HART event",
> + "ConfigCode": "0x8000000000000010",
> + "EventName": "FW_HFENCE_GVMA_VMID_SENT",
> + "BriefDescription": "Sent HFENCE.GVMA with VMID request to other
> HART event"
> + },
> + {
> + "PublicDescription": "Received HFENCE.GVMA with VMID request
> from other HART event",
> + "ConfigCode": "0x8000000000000011",
> + "EventName": "FW_HFENCE_GVMA_VMID_RECEIVED",
> + "BriefDescription": "Received HFENCE.GVMA with VMID request from
> other HART event"
> + },
> + {
> + "PublicDescription": "Sent HFENCE.VVMA request to other HART
> event",
> + "ConfigCode": "0x8000000000000012",
> + "EventName": "FW_HFENCE_VVMA_SENT",
> + "BriefDescription": "Sent HFENCE.VVMA request to other HART
> event"
> + },
> + {
> + "PublicDescription": "Received HFENCE.VVMA request from other
> HART event",
> + "ConfigCode": "0x8000000000000013",
> + "EventName": "FW_HFENCE_VVMA_RECEIVED",
> + "BriefDescription": "Received HFENCE.VVMA request from other
> HART event"
> + },
> + {
> + "PublicDescription": "Sent HFENCE.VVMA with ASID request to
> other HART event",
> + "ConfigCode": "0x8000000000000014",
> + "EventName": "FW_HFENCE_VVMA_ASID_SENT",
> + "BriefDescription": "Sent HFENCE.VVMA with ASID request to other
> HART event"
> + },
> + {
> + "PublicDescription": "Received HFENCE.VVMA with ASID request
> from other HART event",
> + "ConfigCode": "0x8000000000000015",
> + "EventName": "FW_HFENCE_VVMA_ASID_RECEIVED",
> + "BriefDescription": "Received HFENCE.VVMA with ASID request from
> other HART event"
> + }
> +]
When testing with perf using firmware events we saw this error:
WARNING: event 'N/A' not valid (bits 59 of config '80000000000000a' not
supported by kernel)!
It looks it is due to a typo and applying the below patch resolved the
issue for us.
Tested-by: Kautuk Consul <[email protected]>
diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
index b9d305f1ada8..a9939823b14b 100644
--- a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
+++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
@@ -61,7 +61,7 @@
},
{
"PublicDescription": "Sent SFENCE.VMA request to other HART
event",
- "ConfigCode": "0x80000000000000a",
+ "ConfigCode": "0x800000000000000a",
"EventName": "FW_SFENCE_VMA_SENT",
"BriefDescription": "Sent SFENCE.VMA request to other HART event"
},
Hello Mayuresh!
On Wed, 10 Aug 2022 20:26:18 +0530
Mayuresh Chitale <[email protected]> wrote:
> On Tue, 2022-06-28 at 14:45 +0300, Nikita Shubin wrote:
> > From: Nikita Shubin <[email protected]>
> >
> > Firmware events are defined by "RISC-V Supervisor Binary Interface
> > Specification", which means they should be always available as long
> > as
> > firmware supports >= 0.3.0 SBI.
> >
> > Expose them to arch std events, so they can be reused by particular
> > PMU bindings.
> >
> > Signed-off-by: Nikita Shubin <[email protected]>
> > ---
> > v4->v5:
> > - changed EventCode to ConfigCode, as 63 bit exceeds event code
> > format
> > ---
> > .../arch/riscv/riscv-sbi-firmware.json | 134
> > ++++++++++++++++++
> > 1 file changed, 134 insertions(+)
> > create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-
> > firmware.json
> >
> > diff --git
> > a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> > b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json new file
> > mode 100644 index 000000000000..b9d305f1ada8
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> > @@ -0,0 +1,134 @@
> > +[
> > + {
> > + "PublicDescription": "Misaligned load trap",
> > + "ConfigCode": "0x8000000000000000",
> > + "EventName": "FW_MISALIGNED_LOAD",
> > + "BriefDescription": "Misaligned load trap event"
> > + },
> > + {
> > + "PublicDescription": "Misaligned store trap",
> > + "ConfigCode": "0x8000000000000001",
> > + "EventName": "FW_MISALIGNED_STORE",
> > + "BriefDescription": "Misaligned store trap event"
> > + },
> > + {
> > + "PublicDescription": "Load access trap",
> > + "ConfigCode": "0x8000000000000002",
> > + "EventName": "FW_ACCESS_LOAD",
> > + "BriefDescription": "Load access trap event"
> > + },
> > + {
> > + "PublicDescription": "Store access trap",
> > + "ConfigCode": "0x8000000000000003",
> > + "EventName": "FW_ACCESS_STORE",
> > + "BriefDescription": "Store access trap event"
> > + },
> > + {
> > + "PublicDescription": "Illegal instruction trap",
> > + "ConfigCode": "0x8000000000000004",
> > + "EventName": "FW_ILLEGAL_INSN",
> > + "BriefDescription": "Illegal instruction trap event"
> > + },
> > + {
> > + "PublicDescription": "Set timer event",
> > + "ConfigCode": "0x8000000000000005",
> > + "EventName": "FW_SET_TIMER",
> > + "BriefDescription": "Set timer event"
> > + },
> > + {
> > + "PublicDescription": "Sent IPI to other HART event",
> > + "ConfigCode": "0x8000000000000006",
> > + "EventName": "FW_IPI_SENT",
> > + "BriefDescription": "Sent IPI to other HART event"
> > + },
> > + {
> > + "PublicDescription": "Received IPI from other HART event",
> > + "ConfigCode": "0x8000000000000007",
> > + "EventName": "FW_IPI_RECEIVED",
> > + "BriefDescription": "Received IPI from other HART event"
> > + },
> > + {
> > + "PublicDescription": "Sent FENCE.I request to other HART
> > event",
> > + "ConfigCode": "0x8000000000000008",
> > + "EventName": "FW_FENCE_I_SENT",
> > + "BriefDescription": "Sent FENCE.I request to other HART event"
> > + },
> > + {
> > + "PublicDescription": "Received FENCE.I request from other HART
> > event",
> > + "ConfigCode": "0x8000000000000009",
> > + "EventName": "FW_FENCE_I_RECEIVED",
> > + "BriefDescription": "Received FENCE.I request from other HART
> > event"
> > + },
> > + {
> > + "PublicDescription": "Sent SFENCE.VMA request to other HART
> > event",
> > + "ConfigCode": "0x80000000000000a",
> > + "EventName": "FW_SFENCE_VMA_SENT",
> > + "BriefDescription": "Sent SFENCE.VMA request to other HART
> > event"
> > + },
> > + {
> > + "PublicDescription": "Received SFENCE.VMA request from other
> > HART event",
> > + "ConfigCode": "0x800000000000000b",
> > + "EventName": "FW_SFENCE_VMA_RECEIVED",
> > + "BriefDescription": "Received SFENCE.VMA request from other
> > HART event"
> > + },
> > + {
> > + "PublicDescription": "Sent SFENCE.VMA with ASID request to
> > other HART event",
> > + "ConfigCode": "0x800000000000000c",
> > + "EventName": "FW_SFENCE_VMA_RECEIVED",
> > + "BriefDescription": "Sent SFENCE.VMA with ASID request to other
> > HART event"
> > + },
> > + {
> > + "PublicDescription": "Received SFENCE.VMA with ASID request
> > from other HART event",
> > + "ConfigCode": "0x800000000000000d",
> > + "EventName": "FW_SFENCE_VMA_ASID_RECEIVED",
> > + "BriefDescription": "Received SFENCE.VMA with ASID request from
> > other HART event"
> > + },
> > + {
> > + "PublicDescription": "Sent HFENCE.GVMA request to other HART
> > event",
> > + "ConfigCode": "0x800000000000000e",
> > + "EventName": "FW_HFENCE_GVMA_SENT",
> > + "BriefDescription": "Sent HFENCE.GVMA request to other HART
> > event"
> > + },
> > + {
> > + "PublicDescription": "Received HFENCE.GVMA request from other
> > HART event",
> > + "ConfigCode": "0x800000000000000f",
> > + "EventName": "FW_HFENCE_GVMA_RECEIVED",
> > + "BriefDescription": "Received HFENCE.GVMA request from other
> > HART event"
> > + },
> > + {
> > + "PublicDescription": "Sent HFENCE.GVMA with VMID request to
> > other HART event",
> > + "ConfigCode": "0x8000000000000010",
> > + "EventName": "FW_HFENCE_GVMA_VMID_SENT",
> > + "BriefDescription": "Sent HFENCE.GVMA with VMID request to
> > other HART event"
> > + },
> > + {
> > + "PublicDescription": "Received HFENCE.GVMA with VMID request
> > from other HART event",
> > + "ConfigCode": "0x8000000000000011",
> > + "EventName": "FW_HFENCE_GVMA_VMID_RECEIVED",
> > + "BriefDescription": "Received HFENCE.GVMA with VMID request
> > from other HART event"
> > + },
> > + {
> > + "PublicDescription": "Sent HFENCE.VVMA request to other HART
> > event",
> > + "ConfigCode": "0x8000000000000012",
> > + "EventName": "FW_HFENCE_VVMA_SENT",
> > + "BriefDescription": "Sent HFENCE.VVMA request to other HART
> > event"
> > + },
> > + {
> > + "PublicDescription": "Received HFENCE.VVMA request from other
> > HART event",
> > + "ConfigCode": "0x8000000000000013",
> > + "EventName": "FW_HFENCE_VVMA_RECEIVED",
> > + "BriefDescription": "Received HFENCE.VVMA request from other
> > HART event"
> > + },
> > + {
> > + "PublicDescription": "Sent HFENCE.VVMA with ASID request to
> > other HART event",
> > + "ConfigCode": "0x8000000000000014",
> > + "EventName": "FW_HFENCE_VVMA_ASID_SENT",
> > + "BriefDescription": "Sent HFENCE.VVMA with ASID request to
> > other HART event"
> > + },
> > + {
> > + "PublicDescription": "Received HFENCE.VVMA with ASID request
> > from other HART event",
> > + "ConfigCode": "0x8000000000000015",
> > + "EventName": "FW_HFENCE_VVMA_ASID_RECEIVED",
> > + "BriefDescription": "Received HFENCE.VVMA with ASID request
> > from other HART event"
> > + }
> > +]
>
> When testing with perf using firmware events we saw this error:
> WARNING: event 'N/A' not valid (bits 59 of config '80000000000000a'
> not supported by kernel)!
>
> It looks it is due to a typo and applying the below patch resolved the
> issue for us.
Thanks for catching this - indeed this is a correct fix.
>
> Tested-by: Kautuk Consul <[email protected]>
Thank you for testing!
Yours,
Nikita Shubin.
>
> diff --git a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> index b9d305f1ada8..a9939823b14b 100644
> --- a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> @@ -61,7 +61,7 @@
> },
> {
> "PublicDescription": "Sent SFENCE.VMA request to other HART
> event",
> - "ConfigCode": "0x80000000000000a",
> + "ConfigCode": "0x800000000000000a",
> "EventName": "FW_SFENCE_VMA_SENT",
> "BriefDescription": "Sent SFENCE.VMA request to other HART event"
> },
>
>
>
Em Thu, Aug 11, 2022 at 11:23:03AM +0300, Nikita Shubin escreveu:
> Hello Mayuresh!
>
> On Wed, 10 Aug 2022 20:26:18 +0530
> Mayuresh Chitale <[email protected]> wrote:
>
> > On Tue, 2022-06-28 at 14:45 +0300, Nikita Shubin wrote:
> > > From: Nikita Shubin <[email protected]>
> > >
> > > Firmware events are defined by "RISC-V Supervisor Binary Interface
> > > Specification", which means they should be always available as long
> > > as
> > > firmware supports >= 0.3.0 SBI.
> > >
> > > Expose them to arch std events, so they can be reused by particular
> > > PMU bindings.
> > >
> > > Signed-off-by: Nikita Shubin <[email protected]>
> > > ---
> > > v4->v5:
> > > - changed EventCode to ConfigCode, as 63 bit exceeds event code
> > > format
> > > ---
> > > .../arch/riscv/riscv-sbi-firmware.json | 134
> > > ++++++++++++++++++
> > > 1 file changed, 134 insertions(+)
> > > create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-
> > > firmware.json
> > >
> > > diff --git
> > > a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> > > b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json new file
> > > mode 100644 index 000000000000..b9d305f1ada8
> > > --- /dev/null
> > > +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> > > @@ -0,0 +1,134 @@
> > > +[
> > > + {
> > > + "PublicDescription": "Misaligned load trap",
> > > + "ConfigCode": "0x8000000000000000",
> > > + "EventName": "FW_MISALIGNED_LOAD",
> > > + "BriefDescription": "Misaligned load trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Misaligned store trap",
> > > + "ConfigCode": "0x8000000000000001",
> > > + "EventName": "FW_MISALIGNED_STORE",
> > > + "BriefDescription": "Misaligned store trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Load access trap",
> > > + "ConfigCode": "0x8000000000000002",
> > > + "EventName": "FW_ACCESS_LOAD",
> > > + "BriefDescription": "Load access trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Store access trap",
> > > + "ConfigCode": "0x8000000000000003",
> > > + "EventName": "FW_ACCESS_STORE",
> > > + "BriefDescription": "Store access trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Illegal instruction trap",
> > > + "ConfigCode": "0x8000000000000004",
> > > + "EventName": "FW_ILLEGAL_INSN",
> > > + "BriefDescription": "Illegal instruction trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Set timer event",
> > > + "ConfigCode": "0x8000000000000005",
> > > + "EventName": "FW_SET_TIMER",
> > > + "BriefDescription": "Set timer event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent IPI to other HART event",
> > > + "ConfigCode": "0x8000000000000006",
> > > + "EventName": "FW_IPI_SENT",
> > > + "BriefDescription": "Sent IPI to other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received IPI from other HART event",
> > > + "ConfigCode": "0x8000000000000007",
> > > + "EventName": "FW_IPI_RECEIVED",
> > > + "BriefDescription": "Received IPI from other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent FENCE.I request to other HART
> > > event",
> > > + "ConfigCode": "0x8000000000000008",
> > > + "EventName": "FW_FENCE_I_SENT",
> > > + "BriefDescription": "Sent FENCE.I request to other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received FENCE.I request from other HART
> > > event",
> > > + "ConfigCode": "0x8000000000000009",
> > > + "EventName": "FW_FENCE_I_RECEIVED",
> > > + "BriefDescription": "Received FENCE.I request from other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent SFENCE.VMA request to other HART
> > > event",
> > > + "ConfigCode": "0x80000000000000a",
> > > + "EventName": "FW_SFENCE_VMA_SENT",
> > > + "BriefDescription": "Sent SFENCE.VMA request to other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received SFENCE.VMA request from other
> > > HART event",
> > > + "ConfigCode": "0x800000000000000b",
> > > + "EventName": "FW_SFENCE_VMA_RECEIVED",
> > > + "BriefDescription": "Received SFENCE.VMA request from other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent SFENCE.VMA with ASID request to
> > > other HART event",
> > > + "ConfigCode": "0x800000000000000c",
> > > + "EventName": "FW_SFENCE_VMA_RECEIVED",
> > > + "BriefDescription": "Sent SFENCE.VMA with ASID request to other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received SFENCE.VMA with ASID request
> > > from other HART event",
> > > + "ConfigCode": "0x800000000000000d",
> > > + "EventName": "FW_SFENCE_VMA_ASID_RECEIVED",
> > > + "BriefDescription": "Received SFENCE.VMA with ASID request from
> > > other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.GVMA request to other HART
> > > event",
> > > + "ConfigCode": "0x800000000000000e",
> > > + "EventName": "FW_HFENCE_GVMA_SENT",
> > > + "BriefDescription": "Sent HFENCE.GVMA request to other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.GVMA request from other
> > > HART event",
> > > + "ConfigCode": "0x800000000000000f",
> > > + "EventName": "FW_HFENCE_GVMA_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.GVMA request from other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.GVMA with VMID request to
> > > other HART event",
> > > + "ConfigCode": "0x8000000000000010",
> > > + "EventName": "FW_HFENCE_GVMA_VMID_SENT",
> > > + "BriefDescription": "Sent HFENCE.GVMA with VMID request to
> > > other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.GVMA with VMID request
> > > from other HART event",
> > > + "ConfigCode": "0x8000000000000011",
> > > + "EventName": "FW_HFENCE_GVMA_VMID_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.GVMA with VMID request
> > > from other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.VVMA request to other HART
> > > event",
> > > + "ConfigCode": "0x8000000000000012",
> > > + "EventName": "FW_HFENCE_VVMA_SENT",
> > > + "BriefDescription": "Sent HFENCE.VVMA request to other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.VVMA request from other
> > > HART event",
> > > + "ConfigCode": "0x8000000000000013",
> > > + "EventName": "FW_HFENCE_VVMA_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.VVMA request from other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.VVMA with ASID request to
> > > other HART event",
> > > + "ConfigCode": "0x8000000000000014",
> > > + "EventName": "FW_HFENCE_VVMA_ASID_SENT",
> > > + "BriefDescription": "Sent HFENCE.VVMA with ASID request to
> > > other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.VVMA with ASID request
> > > from other HART event",
> > > + "ConfigCode": "0x8000000000000015",
> > > + "EventName": "FW_HFENCE_VVMA_ASID_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.VVMA with ASID request
> > > from other HART event"
> > > + }
> > > +]
> >
> > When testing with perf using firmware events we saw this error:
> > WARNING: event 'N/A' not valid (bits 59 of config '80000000000000a'
> > not supported by kernel)!
> >
> > It looks it is due to a typo and applying the below patch resolved the
> > issue for us.
>
> Thanks for catching this - indeed this is a correct fix.
>
> >
> > Tested-by: Kautuk Consul <[email protected]>
>
> Thank you for testing!
Can you please resubmit with the fixes, rebased to the current
acme/perf/core branch?
If I get this today it may even get into v6.0. :-)
Thanks,
- Arnaldo
Hello Arnaldo!
> If I get this today it may even get into v6.0. :-)
>
> Thanks,
>
> - Arnaldo
Well... i missed it :), on the other hand this series depends on
https://lkml.org/lkml/2022/7/27/23
which hasn't been merged yet.
Just have sent a v6 series.
Thank you for review!
Yours,
Nikita Shubin
Em Mon, Aug 15, 2022 at 04:27:55PM +0300, Nikita Shubin escreveu:
> > If I get this today it may even get into v6.0. :-)
> Well... i missed it :), on the other hand this series depends on
> https://lkml.org/lkml/2022/7/27/23
> which hasn't been merged yet.
> Just have sent a v6 series.
> Thank you for review!
Ok! Hopefully it'll make 6.1 then. :-)
- Arnaldo