This series implements Sstc extension support which was ratified recently.
Before the Sstc extension, an SBI call is necessary to generate timer
interrupts as only M-mode have access to the timecompare registers. Thus,
there is significant latency to generate timer interrupts at kernel.
For virtualized enviornments, its even worse as the KVM handles the SBI call
and uses a software timer to emulate the timecomapre register.
Sstc extension solves both these problems by defining a stimecmp/vstimecmp
at supervisor (host/guest) level. It allows kernel to program a timer and
recieve interrupt without supervisor execution enviornment (M-mode/HS mode)
intervention.
To maintain backward compatibility, KVM directly updates the vstimecmp
if older kernel without sstc support is running in guest. Similary, the
M-mode firmware(OpenSBI) uses stimecmp for older kernel without sstc support.
The PATCH 1 & 2 enables the basic infrastructure around Sstc extension while
PATCH 3 lets kernel use the Sstc extension if it is available in hardware.
PATCH 4 implements the Sstc extension in KVM.
This series has been tested on Qemu(RV32 & RV64) with additional patches in
OpenSBI[2] and Qemu[3]. This series can also be found at [4].
Changes from v2->v3:
1. Dropped unrelated KVM fixes from this series.
2. Rebased on 5.18-rc3.
Changes from v1->v2:
1. Separate the static key from kvm usage
2. Makde the sstc specific static key local to the driver/clocksource
3. Moved the vstimecmp update code to the vcpu_timer
4. Used function pointers instead of static key to invoke vstimecmp vs
hrtimer at the run time. This will help in future for migration of vms
from/to sstc enabled hardware to non-sstc enabled hardware.
5. Unified the vstimer & timer to 1 timer as only one of them will be used
at runtime.
[1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view
[2] https://github.com/atishp04/opensbi/tree/sstc_v2
[3] https://github.com/atishp04/qemu/tree/sstc_v2
[3] https://github.com/atishp04/linux/tree/sstc_v3
Atish Patra (4):
RISC-V: Add SSTC extension CSR details
RISC-V: Enable sstc extension parsing from DT
RISC-V: Prefer sstc extension if available
RISC-V: KVM: Support sstc extension
arch/riscv/include/asm/csr.h | 11 ++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/kvm_host.h | 1 +
arch/riscv/include/asm/kvm_vcpu_timer.h | 8 +-
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
arch/riscv/kvm/main.c | 12 ++-
arch/riscv/kvm/vcpu.c | 5 +-
arch/riscv/kvm/vcpu_timer.c | 138 +++++++++++++++++++++++-
drivers/clocksource/timer-riscv.c | 21 +++-
11 files changed, 193 insertions(+), 7 deletions(-)
--
2.25.1
The ISA extension framework now allows parsing any multi-letter
ISA extension.
Enable that for sstc extension.
Signed-off-by: Atish Patra <[email protected]>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 0734e42f74f2..25915eb60d61 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -52,6 +52,7 @@ extern unsigned long elf_hwcap;
*/
enum riscv_isa_ext_id {
RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
+ RISCV_ISA_EXT_SSTC,
RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index ccb617791e56..ca0e4c0db17e 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node)
*/
static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
+ __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
};
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1b2d42d7f589..a214537c22f1 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -192,6 +192,7 @@ void __init riscv_fill_hwcap(void)
set_bit(*ext - 'a', this_isa);
} else {
SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
+ SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
}
#undef SET_ISA_EXT_MAP
}
--
2.25.1
Sstc extension allows the guest to program the vstimecmp CSR directly
instead of making an SBI call to the hypervisor to program the next
event. The timer interrupt is also directly injected to the guest by
the hardware in this case. To maintain backward compatibility, the
hypervisors also update the vstimecmp in an SBI set_time call if
the hardware supports it. Thus, the older kernels in guest also
take advantage of the sstc extension.
Signed-off-by: Atish Patra <[email protected]>
---
arch/riscv/include/asm/kvm_host.h | 1 +
arch/riscv/include/asm/kvm_vcpu_timer.h | 8 +-
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/main.c | 12 ++-
arch/riscv/kvm/vcpu.c | 5 +-
arch/riscv/kvm/vcpu_timer.c | 138 +++++++++++++++++++++++-
6 files changed, 159 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
index 78da839657e5..50a97c821f83 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -135,6 +135,7 @@ struct kvm_vcpu_csr {
unsigned long hvip;
unsigned long vsatp;
unsigned long scounteren;
+ u64 vstimecmp;
};
struct kvm_vcpu_arch {
diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h
index 375281eb49e0..a24a265f3ccb 100644
--- a/arch/riscv/include/asm/kvm_vcpu_timer.h
+++ b/arch/riscv/include/asm/kvm_vcpu_timer.h
@@ -28,6 +28,11 @@ struct kvm_vcpu_timer {
u64 next_cycles;
/* Underlying hrtimer instance */
struct hrtimer hrt;
+
+ /* Flag to check if sstc is enabled or not */
+ bool sstc_enabled;
+ /* A function pointer to switch between stimecmp or hrtimer at runtime */
+ int (*timer_next_event)(struct kvm_vcpu *vcpu, u64 ncycles);
};
int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles);
@@ -39,6 +44,7 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu);
int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu);
int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu);
void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu);
+void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu);
int kvm_riscv_guest_timer_init(struct kvm *kvm);
-
+bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu);
#endif
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 92bd469e2ba6..d2f02ba1947a 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -96,6 +96,7 @@ enum KVM_RISCV_ISA_EXT_ID {
KVM_RISCV_ISA_EXT_H,
KVM_RISCV_ISA_EXT_I,
KVM_RISCV_ISA_EXT_M,
+ KVM_RISCV_ISA_EXT_SSTC,
KVM_RISCV_ISA_EXT_MAX,
};
diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
index 2e5ca43c8c49..83c4db7fc35f 100644
--- a/arch/riscv/kvm/main.c
+++ b/arch/riscv/kvm/main.c
@@ -32,7 +32,7 @@ int kvm_arch_hardware_setup(void *opaque)
int kvm_arch_hardware_enable(void)
{
- unsigned long hideleg, hedeleg;
+ unsigned long hideleg, hedeleg, henvcfg;
hedeleg = 0;
hedeleg |= (1UL << EXC_INST_MISALIGNED);
@@ -51,6 +51,16 @@ int kvm_arch_hardware_enable(void)
csr_write(CSR_HCOUNTEREN, -1UL);
+ if (riscv_isa_extension_available(NULL, SSTC)) {
+#ifdef CONFIG_64BIT
+ henvcfg = csr_read(CSR_HENVCFG);
+ csr_write(CSR_HENVCFG, henvcfg | 1UL<<HENVCFG_STCE);
+#else
+ henvcfg = csr_read(CSR_HENVCFGH);
+ csr_write(CSR_HENVCFGH, henvcfg | 1UL<<HENVCFGH_STCE);
+#endif
+ }
+
csr_write(CSR_HVIP, 0);
return 0;
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 93492eb292fd..da1559725b03 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -143,7 +143,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
{
- return kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER);
+ return kvm_riscv_vcpu_timer_pending(vcpu);
}
void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
@@ -374,6 +374,7 @@ static unsigned long kvm_isa_ext_arr[] = {
RISCV_ISA_EXT_h,
RISCV_ISA_EXT_i,
RISCV_ISA_EXT_m,
+ RISCV_ISA_EXT_SSTC,
};
static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
@@ -754,6 +755,8 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
vcpu->arch.isa);
kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);
+ kvm_riscv_vcpu_timer_save(vcpu);
+
csr->vsstatus = csr_read(CSR_VSSTATUS);
csr->vsie = csr_read(CSR_VSIE);
csr->vstvec = csr_read(CSR_VSTVEC);
diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c
index 5c4c37ff2d48..d226a931de92 100644
--- a/arch/riscv/kvm/vcpu_timer.c
+++ b/arch/riscv/kvm/vcpu_timer.c
@@ -69,7 +69,18 @@ static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t)
return 0;
}
-int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
+static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles)
+{
+#if __riscv_xlen == 32
+ csr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF);
+ csr_write(CSR_VSTIMECMPH, ncycles >> 32);
+#else
+ csr_write(CSR_VSTIMECMP, ncycles);
+#endif
+ return 0;
+}
+
+static int kvm_riscv_vcpu_update_hrtimer(struct kvm_vcpu *vcpu, u64 ncycles)
{
struct kvm_vcpu_timer *t = &vcpu->arch.timer;
struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
@@ -88,6 +99,68 @@ int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
return 0;
}
+int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
+{
+ struct kvm_vcpu_timer *t = &vcpu->arch.timer;
+
+ return t->timer_next_event(vcpu, ncycles);
+}
+
+static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer *h)
+{
+ u64 delta_ns;
+ struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt);
+ struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer);
+ struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
+
+ if (kvm_riscv_current_cycles(gt) < t->next_cycles) {
+ delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t);
+ hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns));
+ return HRTIMER_RESTART;
+ }
+
+ t->next_set = false;
+ kvm_vcpu_kick(vcpu);
+
+ return HRTIMER_NORESTART;
+}
+
+bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_timer *t = &vcpu->arch.timer;
+ struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
+ u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp;
+
+ if (!kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t) ||
+ kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER))
+ return true;
+ else
+ return false;
+}
+
+static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_timer *t = &vcpu->arch.timer;
+ struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
+ u64 delta_ns;
+ u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp;
+
+ if (!t->init_done)
+ return;
+
+ delta_ns = kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t);
+ if (delta_ns) {
+ t->next_cycles = vstimecmp_val;
+ hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL);
+ t->next_set = true;
+ }
+}
+
+static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu)
+{
+ kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
+}
+
int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu,
const struct kvm_one_reg *reg)
{
@@ -180,10 +253,20 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu)
return -EINVAL;
hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
- t->hrt.function = kvm_riscv_vcpu_hrtimer_expired;
t->init_done = true;
t->next_set = false;
+ /* Enable sstc for every vcpu if available in hardware */
+ if (riscv_isa_extension_available(NULL, SSTC)) {
+ t->sstc_enabled = true;
+ t->hrt.function = kvm_riscv_vcpu_vstimer_expired;
+ t->timer_next_event = kvm_riscv_vcpu_update_vstimecmp;
+ } else {
+ t->sstc_enabled = false;
+ t->hrt.function = kvm_riscv_vcpu_hrtimer_expired;
+ t->timer_next_event = kvm_riscv_vcpu_update_hrtimer;
+ }
+
return 0;
}
@@ -202,7 +285,7 @@ int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu)
return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
}
-void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
+static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu)
{
struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
@@ -214,6 +297,55 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
#endif
}
+void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_csr *csr;
+ struct kvm_vcpu_timer *t = &vcpu->arch.timer;
+
+ kvm_riscv_vcpu_update_timedelta(vcpu);
+
+ if (!t->sstc_enabled)
+ return;
+
+ csr = &vcpu->arch.guest_csr;
+#ifdef CONFIG_64BIT
+ csr_write(CSR_VSTIMECMP, csr->vstimecmp);
+#else
+ csr_write(CSR_VSTIMECMP, (u32)csr->vstimecmp);
+ csr_write(CSR_VSTIMECMPH, (u32)(csr->vstimecmp >> 32));
+#endif
+
+ /* timer should be enabled for the remaining operations */
+ if (unlikely(!t->init_done))
+ return;
+
+ kvm_riscv_vcpu_timer_unblocking(vcpu);
+}
+
+void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu)
+{
+ struct kvm_vcpu_csr *csr;
+ struct kvm_vcpu_timer *t = &vcpu->arch.timer;
+
+ if (!t->sstc_enabled)
+ return;
+
+ csr = &vcpu->arch.guest_csr;
+ t = &vcpu->arch.timer;
+#ifdef CONFIG_64BIT
+ csr->vstimecmp = csr_read(CSR_VSTIMECMP);
+#else
+ csr->vstimecmp = csr_read(CSR_VSTIMECMP);
+ csr->vstimecmp |= (u64)csr_read(CSR_VSTIMECMPH) << 32;
+#endif
+ /* timer should be enabled for the remaining operations */
+ if (unlikely(!t->init_done))
+ return;
+
+ if (kvm_vcpu_is_blocking(vcpu))
+ kvm_riscv_vcpu_timer_blocking(vcpu);
+}
+
int kvm_riscv_guest_timer_init(struct kvm *kvm)
{
struct kvm_guest_timer *gt = &kvm->arch.timer;
--
2.25.1
This patch just introduces the required CSR fields related to the
SSTC extension.
Signed-off-by: Atish Patra <[email protected]>
---
arch/riscv/include/asm/csr.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index e935f27b10fd..10f4e1c36908 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -227,6 +227,9 @@
#define CSR_SIP 0x144
#define CSR_SATP 0x180
+#define CSR_STIMECMP 0x14D
+#define CSR_STIMECMPH 0x15D
+
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
#define CSR_VSTVEC 0x205
@@ -236,6 +239,8 @@
#define CSR_VSTVAL 0x243
#define CSR_VSIP 0x244
#define CSR_VSATP 0x280
+#define CSR_VSTIMECMP 0x24D
+#define CSR_VSTIMECMPH 0x25D
#define CSR_HSTATUS 0x600
#define CSR_HEDELEG 0x602
@@ -251,6 +256,8 @@
#define CSR_HTINST 0x64a
#define CSR_HGATP 0x680
#define CSR_HGEIP 0xe12
+#define CSR_HENVCFG 0x60A
+#define CSR_HENVCFGH 0x61A
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
@@ -312,6 +319,10 @@
#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
+/* ENVCFG related bits */
+#define HENVCFG_STCE 63
+#define HENVCFGH_STCE 31
+
#ifndef __ASSEMBLY__
#define csr_swap(csr, val) \
--
2.25.1
RISC-V ISA has sstc extension which allows updating the next clock event
via a CSR (stimecmp) instead of an SBI call. This should happen dynamically
if sstc extension is available. Otherwise, it will fallback to SBI call
to maintain backward compatibility.
Signed-off-by: Atish Patra <[email protected]>
---
drivers/clocksource/timer-riscv.c | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 1767f8bf2013..d9398ae84a20 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -23,11 +23,24 @@
#include <asm/sbi.h>
#include <asm/timex.h>
+static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
+
static int riscv_clock_next_event(unsigned long delta,
struct clock_event_device *ce)
{
+ uint64_t next_tval = get_cycles64() + delta;
+
csr_set(CSR_IE, IE_TIE);
- sbi_set_timer(get_cycles64() + delta);
+ if (static_branch_likely(&riscv_sstc_available)) {
+#if __riscv_xlen == 32
+ csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
+ csr_write(CSR_STIMECMPH, next_tval >> 32);
+#else
+ csr_write(CSR_STIMECMP, next_tval);
+#endif
+ } else
+ sbi_set_timer(next_tval);
+
return 0;
}
@@ -165,6 +178,12 @@ static int __init riscv_timer_init_dt(struct device_node *n)
if (error)
pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
error);
+
+ if (riscv_isa_extension_available(NULL, SSTC)) {
+ pr_info("Timer interrupt in S-mode is available via sstc extension\n");
+ static_branch_enable(&riscv_sstc_available);
+ }
+
return error;
}
--
2.25.1
On 26 Apr 2022, at 19:52, Atish Patra <[email protected]> wrote:
>
> Sstc extension allows the guest to program the vstimecmp CSR directly
> instead of making an SBI call to the hypervisor to program the next
> event. The timer interrupt is also directly injected to the guest by
> the hardware in this case. To maintain backward compatibility, the
> hypervisors also update the vstimecmp in an SBI set_time call if
> the hardware supports it. Thus, the older kernels in guest also
> take advantage of the sstc extension.
This still violates the following part of the ratified SBI spec:
> • All registers except a0 & a1 must be preserved across an SBI call by the callee.
The Set Timer legacy extension and non-legacy function state they clear
the pending timer bit but otherwise make no provision for other S-mode
state being clobbered. The stimecmp register is S-mode read/write
state. I don’t debate that this is a useful thing to allow, but as
things stand this is in direct violation of the letter of the ratified
SBI spec and so if you want to allow this you have to fix your spec
first and deal with the ratified spec compatibility issues that brings.
Jess
> Signed-off-by: Atish Patra <[email protected]>
> ---
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/include/asm/kvm_vcpu_timer.h | 8 +-
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/main.c | 12 ++-
> arch/riscv/kvm/vcpu.c | 5 +-
> arch/riscv/kvm/vcpu_timer.c | 138 +++++++++++++++++++++++-
> 6 files changed, 159 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 78da839657e5..50a97c821f83 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -135,6 +135,7 @@ struct kvm_vcpu_csr {
> unsigned long hvip;
> unsigned long vsatp;
> unsigned long scounteren;
> + u64 vstimecmp;
> };
>
> struct kvm_vcpu_arch {
> diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h
> index 375281eb49e0..a24a265f3ccb 100644
> --- a/arch/riscv/include/asm/kvm_vcpu_timer.h
> +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h
> @@ -28,6 +28,11 @@ struct kvm_vcpu_timer {
> u64 next_cycles;
> /* Underlying hrtimer instance */
> struct hrtimer hrt;
> +
> + /* Flag to check if sstc is enabled or not */
> + bool sstc_enabled;
> + /* A function pointer to switch between stimecmp or hrtimer at runtime */
> + int (*timer_next_event)(struct kvm_vcpu *vcpu, u64 ncycles);
> };
>
> int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles);
> @@ -39,6 +44,7 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu);
> int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu);
> int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu);
> void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu);
> +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu);
> int kvm_riscv_guest_timer_init(struct kvm *kvm);
> -
> +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu);
> #endif
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 92bd469e2ba6..d2f02ba1947a 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -96,6 +96,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_H,
> KVM_RISCV_ISA_EXT_I,
> KVM_RISCV_ISA_EXT_M,
> + KVM_RISCV_ISA_EXT_SSTC,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
> index 2e5ca43c8c49..83c4db7fc35f 100644
> --- a/arch/riscv/kvm/main.c
> +++ b/arch/riscv/kvm/main.c
> @@ -32,7 +32,7 @@ int kvm_arch_hardware_setup(void *opaque)
>
> int kvm_arch_hardware_enable(void)
> {
> - unsigned long hideleg, hedeleg;
> + unsigned long hideleg, hedeleg, henvcfg;
>
> hedeleg = 0;
> hedeleg |= (1UL << EXC_INST_MISALIGNED);
> @@ -51,6 +51,16 @@ int kvm_arch_hardware_enable(void)
>
> csr_write(CSR_HCOUNTEREN, -1UL);
>
> + if (riscv_isa_extension_available(NULL, SSTC)) {
> +#ifdef CONFIG_64BIT
> + henvcfg = csr_read(CSR_HENVCFG);
> + csr_write(CSR_HENVCFG, henvcfg | 1UL<<HENVCFG_STCE);
> +#else
> + henvcfg = csr_read(CSR_HENVCFGH);
> + csr_write(CSR_HENVCFGH, henvcfg | 1UL<<HENVCFGH_STCE);
> +#endif
> + }
> +
> csr_write(CSR_HVIP, 0);
>
> return 0;
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 93492eb292fd..da1559725b03 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -143,7 +143,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
>
> int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
> {
> - return kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER);
> + return kvm_riscv_vcpu_timer_pending(vcpu);
> }
>
> void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
> @@ -374,6 +374,7 @@ static unsigned long kvm_isa_ext_arr[] = {
> RISCV_ISA_EXT_h,
> RISCV_ISA_EXT_i,
> RISCV_ISA_EXT_m,
> + RISCV_ISA_EXT_SSTC,
> };
>
> static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
> @@ -754,6 +755,8 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
> vcpu->arch.isa);
> kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);
>
> + kvm_riscv_vcpu_timer_save(vcpu);
> +
> csr->vsstatus = csr_read(CSR_VSSTATUS);
> csr->vsie = csr_read(CSR_VSIE);
> csr->vstvec = csr_read(CSR_VSTVEC);
> diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c
> index 5c4c37ff2d48..d226a931de92 100644
> --- a/arch/riscv/kvm/vcpu_timer.c
> +++ b/arch/riscv/kvm/vcpu_timer.c
> @@ -69,7 +69,18 @@ static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t)
> return 0;
> }
>
> -int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
> +static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles)
> +{
> +#if __riscv_xlen == 32
> + csr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF);
> + csr_write(CSR_VSTIMECMPH, ncycles >> 32);
> +#else
> + csr_write(CSR_VSTIMECMP, ncycles);
> +#endif
> + return 0;
> +}
> +
> +static int kvm_riscv_vcpu_update_hrtimer(struct kvm_vcpu *vcpu, u64 ncycles)
> {
> struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> @@ -88,6 +99,68 @@ int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
> return 0;
> }
>
> +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
> +{
> + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> +
> + return t->timer_next_event(vcpu, ncycles);
> +}
> +
> +static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer *h)
> +{
> + u64 delta_ns;
> + struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt);
> + struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer);
> + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> +
> + if (kvm_riscv_current_cycles(gt) < t->next_cycles) {
> + delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t);
> + hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns));
> + return HRTIMER_RESTART;
> + }
> +
> + t->next_set = false;
> + kvm_vcpu_kick(vcpu);
> +
> + return HRTIMER_NORESTART;
> +}
> +
> +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp;
> +
> + if (!kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t) ||
> + kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER))
> + return true;
> + else
> + return false;
> +}
> +
> +static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> + u64 delta_ns;
> + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp;
> +
> + if (!t->init_done)
> + return;
> +
> + delta_ns = kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t);
> + if (delta_ns) {
> + t->next_cycles = vstimecmp_val;
> + hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL);
> + t->next_set = true;
> + }
> +}
> +
> +static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu)
> +{
> + kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
> +}
> +
> int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> @@ -180,10 +253,20 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu)
> return -EINVAL;
>
> hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
> - t->hrt.function = kvm_riscv_vcpu_hrtimer_expired;
> t->init_done = true;
> t->next_set = false;
>
> + /* Enable sstc for every vcpu if available in hardware */
> + if (riscv_isa_extension_available(NULL, SSTC)) {
> + t->sstc_enabled = true;
> + t->hrt.function = kvm_riscv_vcpu_vstimer_expired;
> + t->timer_next_event = kvm_riscv_vcpu_update_vstimecmp;
> + } else {
> + t->sstc_enabled = false;
> + t->hrt.function = kvm_riscv_vcpu_hrtimer_expired;
> + t->timer_next_event = kvm_riscv_vcpu_update_hrtimer;
> + }
> +
> return 0;
> }
>
> @@ -202,7 +285,7 @@ int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu)
> return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
> }
>
> -void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
> +static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu)
> {
> struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
>
> @@ -214,6 +297,55 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
> #endif
> }
>
> +void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_vcpu_csr *csr;
> + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> +
> + kvm_riscv_vcpu_update_timedelta(vcpu);
> +
> + if (!t->sstc_enabled)
> + return;
> +
> + csr = &vcpu->arch.guest_csr;
> +#ifdef CONFIG_64BIT
> + csr_write(CSR_VSTIMECMP, csr->vstimecmp);
> +#else
> + csr_write(CSR_VSTIMECMP, (u32)csr->vstimecmp);
> + csr_write(CSR_VSTIMECMPH, (u32)(csr->vstimecmp >> 32));
> +#endif
> +
> + /* timer should be enabled for the remaining operations */
> + if (unlikely(!t->init_done))
> + return;
> +
> + kvm_riscv_vcpu_timer_unblocking(vcpu);
> +}
> +
> +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_vcpu_csr *csr;
> + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> +
> + if (!t->sstc_enabled)
> + return;
> +
> + csr = &vcpu->arch.guest_csr;
> + t = &vcpu->arch.timer;
> +#ifdef CONFIG_64BIT
> + csr->vstimecmp = csr_read(CSR_VSTIMECMP);
> +#else
> + csr->vstimecmp = csr_read(CSR_VSTIMECMP);
> + csr->vstimecmp |= (u64)csr_read(CSR_VSTIMECMPH) << 32;
> +#endif
> + /* timer should be enabled for the remaining operations */
> + if (unlikely(!t->init_done))
> + return;
> +
> + if (kvm_vcpu_is_blocking(vcpu))
> + kvm_riscv_vcpu_timer_blocking(vcpu);
> +}
> +
> int kvm_riscv_guest_timer_init(struct kvm *kvm)
> {
> struct kvm_guest_timer *gt = &kvm->arch.timer;
> --
> 2.25.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Tue, Apr 26, 2022 at 2:10 PM Jessica Clarke <[email protected]> wrote:
>
> On 26 Apr 2022, at 19:52, Atish Patra <[email protected]> wrote:
> >
> > Sstc extension allows the guest to program the vstimecmp CSR directly
> > instead of making an SBI call to the hypervisor to program the next
> > event. The timer interrupt is also directly injected to the guest by
> > the hardware in this case. To maintain backward compatibility, the
> > hypervisors also update the vstimecmp in an SBI set_time call if
> > the hardware supports it. Thus, the older kernels in guest also
> > take advantage of the sstc extension.
>
> This still violates the following part of the ratified SBI spec:
>
> > • All registers except a0 & a1 must be preserved across an SBI call by the callee.
>
> The Set Timer legacy extension and non-legacy function state they clear
> the pending timer bit but otherwise make no provision for other S-mode
> state being clobbered. The stimecmp register is S-mode read/write
> state. I don’t debate that this is a useful thing to allow, but as
> things stand this is in direct violation of the letter of the ratified
> SBI spec and so if you want to allow this you have to fix your spec
> first and deal with the ratified spec compatibility issues that brings.
>
I tried the approach you suggested by keeping separate context for
SBI path & vstimecmp but this results in in unreliable behavior for
guest (which may use SBI call or stimecmp) because hardware will always
trigger virtual timer interrupt whenever henvcfg.STCE==1 and
"vstimecmp < (time+ htimedelta)".
Further, the hypervisor has no idea if the guest wants Sstc extension
or not unless the hypervisor management tool (QEMU/KVMTOOL)
explicitly disables the Sstc extension for a specific Guest/VM. In
general, the hypervisor management tools can't assume anything
about the features supported by Guest OS so explicitly disabling
Sstc extension for Guest/VM is not a practical approach.
Most hypervisors will always have Sstc extension enabled by default
for Guest/VM by setting the henvcfg.STCE bit whenever hardware
supports Sstc. Once this bit is set, hardware will actively compare
vstimecmp value at every CPU clock cycle. vstimecmp value need to be
saved/restored at vcpu_load/put path always. If the vstimecmp is not
updated in the SBI path, it may contain stale value which will trigger
spurious timer interrupts.
Regards,
Anup
> Jess
>
> > Signed-off-by: Atish Patra <[email protected]>
> > ---
> > arch/riscv/include/asm/kvm_host.h | 1 +
> > arch/riscv/include/asm/kvm_vcpu_timer.h | 8 +-
> > arch/riscv/include/uapi/asm/kvm.h | 1 +
> > arch/riscv/kvm/main.c | 12 ++-
> > arch/riscv/kvm/vcpu.c | 5 +-
> > arch/riscv/kvm/vcpu_timer.c | 138 +++++++++++++++++++++++-
> > 6 files changed, 159 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> > index 78da839657e5..50a97c821f83 100644
> > --- a/arch/riscv/include/asm/kvm_host.h
> > +++ b/arch/riscv/include/asm/kvm_host.h
> > @@ -135,6 +135,7 @@ struct kvm_vcpu_csr {
> > unsigned long hvip;
> > unsigned long vsatp;
> > unsigned long scounteren;
> > + u64 vstimecmp;
> > };
> >
> > struct kvm_vcpu_arch {
> > diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h
> > index 375281eb49e0..a24a265f3ccb 100644
> > --- a/arch/riscv/include/asm/kvm_vcpu_timer.h
> > +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h
> > @@ -28,6 +28,11 @@ struct kvm_vcpu_timer {
> > u64 next_cycles;
> > /* Underlying hrtimer instance */
> > struct hrtimer hrt;
> > +
> > + /* Flag to check if sstc is enabled or not */
> > + bool sstc_enabled;
> > + /* A function pointer to switch between stimecmp or hrtimer at runtime */
> > + int (*timer_next_event)(struct kvm_vcpu *vcpu, u64 ncycles);
> > };
> >
> > int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles);
> > @@ -39,6 +44,7 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu);
> > int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu);
> > int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu);
> > void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu);
> > +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu);
> > int kvm_riscv_guest_timer_init(struct kvm *kvm);
> > -
> > +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu);
> > #endif
> > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> > index 92bd469e2ba6..d2f02ba1947a 100644
> > --- a/arch/riscv/include/uapi/asm/kvm.h
> > +++ b/arch/riscv/include/uapi/asm/kvm.h
> > @@ -96,6 +96,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> > KVM_RISCV_ISA_EXT_H,
> > KVM_RISCV_ISA_EXT_I,
> > KVM_RISCV_ISA_EXT_M,
> > + KVM_RISCV_ISA_EXT_SSTC,
> > KVM_RISCV_ISA_EXT_MAX,
> > };
> >
> > diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
> > index 2e5ca43c8c49..83c4db7fc35f 100644
> > --- a/arch/riscv/kvm/main.c
> > +++ b/arch/riscv/kvm/main.c
> > @@ -32,7 +32,7 @@ int kvm_arch_hardware_setup(void *opaque)
> >
> > int kvm_arch_hardware_enable(void)
> > {
> > - unsigned long hideleg, hedeleg;
> > + unsigned long hideleg, hedeleg, henvcfg;
> >
> > hedeleg = 0;
> > hedeleg |= (1UL << EXC_INST_MISALIGNED);
> > @@ -51,6 +51,16 @@ int kvm_arch_hardware_enable(void)
> >
> > csr_write(CSR_HCOUNTEREN, -1UL);
> >
> > + if (riscv_isa_extension_available(NULL, SSTC)) {
> > +#ifdef CONFIG_64BIT
> > + henvcfg = csr_read(CSR_HENVCFG);
> > + csr_write(CSR_HENVCFG, henvcfg | 1UL<<HENVCFG_STCE);
> > +#else
> > + henvcfg = csr_read(CSR_HENVCFGH);
> > + csr_write(CSR_HENVCFGH, henvcfg | 1UL<<HENVCFGH_STCE);
> > +#endif
> > + }
> > +
> > csr_write(CSR_HVIP, 0);
> >
> > return 0;
> > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> > index 93492eb292fd..da1559725b03 100644
> > --- a/arch/riscv/kvm/vcpu.c
> > +++ b/arch/riscv/kvm/vcpu.c
> > @@ -143,7 +143,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
> >
> > int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
> > {
> > - return kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER);
> > + return kvm_riscv_vcpu_timer_pending(vcpu);
> > }
> >
> > void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
> > @@ -374,6 +374,7 @@ static unsigned long kvm_isa_ext_arr[] = {
> > RISCV_ISA_EXT_h,
> > RISCV_ISA_EXT_i,
> > RISCV_ISA_EXT_m,
> > + RISCV_ISA_EXT_SSTC,
> > };
> >
> > static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
> > @@ -754,6 +755,8 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
> > vcpu->arch.isa);
> > kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);
> >
> > + kvm_riscv_vcpu_timer_save(vcpu);
> > +
> > csr->vsstatus = csr_read(CSR_VSSTATUS);
> > csr->vsie = csr_read(CSR_VSIE);
> > csr->vstvec = csr_read(CSR_VSTVEC);
> > diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c
> > index 5c4c37ff2d48..d226a931de92 100644
> > --- a/arch/riscv/kvm/vcpu_timer.c
> > +++ b/arch/riscv/kvm/vcpu_timer.c
> > @@ -69,7 +69,18 @@ static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t)
> > return 0;
> > }
> >
> > -int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
> > +static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles)
> > +{
> > +#if __riscv_xlen == 32
> > + csr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF);
> > + csr_write(CSR_VSTIMECMPH, ncycles >> 32);
> > +#else
> > + csr_write(CSR_VSTIMECMP, ncycles);
> > +#endif
> > + return 0;
> > +}
> > +
> > +static int kvm_riscv_vcpu_update_hrtimer(struct kvm_vcpu *vcpu, u64 ncycles)
> > {
> > struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> > struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> > @@ -88,6 +99,68 @@ int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
> > return 0;
> > }
> >
> > +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
> > +{
> > + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> > +
> > + return t->timer_next_event(vcpu, ncycles);
> > +}
> > +
> > +static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer *h)
> > +{
> > + u64 delta_ns;
> > + struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt);
> > + struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer);
> > + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> > +
> > + if (kvm_riscv_current_cycles(gt) < t->next_cycles) {
> > + delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t);
> > + hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns));
> > + return HRTIMER_RESTART;
> > + }
> > +
> > + t->next_set = false;
> > + kvm_vcpu_kick(vcpu);
> > +
> > + return HRTIMER_NORESTART;
> > +}
> > +
> > +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu)
> > +{
> > + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> > + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> > + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp;
> > +
> > + if (!kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t) ||
> > + kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER))
> > + return true;
> > + else
> > + return false;
> > +}
> > +
> > +static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu)
> > +{
> > + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> > + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> > + u64 delta_ns;
> > + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp;
> > +
> > + if (!t->init_done)
> > + return;
> > +
> > + delta_ns = kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t);
> > + if (delta_ns) {
> > + t->next_cycles = vstimecmp_val;
> > + hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL);
> > + t->next_set = true;
> > + }
> > +}
> > +
> > +static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu)
> > +{
> > + kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
> > +}
> > +
> > int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu,
> > const struct kvm_one_reg *reg)
> > {
> > @@ -180,10 +253,20 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu)
> > return -EINVAL;
> >
> > hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
> > - t->hrt.function = kvm_riscv_vcpu_hrtimer_expired;
> > t->init_done = true;
> > t->next_set = false;
> >
> > + /* Enable sstc for every vcpu if available in hardware */
> > + if (riscv_isa_extension_available(NULL, SSTC)) {
> > + t->sstc_enabled = true;
> > + t->hrt.function = kvm_riscv_vcpu_vstimer_expired;
> > + t->timer_next_event = kvm_riscv_vcpu_update_vstimecmp;
> > + } else {
> > + t->sstc_enabled = false;
> > + t->hrt.function = kvm_riscv_vcpu_hrtimer_expired;
> > + t->timer_next_event = kvm_riscv_vcpu_update_hrtimer;
> > + }
> > +
> > return 0;
> > }
> >
> > @@ -202,7 +285,7 @@ int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu)
> > return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
> > }
> >
> > -void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
> > +static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu)
> > {
> > struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> >
> > @@ -214,6 +297,55 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
> > #endif
> > }
> >
> > +void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
> > +{
> > + struct kvm_vcpu_csr *csr;
> > + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> > +
> > + kvm_riscv_vcpu_update_timedelta(vcpu);
> > +
> > + if (!t->sstc_enabled)
> > + return;
> > +
> > + csr = &vcpu->arch.guest_csr;
> > +#ifdef CONFIG_64BIT
> > + csr_write(CSR_VSTIMECMP, csr->vstimecmp);
> > +#else
> > + csr_write(CSR_VSTIMECMP, (u32)csr->vstimecmp);
> > + csr_write(CSR_VSTIMECMPH, (u32)(csr->vstimecmp >> 32));
> > +#endif
> > +
> > + /* timer should be enabled for the remaining operations */
> > + if (unlikely(!t->init_done))
> > + return;
> > +
> > + kvm_riscv_vcpu_timer_unblocking(vcpu);
> > +}
> > +
> > +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu)
> > +{
> > + struct kvm_vcpu_csr *csr;
> > + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> > +
> > + if (!t->sstc_enabled)
> > + return;
> > +
> > + csr = &vcpu->arch.guest_csr;
> > + t = &vcpu->arch.timer;
> > +#ifdef CONFIG_64BIT
> > + csr->vstimecmp = csr_read(CSR_VSTIMECMP);
> > +#else
> > + csr->vstimecmp = csr_read(CSR_VSTIMECMP);
> > + csr->vstimecmp |= (u64)csr_read(CSR_VSTIMECMPH) << 32;
> > +#endif
> > + /* timer should be enabled for the remaining operations */
> > + if (unlikely(!t->init_done))
> > + return;
> > +
> > + if (kvm_vcpu_is_blocking(vcpu))
> > + kvm_riscv_vcpu_timer_blocking(vcpu);
> > +}
> > +
> > int kvm_riscv_guest_timer_init(struct kvm *kvm)
> > {
> > struct kvm_guest_timer *gt = &kvm->arch.timer;
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
--
Regards,
Atish
On Wed, Apr 27, 2022 at 12:23 AM Atish Patra <[email protected]> wrote:
>
> RISC-V ISA has sstc extension which allows updating the next clock event
> via a CSR (stimecmp) instead of an SBI call. This should happen dynamically
> if sstc extension is available. Otherwise, it will fallback to SBI call
> to maintain backward compatibility.
>
> Signed-off-by: Atish Patra <[email protected]>
> ---
> drivers/clocksource/timer-riscv.c | 21 ++++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 1767f8bf2013..d9398ae84a20 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -23,11 +23,24 @@
Add "#define pr_fmt(fmt)" here since you are using pr_info(...)
> #include <asm/sbi.h>
> #include <asm/timex.h>
>
> +static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
> +
> static int riscv_clock_next_event(unsigned long delta,
> struct clock_event_device *ce)
> {
> + uint64_t next_tval = get_cycles64() + delta;
Use "u64" here to be consistent with other parts of the kernel.
> +
> csr_set(CSR_IE, IE_TIE);
> - sbi_set_timer(get_cycles64() + delta);
> + if (static_branch_likely(&riscv_sstc_available)) {
> +#if __riscv_xlen == 32
Use CONFIG_32BIT here.
> + csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
> + csr_write(CSR_STIMECMPH, next_tval >> 32);
> +#else
> + csr_write(CSR_STIMECMP, next_tval);
> +#endif
> + } else
> + sbi_set_timer(next_tval);
> +
> return 0;
> }
>
> @@ -165,6 +178,12 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> if (error)
> pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
> error);
> +
> + if (riscv_isa_extension_available(NULL, SSTC)) {
> + pr_info("Timer interrupt in S-mode is available via sstc extension\n");
> + static_branch_enable(&riscv_sstc_available);
> + }
> +
> return error;
> }
>
> --
> 2.25.1
>
Regards,
Anup
On Wed, Apr 27, 2022 at 12:23 AM Atish Patra <[email protected]> wrote:
>
> This patch just introduces the required CSR fields related to the
> SSTC extension.
>
> Signed-off-by: Atish Patra <[email protected]>
Looks good to me.
Reviewed-by: Anup Patel <[email protected]>
Regards,
Anup
> ---
> arch/riscv/include/asm/csr.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index e935f27b10fd..10f4e1c36908 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -227,6 +227,9 @@
> #define CSR_SIP 0x144
> #define CSR_SATP 0x180
>
> +#define CSR_STIMECMP 0x14D
> +#define CSR_STIMECMPH 0x15D
> +
> #define CSR_VSSTATUS 0x200
> #define CSR_VSIE 0x204
> #define CSR_VSTVEC 0x205
> @@ -236,6 +239,8 @@
> #define CSR_VSTVAL 0x243
> #define CSR_VSIP 0x244
> #define CSR_VSATP 0x280
> +#define CSR_VSTIMECMP 0x24D
> +#define CSR_VSTIMECMPH 0x25D
>
> #define CSR_HSTATUS 0x600
> #define CSR_HEDELEG 0x602
> @@ -251,6 +256,8 @@
> #define CSR_HTINST 0x64a
> #define CSR_HGATP 0x680
> #define CSR_HGEIP 0xe12
> +#define CSR_HENVCFG 0x60A
> +#define CSR_HENVCFGH 0x61A
>
> #define CSR_MSTATUS 0x300
> #define CSR_MISA 0x301
> @@ -312,6 +319,10 @@
> #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
> #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
>
> +/* ENVCFG related bits */
> +#define HENVCFG_STCE 63
> +#define HENVCFGH_STCE 31
> +
> #ifndef __ASSEMBLY__
>
> #define csr_swap(csr, val) \
> --
> 2.25.1
>
On Wed, Apr 27, 2022 at 12:23 AM Atish Patra <[email protected]> wrote:
>
> The ISA extension framework now allows parsing any multi-letter
> ISA extension.
>
> Enable that for sstc extension.
>
> Signed-off-by: Atish Patra <[email protected]>
Looks good to me.
Reviewed-by: Anup Patel <[email protected]>
Regards,
Anup
> ---
> arch/riscv/include/asm/hwcap.h | 1 +
> arch/riscv/kernel/cpu.c | 1 +
> arch/riscv/kernel/cpufeature.c | 1 +
> 3 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 0734e42f74f2..25915eb60d61 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -52,6 +52,7 @@ extern unsigned long elf_hwcap;
> */
> enum riscv_isa_ext_id {
> RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
> + RISCV_ISA_EXT_SSTC,
> RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index ccb617791e56..ca0e4c0db17e 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node)
> */
> static struct riscv_isa_ext_data isa_ext_arr[] = {
> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> + __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
> __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
> };
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 1b2d42d7f589..a214537c22f1 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -192,6 +192,7 @@ void __init riscv_fill_hwcap(void)
> set_bit(*ext - 'a', this_isa);
> } else {
> SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
> + SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
> }
> #undef SET_ISA_EXT_MAP
> }
> --
> 2.25.1
>
On Wed, Apr 27, 2022 at 12:23 AM Atish Patra <[email protected]> wrote:
>
> Sstc extension allows the guest to program the vstimecmp CSR directly
> instead of making an SBI call to the hypervisor to program the next
> event. The timer interrupt is also directly injected to the guest by
> the hardware in this case. To maintain backward compatibility, the
> hypervisors also update the vstimecmp in an SBI set_time call if
> the hardware supports it. Thus, the older kernels in guest also
> take advantage of the sstc extension.
>
> Signed-off-by: Atish Patra <[email protected]>
> ---
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/include/asm/kvm_vcpu_timer.h | 8 +-
> arch/riscv/include/uapi/asm/kvm.h | 1 +
> arch/riscv/kvm/main.c | 12 ++-
> arch/riscv/kvm/vcpu.c | 5 +-
> arch/riscv/kvm/vcpu_timer.c | 138 +++++++++++++++++++++++-
> 6 files changed, 159 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h
> index 78da839657e5..50a97c821f83 100644
> --- a/arch/riscv/include/asm/kvm_host.h
> +++ b/arch/riscv/include/asm/kvm_host.h
> @@ -135,6 +135,7 @@ struct kvm_vcpu_csr {
> unsigned long hvip;
> unsigned long vsatp;
> unsigned long scounteren;
> + u64 vstimecmp;
No need for separate "vstimecmp" here instead you can re-use
"next_cycles" of "struct kvm_vcpu_timer".
> };
>
> struct kvm_vcpu_arch {
> diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h
> index 375281eb49e0..a24a265f3ccb 100644
> --- a/arch/riscv/include/asm/kvm_vcpu_timer.h
> +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h
> @@ -28,6 +28,11 @@ struct kvm_vcpu_timer {
> u64 next_cycles;
> /* Underlying hrtimer instance */
> struct hrtimer hrt;
> +
> + /* Flag to check if sstc is enabled or not */
> + bool sstc_enabled;
> + /* A function pointer to switch between stimecmp or hrtimer at runtime */
> + int (*timer_next_event)(struct kvm_vcpu *vcpu, u64 ncycles);
> };
>
> int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles);
> @@ -39,6 +44,7 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu);
> int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu);
> int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu);
> void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu);
> +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu);
> int kvm_riscv_guest_timer_init(struct kvm *kvm);
> -
> +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu);
> #endif
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 92bd469e2ba6..d2f02ba1947a 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -96,6 +96,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> KVM_RISCV_ISA_EXT_H,
> KVM_RISCV_ISA_EXT_I,
> KVM_RISCV_ISA_EXT_M,
> + KVM_RISCV_ISA_EXT_SSTC,
> KVM_RISCV_ISA_EXT_MAX,
> };
>
> diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
> index 2e5ca43c8c49..83c4db7fc35f 100644
> --- a/arch/riscv/kvm/main.c
> +++ b/arch/riscv/kvm/main.c
> @@ -32,7 +32,7 @@ int kvm_arch_hardware_setup(void *opaque)
>
> int kvm_arch_hardware_enable(void)
> {
> - unsigned long hideleg, hedeleg;
> + unsigned long hideleg, hedeleg, henvcfg;
>
> hedeleg = 0;
> hedeleg |= (1UL << EXC_INST_MISALIGNED);
> @@ -51,6 +51,16 @@ int kvm_arch_hardware_enable(void)
>
> csr_write(CSR_HCOUNTEREN, -1UL);
>
> + if (riscv_isa_extension_available(NULL, SSTC)) {
> +#ifdef CONFIG_64BIT
> + henvcfg = csr_read(CSR_HENVCFG);
> + csr_write(CSR_HENVCFG, henvcfg | 1UL<<HENVCFG_STCE);
> +#else
> + henvcfg = csr_read(CSR_HENVCFGH);
> + csr_write(CSR_HENVCFGH, henvcfg | 1UL<<HENVCFGH_STCE);
> +#endif
> + }
> +
> csr_write(CSR_HVIP, 0);
>
> return 0;
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 93492eb292fd..da1559725b03 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -143,7 +143,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
>
> int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
> {
> - return kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER);
> + return kvm_riscv_vcpu_timer_pending(vcpu);
> }
>
> void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
> @@ -374,6 +374,7 @@ static unsigned long kvm_isa_ext_arr[] = {
> RISCV_ISA_EXT_h,
> RISCV_ISA_EXT_i,
> RISCV_ISA_EXT_m,
> + RISCV_ISA_EXT_SSTC,
> };
>
> static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
> @@ -754,6 +755,8 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
> vcpu->arch.isa);
> kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);
>
> + kvm_riscv_vcpu_timer_save(vcpu);
> +
> csr->vsstatus = csr_read(CSR_VSSTATUS);
> csr->vsie = csr_read(CSR_VSIE);
> csr->vstvec = csr_read(CSR_VSTVEC);
> diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c
> index 5c4c37ff2d48..d226a931de92 100644
> --- a/arch/riscv/kvm/vcpu_timer.c
> +++ b/arch/riscv/kvm/vcpu_timer.c
> @@ -69,7 +69,18 @@ static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t)
> return 0;
> }
>
> -int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
> +static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles)
> +{
> +#if __riscv_xlen == 32
> + csr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF);
> + csr_write(CSR_VSTIMECMPH, ncycles >> 32);
> +#else
> + csr_write(CSR_VSTIMECMP, ncycles);
> +#endif
> + return 0;
> +}
> +
> +static int kvm_riscv_vcpu_update_hrtimer(struct kvm_vcpu *vcpu, u64 ncycles)
> {
> struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> @@ -88,6 +99,68 @@ int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
> return 0;
> }
>
> +int kvm_riscv_vcpu_timer_next_event(struct kvm_vcpu *vcpu, u64 ncycles)
> +{
> + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> +
> + return t->timer_next_event(vcpu, ncycles);
> +}
> +
> +static enum hrtimer_restart kvm_riscv_vcpu_vstimer_expired(struct hrtimer *h)
> +{
> + u64 delta_ns;
> + struct kvm_vcpu_timer *t = container_of(h, struct kvm_vcpu_timer, hrt);
> + struct kvm_vcpu *vcpu = container_of(t, struct kvm_vcpu, arch.timer);
> + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> +
> + if (kvm_riscv_current_cycles(gt) < t->next_cycles) {
> + delta_ns = kvm_riscv_delta_cycles2ns(t->next_cycles, gt, t);
> + hrtimer_forward_now(&t->hrt, ktime_set(0, delta_ns));
> + return HRTIMER_RESTART;
> + }
> +
> + t->next_set = false;
> + kvm_vcpu_kick(vcpu);
> +
> + return HRTIMER_NORESTART;
> +}
> +
> +bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp;
> +
> + if (!kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t) ||
> + kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER))
> + return true;
> + else
> + return false;
> +}
> +
> +static void kvm_riscv_vcpu_timer_blocking(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> + struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
> + u64 delta_ns;
> + u64 vstimecmp_val = vcpu->arch.guest_csr.vstimecmp;
Define delta_ns is same line as vstimecmp_val
> +
> + if (!t->init_done)
> + return;
> +
> + delta_ns = kvm_riscv_delta_cycles2ns(vstimecmp_val, gt, t);
> + if (delta_ns) {
> + t->next_cycles = vstimecmp_val;
> + hrtimer_start(&t->hrt, ktime_set(0, delta_ns), HRTIMER_MODE_REL);
> + t->next_set = true;
> + }
> +}
> +
> +static void kvm_riscv_vcpu_timer_unblocking(struct kvm_vcpu *vcpu)
> +{
> + kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
> +}
> +
> int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> @@ -180,10 +253,20 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu)
> return -EINVAL;
>
> hrtimer_init(&t->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
> - t->hrt.function = kvm_riscv_vcpu_hrtimer_expired;
> t->init_done = true;
> t->next_set = false;
>
> + /* Enable sstc for every vcpu if available in hardware */
> + if (riscv_isa_extension_available(NULL, SSTC)) {
> + t->sstc_enabled = true;
> + t->hrt.function = kvm_riscv_vcpu_vstimer_expired;
> + t->timer_next_event = kvm_riscv_vcpu_update_vstimecmp;
> + } else {
> + t->sstc_enabled = false;
> + t->hrt.function = kvm_riscv_vcpu_hrtimer_expired;
> + t->timer_next_event = kvm_riscv_vcpu_update_hrtimer;
> + }
> +
> return 0;
> }
>
> @@ -202,7 +285,7 @@ int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu)
Set "next_cycles" to -1ULL in kvm_riscv_vcpu_timer_reset() because if we have
older kernel (which does not use Sstc) as Guest then it will get timer interrupt
immediately after enabling sie.STIE.
> return kvm_riscv_vcpu_timer_cancel(&vcpu->arch.timer);
> }
>
> -void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
> +static void kvm_riscv_vcpu_update_timedelta(struct kvm_vcpu *vcpu)
> {
> struct kvm_guest_timer *gt = &vcpu->kvm->arch.timer;
>
> @@ -214,6 +297,55 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
> #endif
> }
>
> +void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_vcpu_csr *csr;
> + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> +
> + kvm_riscv_vcpu_update_timedelta(vcpu);
> +
> + if (!t->sstc_enabled)
> + return;
> +
> + csr = &vcpu->arch.guest_csr;
> +#ifdef CONFIG_64BIT
> + csr_write(CSR_VSTIMECMP, csr->vstimecmp);
> +#else
> + csr_write(CSR_VSTIMECMP, (u32)csr->vstimecmp);
> + csr_write(CSR_VSTIMECMPH, (u32)(csr->vstimecmp >> 32));
> +#endif
> +
> + /* timer should be enabled for the remaining operations */
> + if (unlikely(!t->init_done))
> + return;
> +
> + kvm_riscv_vcpu_timer_unblocking(vcpu);
> +}
> +
> +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_vcpu_csr *csr;
> + struct kvm_vcpu_timer *t = &vcpu->arch.timer;
> +
> + if (!t->sstc_enabled)
> + return;
> +
> + csr = &vcpu->arch.guest_csr;
> + t = &vcpu->arch.timer;
> +#ifdef CONFIG_64BIT
> + csr->vstimecmp = csr_read(CSR_VSTIMECMP);
> +#else
> + csr->vstimecmp = csr_read(CSR_VSTIMECMP);
> + csr->vstimecmp |= (u64)csr_read(CSR_VSTIMECMPH) << 32;
> +#endif
> + /* timer should be enabled for the remaining operations */
> + if (unlikely(!t->init_done))
> + return;
> +
> + if (kvm_vcpu_is_blocking(vcpu))
> + kvm_riscv_vcpu_timer_blocking(vcpu);
> +}
> +
> int kvm_riscv_guest_timer_init(struct kvm *kvm)
> {
> struct kvm_guest_timer *gt = &kvm->arch.timer;
> --
> 2.25.1
>
Regards,
Anup