The goal of this series is to switch the meson sub-drivers to use
clk_ops.determine_rate instead of clk_ops.round_rate. The former has
lower precision (2^31 instead of 2^32 on 32-bit systems). Also the idea
of the .determine_rate callback is that is replaces .round_rate so the
latter can be removed at some point.
No functional changes (apart from the 2^31 to 2^32 difference mentioned
bove) intended.
Martin Blumenstingl (4):
clk: meson: mpll: Switch from .round_rate to .determine_rate
clk: meson: dualdiv: switch from .round_rate to .determine_rate
clk: meson: sclk-div: switch from .round_rate to .determine_rate
clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate
drivers/clk/meson/clk-cpu-dyndiv.c | 9 ++++-----
drivers/clk/meson/clk-dualdiv.c | 21 +++++++++++++--------
drivers/clk/meson/clk-mpll.c | 20 +++++++++++++-------
drivers/clk/meson/sclk-div.c | 11 ++++++-----
4 files changed, 36 insertions(+), 25 deletions(-)
--
2.39.0
clk_ops.round_rate will be removed at some point. It's replacement is
.determine_rate. Switch clk-cpu-dyndiv over to use .determine_rate.
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/clk/meson/clk-cpu-dyndiv.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu-dyndiv.c
index 36976927fe82..8778c149d26a 100644
--- a/drivers/clk/meson/clk-cpu-dyndiv.c
+++ b/drivers/clk/meson/clk-cpu-dyndiv.c
@@ -27,14 +27,13 @@ static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw,
NULL, 0, data->div.width);
}
-static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *prate)
+static int meson_clk_cpu_dyndiv_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
- return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);
+ return divider_determine_rate(hw, req, NULL, data->div.width, 0);
}
static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -63,7 +62,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
const struct clk_ops meson_clk_cpu_dyndiv_ops = {
.recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,
- .round_rate = meson_clk_cpu_dyndiv_round_rate,
+ .determine_rate = meson_clk_cpu_dyndiv_determine_rate,
.set_rate = meson_clk_cpu_dyndiv_set_rate,
};
EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);
--
2.39.0
Quoting Martin Blumenstingl (2022-12-25 13:26:28)
> The goal of this series is to switch the meson sub-drivers to use
> clk_ops.determine_rate instead of clk_ops.round_rate. The former has
> lower precision (2^31 instead of 2^32 on 32-bit systems). Also the idea
> of the .determine_rate callback is that is replaces .round_rate so the
> latter can be removed at some point.
>
> No functional changes (apart from the 2^31 to 2^32 difference mentioned
> bove) intended.
>
>
> Martin Blumenstingl (4):
> clk: meson: mpll: Switch from .round_rate to .determine_rate
> clk: meson: dualdiv: switch from .round_rate to .determine_rate
> clk: meson: sclk-div: switch from .round_rate to .determine_rate
> clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate
>
Acked-by: Stephen Boyd <[email protected]>
On Sun 25 Dec 2022 at 22:26, Martin Blumenstingl <[email protected]> wrote:
> The goal of this series is to switch the meson sub-drivers to use
> clk_ops.determine_rate instead of clk_ops.round_rate. The former has
> lower precision (2^31 instead of 2^32 on 32-bit systems). Also the idea
> of the .determine_rate callback is that is replaces .round_rate so the
> latter can be removed at some point.
>
> No functional changes (apart from the 2^31 to 2^32 difference mentioned
> bove) intended.
Applied. Thx Martin.
>
>
> Martin Blumenstingl (4):
> clk: meson: mpll: Switch from .round_rate to .determine_rate
> clk: meson: dualdiv: switch from .round_rate to .determine_rate
> clk: meson: sclk-div: switch from .round_rate to .determine_rate
> clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate
>
> drivers/clk/meson/clk-cpu-dyndiv.c | 9 ++++-----
> drivers/clk/meson/clk-dualdiv.c | 21 +++++++++++++--------
> drivers/clk/meson/clk-mpll.c | 20 +++++++++++++-------
> drivers/clk/meson/sclk-div.c | 11 ++++++-----
> 4 files changed, 36 insertions(+), 25 deletions(-)