The ServerWorks peer bus problem is still present on the 2.4.1 kernel. The
problem stems from the fact that there can be more than one secondary bus
for a given north bridge. For example, the Compaq Proliant DL580 has two
"root busses" coming off of a single north bridge. I'm including below an
email from Adam Lackorzynski. In his email, he includes a patch that fixes
the problem. I think Martin objected because he thought the patch got the
meaning of the two config registers wrong, but it is, in fact, correct.
Please accept this patch so that the 2.4 kernel can see all PCI devices on
systems with the ServerWorks chipset.
Thanks,
Dan Zink
____________________________
[email protected]
------------------------------------------
The patch below (against vanilla 2.4.0) makes Linux recognize
PCI-Devices sitting in another PCI bus than 0 (or 1).
This was tested on a Netfinity 7100-8666 using a ServerWorks chipset.
00:00.0 Host bridge: ServerWorks CNB20HE (rev 21)
00:00.1 Host bridge: ServerWorks CNB20HE (rev 01)
00:00.2 Host bridge: ServerWorks: Unknown device 0006
00:00.3 Host bridge: ServerWorks: Unknown device 0006
00:01.0 SCSI storage controller: Adaptec 7896
00:01.1 SCSI storage controller: Adaptec 7896
00:05.0 Ethernet controller: Advanced Micro Devices [AMD] 79c970 [PCnet
LANCE] (rev 44)
00:06.0 VGA compatible controller: S3 Inc. Trio 64 3D (rev 01)
00:0f.0 ISA bridge: ServerWorks OSB4 (rev 4f)
00:0f.1 IDE interface: ServerWorks: Unknown device 0211
00:0f.2 USB Controller: ServerWorks: Unknown device 0220 (rev 04)
02:04.0 Ethernet controller: Digital Equipment Corporation DECchip 21142/43
(rev 41)
02:06.0 RAID bus controller: IBM: Unknown device 01bd
The last two lines do not occur without the patch.
diff -ur linux-2.4.0/linux/arch/i386/kernel/pci-pc.c
linux/arch/i386/kernel/pci-pc.c
--- linux-2.4.0/linux/arch/i386/kernel/pci-pc.c Thu Jun 22 16:17:16 2000
+++ linux/arch/i386/kernel/pci-pc.c Tue Jan 16 18:10:30 2001
@@ -849,10 +849,13 @@
* ServerWorks host bridges -- Find and scan all secondary buses.
* Register 0x44 contains first, 0x45 last bus number routed there.
*/
- u8 busno;
- pci_read_config_byte(d, 0x44, &busno);
- printk("PCI: ServerWorks host bridge: secondary bus %02x\n", busno);
- pci_scan_bus(busno, pci_root_ops, NULL);
+ u8 busno_first, busno_last, i;
+ pci_read_config_byte(d, 0x44, &busno_first);
+ pci_read_config_byte(d, 0x45, &busno_last);
+ for (i = busno_first; i <= busno_last; i++) {
+ printk("PCI: ServerWorks host bridge: secondary bus %02x\n",
i);
+ pci_scan_bus(i, pci_root_ops, NULL);
+ }
pcibios_last_bus = -1;
}
Adam
--
Adam [email protected]
Lackorzynski http://a.home.dhs.org
Hello!
> The ServerWorks peer bus problem is still present on the 2.4.1 kernel. The
> problem stems from the fact that there can be more than one secondary bus
> for a given north bridge. For example, the Compaq Proliant DL580 has two
> "root busses" coming off of a single north bridge. I'm including below an
> email from Adam Lackorzynski. In his email, he includes a patch that fixes
> the problem. I think Martin objected because he thought the patch got the
> meaning of the two config registers wrong, but it is, in fact, correct.
What leads you to your belief it's correct? The lspci dump Adam has sent
to the list shows that there's something utterly wrong with our understanding
of the ServerWorks config registers -- they seem to say that the primary
bus numbers are 00 and 01, but in reality they are 00 and 02.
For now, it will be better to comment out the whole ServerWorks fixup thing
and let the generic peer bus code do its magic work -- it's far better to rely
on BIOS and chipset to behave sanely (i.e., BIOS reporting last_bus not lower
than the real one and chipset not decoding out-of-range bus numbers) than on
guesses of register values which are probably wrong, at least until we have
some more examples for comparison.
Dan, can you send me outputs of 'lspci -MH1 -vvx' and 'lspci -vvxxx -s0:0'
and also try commenting out the lines
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HE, pci_fixup_serverworks },
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE, pci_fixup_serverworks },
{ PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CMIC_HE, pci_fixup_serverworks },
in arch/i386/kernel/pci-pc.c, please?
Have a nice fortnight
--
Martin `MJ' Mares <[email protected]> <[email protected]> http://atrey.karlin.mff.cuni.cz/~mj/
This message transmited on 100% recycled electrons.
Dan,
Have you got a hack for 2.2.18/19x ??
Andre Hedrick
Linux ATA Development
ASL Kernel Development
-----------------------------------------------------------------------------
ASL, Inc. Toll free: 1-877-ASL-3535
1757 Houret Court Fax: 1-408-941-2071
Milpitas, CA 95035 Web: http://www.aslab.com
On Thu Feb 08, 2001 at 03:06:27 -0800, Andre Hedrick wrote:
> Have you got a hack for 2.2.18/19x ??
I do not have problems with 2.2.x Kernels here. They see all the PCI
devices just fine.
Adam
--
Adam [email protected]
Lackorzynski http://a.home.dhs.org
>
> What leads you to your belief it's correct? The lspci dump Adam has sent
> to the list shows that there's something utterly wrong with our
understanding
> of the ServerWorks config registers -- they seem to say that the primary
> bus numbers are 00 and 01, but in reality they are 00 and 02.
If you look at the lspci output below, you will find that this server has
root
busses 0, 2, and 7. Also, the BIOS reports the last bus to be 10.
Accordingly,
offset 44 and 45 of function 0 are 2 and 10. For function 1 they are 0 and
1.
That matches the comment in the kernel about them being the first and last
bus.
> For now, it will be better to comment out the whole ServerWorks fixup
thing
> and let the generic peer bus code do its magic work -- it's far better to
rely
> on BIOS and chipset to behave sanely (i.e., BIOS reporting last_bus not
lower
> than the real one and chipset not decoding out-of-range bus numbers) than
on
> guesses of register values which are probably wrong, at least until we
have
> some more examples for comparison.
I agree with this. Especially given the fact that it will require less
maintenance
down the road. It would be hard to keep up with the ever-changing chipset
world.
> and also try commenting out the lines
>
> { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS,
> PCI_DEVICE_ID_SERVERWORKS_HE, pci_fixup_serverworks },
> { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS,
> PCI_DEVICE_ID_SERVERWORKS_LE, pci_fixup_serverworks },
> { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS,
> PCI_DEVICE_ID_SERVERWORKS_CMIC_HE, pci_fixup_serverworks },
>
> in arch/i386/kernel/pci-pc.c, please?
I had already tried that with good results. Everything works fine if we
don't use
the pci_fixup_serverworks function.
Thanks,
Dan
Here is the output of 'lspci -MH1 -vvx' slightly edited to reduce the
length...
00:00.0 Host bridge: ServerWorks CNB20HE (rev 21)
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
00: 66 11 08 00 00 00 00 00 21 00 00 06 08 40 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:00.1 Host bridge: ServerWorks CNB20HE (rev 01)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
Latency: 64, cache line size 08
00: 66 11 08 00 47 01 00 22 01 00 00 06 08 40 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:00.2 Host bridge: ServerWorks: Unknown device 0006
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
00: 66 11 06 00 42 01 00 22 00 00 00 06 08 40 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:00.3 Host bridge: ServerWorks: Unknown device 0006
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
00: 66 11 06 00 42 01 00 22 00 00 00 06 08 40 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:03.0 System peripheral: Compaq Computer Corporation Advanced System
Management Controller
Subsystem: Compaq Computer Corporation: Unknown device b0f3
Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin A routed to IRQ 255
Region 0: I/O ports at 1800
Region 1: Memory at cabf0000 (32-bit, non-prefetchable)
00: 11 0e f0 a0 43 01 00 02 00 00 80 08 00 00 00 00
10: 01 18 00 00 00 00 bf ca 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 11 0e f3 b0
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 01 00 00
00:0f.0 ISA bridge: ServerWorks OSB4 (rev 4f)
Subsystem: ServerWorks OSB4
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 0
00: 66 11 00 02 07 00 00 02 4f 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 66 11 00 02
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:0f.1 IDE interface: ServerWorks: Unknown device 0211 (prog-if 8a [Master
SecP PriP])
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Latency: 64
Region 4: I/O ports at 2c00
00: 66 11 11 02 45 01 00 02 00 8a 01 01 00 40 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 2c 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
02:05.0 PCI Hot-plug controller: Compaq Computer Corporation PCI Hotplug
Controller (rev 12)
Subsystem: Compaq Computer Corporation: Unknown device a2f8
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin A routed to IRQ 10
Region 0: Memory at dcef0000 (32-bit, non-prefetchable)
Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/0
Enable-
Address: 0000000000000000 Data: 0000
00: 11 0e f7 a0 42 01 30 02 12 00 04 08 00 00 00 00
10: 00 00 ef dc 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 11 0e f8 a2
30: 00 00 00 00 58 00 00 00 00 00 00 00 0a 01 00 00
07:05.0 PCI Hot-plug controller: Compaq Computer Corporation PCI Hotplug
Controller (rev 12)
Subsystem: Compaq Computer Corporation: Unknown device a2f9
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin A routed to IRQ 10
Region 0: Memory at f7ff0000 (32-bit, non-prefetchable)
Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/0
Enable-
Address: 0000000000000000 Data: 0000
00: 11 0e f7 a0 42 01 30 02 12 00 04 08 00 00 00 00
10: 00 00 ff f7 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 11 0e f9 a2
30: 00 00 00 00 58 00 00 00 00 00 00 00 0a 01 00 00
Summary of buses:
00: Primary host bus
02: Secondary host bus (?)
07: Secondary host bus (?)
Here is the complete output of 'lspci -vvxxx -s0:0'...
00:00.0 Host bridge: ServerWorks CNB20HE (rev 21)
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR-
00: 66 11 08 00 00 00 00 00 21 00 00 06 08 40 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 02 0a 00 00 00 71 03 3b 00 00 00 00
50: 00 00 00 00 f3 0b 00 00 00 00 00 10 40 00 00 00
60: 00 00 c0 10 00 01 07 07 00 00 00 00 00 00 00 00
70: 04 2a 00 aa 90 0c ff 2f 09 18 80 00 00 60 00 00
80: 00 00 00 00 00 00 00 07 00 00 00 00 00 00 00 00
90: 08 fa 3e 5f 01 00 f0 00 05 00 f0 00 00 00 00 00
a0: 00 01 02 20 04 05 06 07 00 00 00 00 00 00 00 00
b0: ff 7e fc 7f cf 78 de df e7 d2 c0 ee f3 be 80 60
c0: ac 0c 7f 0f 00 00 00 00 00 00 00 00 01 07 c0 fe
d0: 00 30 fc 8f 00 00 00 00 00 00 00 00 01 00 00 00
e0: 04 00 00 00 aa 78 ff 7d ff ff 78 aa 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 c0 00 00 00
00:00.1 Host bridge: ServerWorks CNB20HE (rev 01)
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
Latency: 64, cache line size 08
00: 66 11 08 00 47 01 00 22 01 00 00 06 08 40 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 01 18 00 80 00 00 4b 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 02 00 20 00 01 02 00 10 41 3c 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 90 0c ab 0c 00 00 00 00 00 00 00 00 01 07 00 00
d0: 00 00 0c 2c 00 00 00 00 00 00 00 00 01 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: df fa f6 7b bf b3 f7 3f 00 00 00 00 c2 0d 00 00
00:00.2 Host bridge: ServerWorks: Unknown device 0006
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
00: 66 11 06 00 42 01 00 22 00 00 00 06 08 40 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 02 06 00 00 00 00 00 0e 00 00 00 20
50: 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 2a 00 aa 90 0c ff 0f 00 00 00 00 00 00 00 00
80: 10 00 00 00 91 00 ce 50 d5 04 00 10 00 00 00 00
90: 90 54 40 49 94 94 d0 56 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: ac 0c ce 0d 00 00 00 00 00 00 00 00 01 07 00 00
d0: 00 30 fc 5f 10 d1 40 06 30 01 50 1c 01 00 00 00
e0: 11 d0 45 d4 00 00 00 00 00 00 00 00 c4 00 00 00
f0: 40 e0 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:00.3 Host bridge: ServerWorks: Unknown device 0006
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+
Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort+ >SERR- <PERR-
00: 66 11 06 00 42 01 00 22 00 00 00 06 08 40 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 07 0a 00 00 00 00 00 0e 00 00 00 00
50: 11 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 2a 00 aa 90 0c ff 0f 00 00 00 00 00 00 00 00
80: 10 00 00 00 91 00 ce 50 d5 04 00 10 00 00 00 00
90: 30 dc 00 04 d0 54 90 10 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 c1 00 29 44 00 00 00 00 00 00 00 00
c0: cf 0d 7f 0f 00 00 00 00 00 00 00 00 01 07 00 00
d0: 00 60 fc 8f b0 55 00 31 10 9e 58 a1 01 00 00 00
e0: 50 9c 59 d5 00 00 00 00 00 00 00 00 c6 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
On Thu, 8 Feb 2001, Adam Lackorzynski wrote:
> On Thu Feb 08, 2001 at 03:06:27 -0800, Andre Hedrick wrote:
> > Have you got a hack for 2.2.18/19x ??
>
> I do not have problems with 2.2.x Kernels here. They see all the PCI
> devices just fine.
But it will not register the device
Bus 0, device 15, function 2:
USB Controller: Unknown vendor OSB4 USB (rev 4).
Medium devsel. Fast back-to-back capable. IRQ 10. Master Capable. Latency=32. Max Lat=80.
Non-prefetchable 32 bit memory at 0xfe9fc000 [0xfe9fc000].
Bus 1, device 2, function 0:
RAID storage controller: CMD 649 (rev 1).
Medium devsel. Fast back-to-back capable. IRQ 27. Master Capable. Latency=64. Min Gnt=2.Max Lat=4.
I/O at 0xefe0 [0xefe1].
I/O at 0xefac [0xefad].
I/O at 0xefa0 [0xefa1].
I/O at 0xefa8 [0xefa9].
I/O at 0xef90 [0xef91].
The interrupts are invalid.
It wants 10 and it is yeilding 27.
This is the first time it has ever done this with my code.
Andre Hedrick
Linux ATA Development
ASL Kernel Development
-----------------------------------------------------------------------------
ASL, Inc. Toll free: 1-877-ASL-3535
1757 Houret Court Fax: 1-408-941-2071
Milpitas, CA 95035 Web: http://www.aslab.com
In article <[email protected]>,
Martin Mares <[email protected]> wrote:
>
>What leads you to your belief it's correct? The lspci dump Adam has sent
>to the list shows that there's something utterly wrong with our understanding
>of the ServerWorks config registers -- they seem to say that the primary
>bus numbers are 00 and 01, but in reality they are 00 and 02.
Is there any reason to not just change the default pcibios_last_bus to
255, and just always default to scanning all PCI bus numbers?
Alternatively, how about just changing the fixups to be saner. Right now
they are obviously bogus, and don't even match with their comments.
Somehting like this..
Linus
----
--- old-linux/arch/i386/kernel/pci-pc.c Thu Jun 22 07:17:16 2000
+++ linux/arch/i386/kernel/pci-pc.c Thu Feb 8 11:36:58 2001
@@ -843,30 +843,40 @@
pcibios_last_bus = -1;
}
+/*
+ * ServerWorks host bridges -- Find and scan all secondary buses.
+ * Register 0x44 contains first, 0x45 last bus number routed there.
+ */
static void __init pci_fixup_serverworks(struct pci_dev *d)
{
- /*
- * ServerWorks host bridges -- Find and scan all secondary buses.
- * Register 0x44 contains first, 0x45 last bus number routed there.
- */
- u8 busno;
- pci_read_config_byte(d, 0x44, &busno);
- printk("PCI: ServerWorks host bridge: secondary bus %02x\n", busno);
- pci_scan_bus(busno, pci_root_ops, NULL);
- pcibios_last_bus = -1;
+ u8 busno1, busno2;
+
+ pci_read_config_byte(d, 0x44, &busno1);
+ pci_read_config_byte(d, 0x45, &busno2);
+ if (busno2 < busno1)
+ busno2 = busno1;
+ if (busno2 > pcibios_last_bus) {
+ pcibios_last_bus = busno2;
+ printk("PCI: ServerWorks host bridge: last bus %02x\n", pcibios_last_bus);
+ }
}
+/*
+ * Compaq host bridges -- Find and scan all secondary buses.
+ * This time registers 0xc8 and 0xc9.
+ */
static void __init pci_fixup_compaq(struct pci_dev *d)
{
- /*
- * Compaq host bridges -- Find and scan all secondary buses.
- * This time registers 0xc8 and 0xc9.
- */
- u8 busno;
- pci_read_config_byte(d, 0xc8, &busno);
- printk("PCI: Compaq host bridge: secondary bus %02x\n", busno);
- pci_scan_bus(busno, pci_root_ops, NULL);
- pcibios_last_bus = -1;
+ u8 busno1, busno2;
+
+ pci_read_config_byte(d, 0xc8, &busno1);
+ pci_read_config_byte(d, 0xc9, &busno2);
+ if (busno2 < busno1)
+ busno2 = busno1;
+ if (busno2 > pcibios_last_bus) {
+ pcibios_last_bus = busno2;
+ printk("PCI: Compaq host bridge: last bus %02x\n", busno2);
+ }
}
static void __init pci_fixup_umc_ide(struct pci_dev *d)