> > And that would now really work when CONFIG_X86_OOSTORE=1 is required
> > [after all, it is a write, so it'd need the equivalent of a wmb() or
> > xchg()].
>
> Is this a hint that your employer may have an x86 chip in the future
> with weak ordering? :)
Hmmm ... taking into account that there are some many thousands of
employees in my company and that I know less than one hundred ...
and that they are all software ... well, I don't think I am into
the rumour mill :]
Inaky Perez-Gonzalez -- Not speaking for Intel - opinions are my own [or my
fault]
On Thu, 2002-12-19 at 19:04, Perez-Gonzalez, Inaky wrote:
>
> > > And that would now really work when CONFIG_X86_OOSTORE=1 is required
> > > [after all, it is a write, so it'd need the equivalent of a wmb() or
> > > xchg()].
> >
> > Is this a hint that your employer may have an x86 chip in the future
> > with weak ordering? :)
>
> Hmmm ... taking into account that there are some many thousands of
> employees in my company and that I know less than one hundred ...
> and that they are all software ... well, I don't think I am into
> the rumour mill :]
Also OOSTORE is there because other vendors already make weak store
order capable x86 processors. One example of this is the Winchip - where
turning off strict store ordering is worth 30% performance.
In addition you have to treat store ordering/locking carefully due to
the pentium pro store fencing errata. (Thats why our < PII kernel
generates lock movb to unlock when in theory the lock isnt needed).
Alan
On Fri, Dec 20, 2002 at 03:08:28AM +0000, Alan Cox wrote:
> In addition you have to treat store ordering/locking carefully due to
> the pentium pro store fencing errata. (Thats why our < PII kernel
> generates lock movb to unlock when in theory the lock isnt needed).
Except the SMP causality test app I wrote got success reports from every
PPro stepping level.
--
"Love the dolphins," she advised him. "Write by W.A.S.T.E.."