All,
The following patch updates the PCI subsystem so that root PCI host
bridges appear as devices hanging off the system bus instead of root
level devices. To me, this makes more sense from a topology point of
view since most systems look as such:
cpu0 <-- sys_bus --> Memory Controller/PCI Bridge <-- sys_bus --> cpu1
|
|
|
<---------------------------- Root Level PCI Bus -------------------->
Even on system on a chip designs, the PCI bridge unit and the CPU core are
physically connected over the system bus. A PCI host bridge always connects
the system/cpu/local bus to the PCI bus, so I think the device tree should
represent this.
I'm not sure if this is the best solution as we could have embedded systems
where the root PCI bus is hanging off from something like a Rapid I/O bus or
other non-CPU bus, so maybe we should just kill pci_scan_bus() and force all
platforms to use pci_scan_bus_parented() so developers can best determine how
to map their system's topology to the device tree?
Thanks,
~Deepak
diff -Nru a/drivers/base/sys.c b/drivers/base/sys.c
--- a/drivers/base/sys.c Tue Mar 25 16:07:06 2003
+++ b/drivers/base/sys.c Tue Mar 25 16:07:06 2003
@@ -21,7 +21,7 @@
#include <linux/string.h>
/* The default system device parent. */
-static struct device system_bus = {
+struct device system_bus = {
.name = "System Bus",
.bus_id = "sys",
};
@@ -144,6 +144,7 @@
return device_register(&system_bus);
}
+EXPORT_SYMBOL(system_bus);
EXPORT_SYMBOL(system_bus_type);
EXPORT_SYMBOL(sys_device_register);
EXPORT_SYMBOL(sys_device_unregister);
diff -Nru a/include/linux/device.h b/include/linux/device.h
--- a/include/linux/device.h Tue Mar 25 16:07:06 2003
+++ b/include/linux/device.h Tue Mar 25 16:07:06 2003
@@ -353,6 +353,7 @@
extern void sys_device_unregister(struct sys_device *);
extern struct bus_type system_bus_type;
+extern struct device system_bus;
/* drivers/base/platform.c */
diff -Nru a/include/linux/pci.h b/include/linux/pci.h
--- a/include/linux/pci.h Tue Mar 25 16:07:06 2003
+++ b/include/linux/pci.h Tue Mar 25 16:07:06 2003
@@ -537,12 +537,12 @@
struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata);
static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
{
- return pci_scan_bus_parented(NULL, bus, ops, sysdata);
+ return pci_scan_bus_parented(&system_bus, bus, ops, sysdata);
}
struct pci_bus *pci_alloc_primary_bus_parented(struct device * parent, int bus);
static inline struct pci_bus *pci_alloc_primary_bus(int bus)
{
- return pci_alloc_primary_bus_parented(NULL, bus);
+ return pci_alloc_primary_bus_parented(&system_bus, bus);
}
int pci_scan_slot(struct pci_bus *bus, int devfn);
void pci_bus_add_devices(struct pci_bus *bus);
--
Deepak Saxena
MontaVista Software - Powering the Embedded Revolution - http://www.mvista.com
On Tue, 2003-03-25 at 23:16, Deepak Saxena wrote:
> All,
>
> The following patch updates the PCI subsystem so that root PCI host
> bridges appear as devices hanging off the system bus instead of root
This seems odd for some systems we support. Older PARISC for example
have PCI busses hanging off gecko. I do agree with you for the general
case. So systems whose root level bridges are 'normal' should reflect
this and I guess others should attach them to the relevant bus.
Over time it seems that PCI is going to become a secondary bus like
ISA did as well. In fact it already has in many ways, its just things
like VLINK and the Intel hub busses look like PCI to us
On Mar 26 2003, at 00:35, Alan Cox was caught saying:
> On Tue, 2003-03-25 at 23:16, Deepak Saxena wrote:
> > All,
> >
> > The following patch updates the PCI subsystem so that root PCI host
> > bridges appear as devices hanging off the system bus instead of root
>
> This seems odd for some systems we support. Older PARISC for example
> have PCI busses hanging off gecko. I do agree with you for the general
> case. So systems whose root level bridges are 'normal' should reflect
> this and I guess others should attach them to the relevant bus.
>
> Over time it seems that PCI is going to become a secondary bus like
> ISA did as well. In fact it already has in many ways, its just things
> like VLINK and the Intel hub busses look like PCI to us
Sounds like more reasoning to just force the caller to provide a parent.
'normal' is a moving target and I'd rather not have the code making
assumptions and let the platform's kernel developer explictly map
the PCI bridge into the system.
~Deepak
--
Deepak Saxena
MontaVista Software - Powering the Embedded Revolution - http://www.mvista.com
On Tue, 25 Mar 2003, Deepak Saxena wrote:
> On Mar 26 2003, at 00:35, Alan Cox was caught saying:
> > On Tue, 2003-03-25 at 23:16, Deepak Saxena wrote:
> > > All,
> > >
> > > The following patch updates the PCI subsystem so that root PCI host
> > > bridges appear as devices hanging off the system bus instead of root
> >
> > This seems odd for some systems we support. Older PARISC for example
> > have PCI busses hanging off gecko. I do agree with you for the general
> > case. So systems whose root level bridges are 'normal' should reflect
> > this and I guess others should attach them to the relevant bus.
> >
> > Over time it seems that PCI is going to become a secondary bus like
> > ISA did as well. In fact it already has in many ways, its just things
> > like VLINK and the Intel hub busses look like PCI to us
>
> Sounds like more reasoning to just force the caller to provide a parent.
> 'normal' is a moving target and I'd rather not have the code making
> assumptions and let the platform's kernel developer explictly map
> the PCI bridge into the system.
Actually, that's been the intention all along. The PCI code may not
support it today (I haven't looked at it in a while), but there is no
reason why the parent for a host bridge couldn't be set, and the bridge
show up in the proper place in the hierarchy.
And, if it isn't set, then it shows up under the root, which makes sense
physically and conceptually.
-pat