2004-06-19 20:20:42

by Rafał J. Wysocki

[permalink] [raw]
Subject: Opteron bug

Hi,

I hope everyone interested in the development for Opteron is aware of the bug
described here:

http://www.3dchips.net/content/story.php?id=3927

Yours,
rjw

--
Rafael J. Wysocki,
SiSK
[tel. (+48) 605 053 693]
----------------------------
For a successful technology, reality must take precedence over public
relations, for nature cannot be fooled.
-- Richard P. Feynman


2004-06-20 11:26:34

by Andi Kleen

[permalink] [raw]
Subject: Re: Opteron bug

On Sat, 19 Jun 2004 22:29:14 +0200
"R. J. Wysocki" <[email protected]> wrote:

> Hi,
>
> I hope everyone interested in the development for Opteron is aware of the bug
> described here:
>
> http://www.3dchips.net/content/story.php?id=3927

The kernel never uses backwards REP prefixes.

-Andi

2004-06-20 11:38:39

by Rafał J. Wysocki

[permalink] [raw]
Subject: Re: Opteron bug

On Sunday 20 of June 2004 15:22, Andi Kleen wrote:
> On Sat, 19 Jun 2004 22:29:14 +0200
>
> "R. J. Wysocki" <[email protected]> wrote:
> > Hi,
> >
> > I hope everyone interested in the development for Opteron is aware of the
> > bug described here:
> >
> > http://www.3dchips.net/content/story.php?id=3927
>
> The kernel never uses backwards REP prefixes.

So it doesn't matter. :-)

Well, is there any case in which the gcc can produce such stuff?

rjw

2004-06-20 11:49:30

by Andi Kleen

[permalink] [raw]
Subject: Re: Opteron bug

On Sun, 20 Jun 2004 13:47:17 +0200
"R. J. Wysocki" <[email protected]> wrote:

> On Sunday 20 of June 2004 15:22, Andi Kleen wrote:
> > On Sat, 19 Jun 2004 22:29:14 +0200
> >
> > "R. J. Wysocki" <[email protected]> wrote:
> > > Hi,
> > >
> > > I hope everyone interested in the development for Opteron is aware of the
> > > bug described here:
> > >
> > > http://www.3dchips.net/content/story.php?id=3927
> >
> > The kernel never uses backwards REP prefixes.
>
> So it doesn't matter. :-)

Some user space program could still use it.

You'll have to live with that. CPUs like all other complex
systems have bugs.

> Well, is there any case in which the gcc can produce such stuff?

With inline assembly only I guess.

-Andi

2004-06-20 12:03:15

by Jakub Jelinek

[permalink] [raw]
Subject: Re: Opteron bug

On Sun, Jun 20, 2004 at 01:47:17PM +0200, R. J. Wysocki wrote:
> Well, is there any case in which the gcc can produce such stuff?

GCC doesn't ever generate std instruction (only cld), though users
can use it in inline assembly or assembly source file.
AFAIK x86_64 glibc doesn't use it at all either.

Jakub

2004-06-20 13:08:28

by Manfred Spraul

[permalink] [raw]
Subject: Re: Opteron bug

Andi wrote:

>The kernel never uses backwards REP prefixes.
>
>
Huh? memmove uses backwards rep movsb on x86-64, at least in 2.6.5:

http://lxr.linux.no/source/arch/x86_64/lib/memmove.c?v=2.6.5;a=x86_64#L8

i386 is similar:

http://lxr.linux.no/source/include/asm-i386/string.h?v=2.6.5#L297

But the bug appears to be so rare that it shouldn't matter - lets wait
for the microcode update. Btw, is there a runtime microcode updater for
Opteron cpus, similar to the Intel microcode driver?

--
Manfred

2004-06-20 19:49:35

by Andi Kleen

[permalink] [raw]
Subject: Re: Opteron bug

On Sun, 20 Jun 2004 15:07:59 +0200
Manfred Spraul <[email protected]> wrote:

> Andi wrote:
>
> >The kernel never uses backwards REP prefixes.
> >
> >
> Huh? memmove uses backwards rep movsb on x86-64, at least in 2.6.5:

Hmm, you're right. I forgot that. Ok, I will change it, although
it's unlikely to be a real problem.

> But the bug appears to be so rare that it shouldn't matter - lets wait
> for the microcode update. Btw, is there a runtime microcode updater for
> Opteron cpus, similar to the Intel microcode driver?

AMD seems to only release microcode updates to BIOS vendors.

-Andi

2004-06-21 05:47:19

by Jakub Jelinek

[permalink] [raw]
Subject: Re: Opteron bug

On Mon, Jun 21, 2004 at 02:54:53AM +0300, Denis Vlasenko wrote:
> On Sunday 20 June 2004 15:02, Jakub Jelinek wrote:
> > On Sun, Jun 20, 2004 at 01:47:17PM +0200, R. J. Wysocki wrote:
> > > Well, is there any case in which the gcc can produce such stuff?
> >
> > GCC doesn't ever generate std instruction (only cld), though users
> > can use it in inline assembly or assembly source file.
> > AFAIK x86_64 glibc doesn't use it at all either.
>
> glibc-2.3/sysdeps/i386/memcopy.h:
>
> #define BYTE_COPY_BWD(dst_ep, src_ep, nbytes) \
> do \
> { \
> int __d0; \
> asm volatile(/* Set the direction flag, so copying goes backwards. */ \
> "std\n" \
> /* Copy bytes. */ \
> "rep\n" \
> "movsb\n" \
> /* Clear the dir flag. Convention says it should be 0. */ \
> "cld" : \
> "=D" (dst_ep), "=S" (src_ep), "=c" (__d0) : \
> "0" (dst_ep - 1), "1" (src_ep - 1), "2" (nbytes) : \
> "memory"); \
> dst_ep += 1; \
> src_ep += 1; \
> } while (0)
>
> WORD_COPY_BWD also does this

I know, but I said x86_64 glibc, which doesn't do this.

Jakub