Hello,
Clearing PCI Command bits fixes machine halts observed during sizing
seqences using MMIO cycles. Clearing the bits is suggested by an
implementation note in the PCI spec.
Thanks,
Patrick
Signed-off-by: Patrick Jefferson <[email protected]>
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -147,7 +147,7 @@ static u32 pci_size(u32 base, u32 maxbas
static void pci_read_bases(struct pci_dev *dev, unsigned int howmany,
int rom)
{
unsigned int pos, reg, next;
- u32 l, sz;
+ u32 l, sz, cmd;
struct resource *res;
for(pos=0; pos<howmany; pos = next) {
@@ -155,10 +155,14 @@ static void pci_read_bases(struct pci_de
res = &dev->resource[pos];
res->name = pci_name(dev);
reg = PCI_BASE_ADDRESS_0 + (pos << 2);
+ /* disable Memory & I/O decoders before sizing a BAR */
+ pci_read_config_dword(dev, PCI_COMMAND, &cmd);
+ pci_write_config_dword(dev, PCI_COMMAND, cmd &
~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
pci_read_config_dword(dev, reg, &l);
pci_write_config_dword(dev, reg, ~0);
pci_read_config_dword(dev, reg, &sz);
pci_write_config_dword(dev, reg, l);
+ pci_write_config_dword(dev, PCI_COMMAND, cmd);
if (!sz || sz == 0xffffffff)
continue;
if (l == 0xffffffff)
On Tue, May 23, 2006 at 12:28:10PM +0000, Patrick Jefferson wrote:
> Clearing PCI Command bits fixes machine halts observed during sizing
> seqences using MMIO cycles. Clearing the bits is suggested by an
> implementation note in the PCI spec.
The patch is not acceptable. This was discussed back in 2002:
http://www.uwsg.iu.edu/hypermail/linux/kernel/0212.2/index.html#978
Ivan.
On Wed, May 24, 2006 at 02:06:54AM +0400, Ivan Kokshaysky wrote:
> On Tue, May 23, 2006 at 12:28:10PM +0000, Patrick Jefferson wrote:
> > Clearing PCI Command bits fixes machine halts observed during sizing
> > seqences using MMIO cycles. Clearing the bits is suggested by an
> > implementation note in the PCI spec.
>
> The patch is not acceptable. This was discussed back in 2002:
>
> http://www.uwsg.iu.edu/hypermail/linux/kernel/0212.2/index.html#978
I agree, it's not going to be accepted.
Patrick, are you trying to solve the same thing that Grant was back in
2002? Why do you feel this patch is necessary?
thanks,
greg k-h
Greg KH wrote:
> On Wed, May 24, 2006 at 02:06:54AM +0400, Ivan Kokshaysky wrote:
>
>>On Tue, May 23, 2006 at 12:28:10PM +0000, Patrick Jefferson wrote:
>>
>>>Clearing PCI Command bits fixes machine halts observed during sizing
>>>seqences using MMIO cycles. Clearing the bits is suggested by an
>>>implementation note in the PCI spec.
>>
>>The patch is not acceptable. This was discussed back in 2002:
>>
>> http://www.uwsg.iu.edu/hypermail/linux/kernel/0212.2/index.html#978
>
>
> I agree, it's not going to be accepted.
>
> Patrick, are you trying to solve the same thing that Grant was back in
> 2002? Why do you feel this patch is necessary?
No. The problem is similar, involving colliding addresses, but
critically different. Sizing a device's BAR via memory-mapped
configuration space accesses will do spectacular things when the size,
say E0000000, unforeseeably equals the mapped config space address, like
E0000000. The Memory bit in the PCI Command register must be cleared.
Either a) some other specific sequence exists for safe sizing,
Or b) disabling memory decoding by the device must be allowed, at
minimum, as a special case,
Or c) a switch from MMCONFIG to CF8/CFC and back again should be used
when sizing,
Or d) the resulting machine crash is acceptable during linux boot.
The patch, since it addresses d), is necessary unless b) or c) are
feasible, or a) exists.
Any suggestions would be appreciated.
Thanks,
Patrick