2006-09-24 01:15:38

by Dave Jones

Subject: New Intel feature flags.

Add supplemental SSE3 instructions flag, and Direct Cache Access flag.
As described in "Intel Processor idenfication and the CPUID instruction
AP485 Sept 2006"

Signed-off-by: Dave Jones <[email protected]>

--- local-git/arch/i386/kernel/cpu/proc.c~ 2006-09-23 20:46:35.000000000 -0400
+++ local-git/arch/i386/kernel/cpu/proc.c 2006-09-23 20:48:02.000000000 -0400
@@ -46,8 +46,8 @@ static int show_cpuinfo(struct seq_file

/* Intel-defined (#2) */
"pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
- "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
+ NULL, NULL, "dca", NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

/* VIA/Cyrix/Centaur-defined */

--
http://www.codemonkey.org.uk

2006-09-24 01:21:09

by Michal Piotrowski

Subject: Re: New Intel feature flags.

Hi Dave,

On 24/09/06, Dave Jones <[email protected]> wrote:
> Add supplemental SSE3 instructions flag, and Direct Cache Access flag.
> As described in "Intel Processor idenfication and the CPUID instruction
> AP485 Sept 2006"
>
> Signed-off-by: Dave Jones <[email protected]>
>
> --- local-git/arch/i386/kernel/cpu/proc.c~ 2006-09-23 20:46:35.000000000 -0400
> +++ local-git/arch/i386/kernel/cpu/proc.c 2006-09-23 20:48:02.000000000 -0400
> @@ -46,8 +46,8 @@ static int show_cpuinfo(struct seq_file
>
> /* Intel-defined (#2) */
> "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
> - "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
> - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
> + "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,

ssse3? Typo?

> + NULL, NULL, "dca", NULL, NULL, NULL, NULL, NULL,
> NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
>
> /* VIA/Cyrix/Centaur-defined */
>
> --
> http://www.codemonkey.org.uk
> -

Regards,
Michal

--
Michal K. K. Piotrowski
LTG - Linux Testers Group
(http://www.stardust.webpages.pl/ltg/)

2006-09-24 01:28:28

by Dave Jones

Subject: Re: New Intel feature flags.

On Sun, Sep 24, 2006 at 03:21:06AM +0200, Michal Piotrowski wrote:
> Hi Dave,
>
> On 24/09/06, Dave Jones <[email protected]> wrote:
> > Add supplemental SSE3 instructions flag, and Direct Cache Access flag.
> > As described in "Intel Processor idenfication and the CPUID instruction
> > AP485 Sept 2006"
> >
> > Signed-off-by: Dave Jones <[email protected]>
> >
> > --- local-git/arch/i386/kernel/cpu/proc.c~ 2006-09-23 20:46:35.000000000 -0400
> > +++ local-git/arch/i386/kernel/cpu/proc.c 2006-09-23 20:48:02.000000000 -0400
> > @@ -46,8 +46,8 @@ static int show_cpuinfo(struct seq_file
> >
> > /* Intel-defined (#2) */
> > "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
> > - "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
> > - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
> > + "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
>
> ssse3? Typo?

No. It stands for Supplemental SSE3. SSE is already indicated by 'pni'.

Dave

2006-09-24 08:49:52

by Andi Kleen

Subject: Re: New Intel feature flags.

On Sunday 24 September 2006 03:15, Dave Jones wrote:
> Add supplemental SSE3 instructions flag, and Direct Cache Access flag.
> As described in "Intel Processor idenfication and the CPUID instruction
> AP485 Sept 2006"

Added thanks. I also added it for x86-64

-Andi

2006-09-24 18:28:15

by Dave Jones

Subject: Re: New Intel feature flags.

On Sun, Sep 24, 2006 at 10:50:14AM +0200, Andi Kleen wrote:
> On Sunday 24 September 2006 03:15, Dave Jones wrote:
> > Add supplemental SSE3 instructions flag, and Direct Cache Access flag.
> > As described in "Intel Processor idenfication and the CPUID instruction
> > AP485 Sept 2006"
>
> Added thanks. I also added it for x86-64

Want a patch to make these shared?

Dave

2006-09-25 03:02:25

by Dave Jones

Subject: Re: New Intel feature flags.

On Sun, Sep 24, 2006 at 10:50:14AM +0200, Andi Kleen wrote:
> On Sunday 24 September 2006 03:15, Dave Jones wrote:
> > Add supplemental SSE3 instructions flag, and Direct Cache Access flag.
> > As described in "Intel Processor idenfication and the CPUID instruction
> > AP485 Sept 2006"
>
> Added thanks. I also added it for x86-64

I just looked at ftp://ftp.firstfloor.org/pub/ak/x86_64/quilt-current/patches/new-intel-cpuid-flags
Somehow "ssse3" became "ssse2".

Dave

2006-09-25 03:05:15

by Andi Kleen

Subject: Re: New Intel feature flags.

On Monday 25 September 2006 05:02, Dave Jones wrote:
> On Sun, Sep 24, 2006 at 10:50:14AM +0200, Andi Kleen wrote:
> > On Sunday 24 September 2006 03:15, Dave Jones wrote:
> > > Add supplemental SSE3 instructions flag, and Direct Cache Access flag.
> > > As described in "Intel Processor idenfication and the CPUID instruction
> > > AP485 Sept 2006"
> >
> > Added thanks. I also added it for x86-64
>
> I just looked at ftp://ftp.firstfloor.org/pub/ak/x86_64/quilt-current/patches/new-intel-cpuid-flags
> Somehow "ssse3" became "ssse2".


Sorry fixed.

-Andi