2007-08-07 20:14:12

by Yinghai Lu

Subject: [PATCH] x86_64: clear IO_APIC before enabing apic error vector.

[PATCH] x86_64: clear IO_APIC before enabing apic error vector.

some apic id lifting system: 4 socket quad core, 8 socket quad core will do apic id lifting for BSP.

but io-apic regs for ExtINT still use 0 as dest.

so when we enable apic error vector in BSP, we will get one APIC error.

CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 512K (64 bytes/line)
CPU 0/4 -> Node 0
CPU: Physical Processor ID: 1
CPU: Processor Core ID: 0
SMP alternatives: switching to UP code
ACPI: Core revision 20070126
enabled ExtINT on CPU#0
ESR value after enabling vector: 00000000, after 0000000c
APIC error on CPU0: 0c(08)
ENABLING IO-APIC IRQs
Synchronizing Arb IDs.

So move enable_IO_APIC from setup_IO_APIC into setup_local_APIC and call it
before enabling apic error vector.

Signed-off-by: Yinghai Lu <[email protected]>

diff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c
index 900ff38..a2ae138 100644
--- a/arch/x86_64/kernel/apic.c
+++ b/arch/x86_64/kernel/apic.c
@@ -436,6 +436,14 @@ void __cpuinit setup_local_APIC (void)
value = APIC_DM_NMI | APIC_LVT_MASKED;
apic_write(APIC_LVT1, value);

+ /*
+ * Now enable IO-APICs, actually call clear_IO_APIC
+ * We need clear_IO_APIC before enabling vector on BP
+ */
+ if (!smp_processor_id())
+ if (!skip_ioapic_setup && nr_ioapics)
+ enable_IO_APIC();
+
{
unsigned oldvalue;
maxlvt = get_maxlvt();
diff --git a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c
index 050141c..a537c2f 100644
--- a/arch/x86_64/kernel/io_apic.c
+++ b/arch/x86_64/kernel/io_apic.c
@@ -1165,7 +1165,7 @@ void __apicdebuginit print_PIC(void)

#endif /* 0 */

-static void __init enable_IO_APIC(void)
+void __init enable_IO_APIC(void)
{
union IO_APIC_reg_01 reg_01;
int i8259_apic, i8259_pin;
@@ -1774,7 +1774,10 @@ __setup("no_timer_check", notimercheck);

void __init setup_IO_APIC(void)
{
- enable_IO_APIC();
+
+ /*
+ * calling enable_IO_APIC() is moved to setup_local_APIC for BP
+ */

if (acpi_ioapic)
io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
diff --git a/include/asm-x86_64/hw_irq.h b/include/asm-x86_64/hw_irq.h
index 09dfc18..31aa656 100644
--- a/include/asm-x86_64/hw_irq.h
+++ b/include/asm-x86_64/hw_irq.h
@@ -135,6 +135,7 @@ extern void init_8259A(int aeoi);
extern void send_IPI_self(int vector);
extern void init_VISWS_APIC_irqs(void);
extern void setup_IO_APIC(void);
+extern void enable_IO_APIC(void);
extern void disable_IO_APIC(void);
extern void print_IO_APIC(void);
extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);

2007-08-08 15:56:36

by Joachim Deguara

Subject: Re: [PATCH] x86_64: clear IO_APIC before enabing apic error vector.

On Tuesday 07 August 2007 22:19:35 Yinghai Lu wrote:
> [PATCH] x86_64: clear IO_APIC before enabing apic error vector.
>
> some apic id lifting system: 4 socket quad core, 8 socket quad core will do
> apic id lifting for BSP.
>
> but io-apic regs for ExtINT still use 0 as dest.

good catch!

> diff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c
> index 900ff38..a2ae138 100644
> --- a/arch/x86_64/kernel/apic.c
> +++ b/arch/x86_64/kernel/apic.c
> @@ -436,6 +436,14 @@ void __cpuinit setup_local_APIC (void)
> value = APIC_DM_NMI | APIC_LVT_MASKED;
> apic_write(APIC_LVT1, value);
>
> + /*
> + * Now enable IO-APICs, actually call clear_IO_APIC
> + * We need clear_IO_APIC before enabling vector on BP
> + */
> + if (!smp_processor_id())
> + if (!skip_ioapic_setup && nr_ioapics)
> + enable_IO_APIC();

Surely you meant something prettier like
+ if (!smp_processor_id() && !skip_ioapic_setup && nr_ioapics)
+ enable_IO_APIC();

-Joachim