adds AMD Northbridge config MSR definition
Signed-off-by: Stephane Eranian <[email protected]>
Signed-off-by: Robert Richter <[email protected]>
On 06.03.08 22:25:26, stephane eranian wrote:
> adds AMD Northbridge config MSR definition
>
> Signed-off-by: Stephane Eranian <[email protected]>
> Signed-off-by: Robert Richter <[email protected]>
> --- a/include/asm-x86/msr-index.h
> +++ b/include/asm-x86/msr-index.h
> @@ -83,6 +83,7 @@
> /* AMD64 MSRs. Not complete. See the architecture manual for a more
> complete list. */
>
> +#define MSR_AMD64_NB_CFG 0xc001001f
This will probably not be needed after mm config works fine (patches
from Yinghai Lu). Since the usage of CF8 extended configuration cycles
is not recommended, the current code to enable IBS interrupts can be
seen as temporary. I will rework the IBS code so that it uses mm
config.
-Robert
--
Advanced Micro Devices, Inc.
Operating System Research Center
email: [email protected]
Robert,
On Fri, Mar 7, 2008 at 3:42 AM, Robert Richter <[email protected]> wrote:
>
> On 06.03.08 22:25:26, stephane eranian wrote:
> > adds AMD Northbridge config MSR definition
> >
> > Signed-off-by: Stephane Eranian <[email protected]>
> > Signed-off-by: Robert Richter <[email protected]>
>
> > --- a/include/asm-x86/msr-index.h
> > +++ b/include/asm-x86/msr-index.h
> > @@ -83,6 +83,7 @@
> > /* AMD64 MSRs. Not complete. See the architecture manual for a more
> > complete list. */
> >
> > +#define MSR_AMD64_NB_CFG 0xc001001f
>
> This will probably not be needed after mm config works fine (patches
> from Yinghai Lu). Since the usage of CF8 extended configuration cycles
> is not recommended, the current code to enable IBS interrupts can be
> seen as temporary. I will rework the IBS code so that it uses mm
> config.
>
Ok, but I want to push what we have now. We can change this later.
On 07.03.08 13:01:18, stephane eranian wrote:
> Ok, but I want to push what we have now. We can change this later.
Agree.
-Robert
--
Advanced Micro Devices, Inc.
Operating System Research Center
email: [email protected]