2008-06-18 05:30:32

by Zhenyu Wang

[permalink] [raw]

Subject: [PATCH] [AGP] intel_agp: Add support for Intel 4 series chipsets

---

Dave, here's the patch against current git master.

Thanks.

[AGP] intel_agp: Add support for Intel 4 series chipsets

Signed-off-by: Zhenyu Wang <[email protected]>
---
drivers/char/agp/intel-agp.c | 82 ++++++++++++++++++++++++++++++++++++-----
1 files changed, 72 insertions(+), 10 deletions(-)

diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index eeea50a..76731db 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -34,6 +34,12 @@
#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
+#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
+#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
+#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
+#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
+#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
+#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22

/* cover 915 and 945 variants */
#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -55,6 +61,10 @@
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)

+#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
+ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
+ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
+
extern int agp_memory_reserved;


@@ -80,8 +90,12 @@ extern int agp_memory_reserved;
#define I915_PTEADDR 0x1C
#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
-#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
-#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
+#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
+#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
+#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
+#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
+#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
+#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
#define I915_IFPADDR 0x60

/* Intel 965G registers */
@@ -504,6 +518,10 @@ static void intel_i830_init_gtt_entries(void)
size = 512;
}
size += 4;
+ } else if (IS_G4X) {
+ /* On 4 Series hardware, GTT stolen is seperate from graphics
+ * stolen, ignore it in stolen gtt entries counting */
+ size = 0;
} else {
/* On previous hardware, the GTT size was just what was
* required to map the aperture.
@@ -552,30 +570,54 @@ static void intel_i830_init_gtt_entries(void)
break;
case I915_GMCH_GMS_STOLEN_48M:
/* Check it's really I915G */
- if (IS_I915 || IS_I965 || IS_G33)
+ if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
gtt_entries = MB(48) - KB(size);
else
gtt_entries = 0;
break;
case I915_GMCH_GMS_STOLEN_64M:
/* Check it's really I915G */
- if (IS_I915 || IS_I965 || IS_G33)
+ if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
gtt_entries = MB(64) - KB(size);
else
gtt_entries = 0;
break;
case G33_GMCH_GMS_STOLEN_128M:
- if (IS_G33)
+ if (IS_G33 || IS_I965 || IS_G4X)
gtt_entries = MB(128) - KB(size);
else
gtt_entries = 0;
break;
case G33_GMCH_GMS_STOLEN_256M:
- if (IS_G33)
+ if (IS_G33 || IS_I965 || IS_G4X)
gtt_entries = MB(256) - KB(size);
else
gtt_entries = 0;
break;
+ case INTEL_GMCH_GMS_STOLEN_96M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(96) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
+ case INTEL_GMCH_GMS_STOLEN_160M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(160) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
+ case INTEL_GMCH_GMS_STOLEN_224M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(224) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
+ case INTEL_GMCH_GMS_STOLEN_352M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(352) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
default:
gtt_entries = 0;
break;
@@ -1134,6 +1176,20 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
return addr | bridge->driver->masks[type].mask;
}

+static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
+{
+ switch(agp_bridge->dev->device) {
+ case PCI_DEVICE_ID_INTEL_IGD_HB:
+ case PCI_DEVICE_ID_INTEL_IGD_E_HB:
+ case PCI_DEVICE_ID_INTEL_Q45_HB:
+ case PCI_DEVICE_ID_INTEL_G45_HB:
+ *gtt_offset = *gtt_size = MB(2);
+ break;
+ default:
+ *gtt_offset = *gtt_size = KB(512);
+ }
+}
+
/* The intel i965 automatically initializes the agp aperture during POST.
* Use the memory already set aside for in the GTT.
*/
@@ -1154,10 +1210,7 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)

temp &= 0xfff00000;

- if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
- gtt_offset = gtt_size = MB(2);
- else
- gtt_offset = gtt_size = KB(512);
+ intel_i965_get_gtt_range(&gtt_offset, &gtt_size);

intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);

@@ -2063,6 +2116,12 @@ static const struct intel_driver_description {
NULL, &intel_g33_driver },
{ PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
"Intel Integrated Graphics Device", NULL, &intel_i965_driver },
+ { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
+ "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
+ { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
+ "Q45/Q43", NULL, &intel_i965_driver },
+ { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
+ "G45/G43", NULL, &intel_i965_driver },
{ 0, 0, 0, NULL, NULL, NULL }
};

@@ -2254,6 +2313,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
ID(PCI_DEVICE_ID_INTEL_Q35_HB),
ID(PCI_DEVICE_ID_INTEL_Q33_HB),
ID(PCI_DEVICE_ID_INTEL_IGD_HB),
+ ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
+ ID(PCI_DEVICE_ID_INTEL_Q45_HB),
+ ID(PCI_DEVICE_ID_INTEL_G45_HB),
{ }
};

--
1.5.4

--
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2008-06-18 07:25:36

by Dmitri Vorobiev

[permalink] [raw]

Subject: Re: [PATCH] [AGP] intel_agp: Add support for Intel 4 series chipsets

---

Zhenyu Wang wrote:
> Dave, here's the patch against current git master.
>
> Thanks.
>
> [AGP] intel_agp: Add support for Intel 4 series chipsets
>
> Signed-off-by: Zhenyu Wang <[email protected]>
> ---
> drivers/char/agp/intel-agp.c | 82 ++++++++++++++++++++++++++++++++++++-----
> 1 files changed, 72 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
> index eeea50a..76731db 100644
> --- a/drivers/char/agp/intel-agp.c
> +++ b/drivers/char/agp/intel-agp.c
> @@ -34,6 +34,12 @@
> #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
> #define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
> #define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
> +#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
> +#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
> +#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
> +#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
> +#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
> +#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
>
> /* cover 915 and 945 variants */
> #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
> @@ -55,6 +61,10 @@
> agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
> agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
>
> +#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
> + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
> + agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
> +
> extern int agp_memory_reserved;
>
>
> @@ -80,8 +90,12 @@ extern int agp_memory_reserved;
> #define I915_PTEADDR 0x1C
> #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
> #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
> -#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
> -#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
> +#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
> +#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
> +#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
> +#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
> +#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
> +#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
> #define I915_IFPADDR 0x60
>
> /* Intel 965G registers */
> @@ -504,6 +518,10 @@ static void intel_i830_init_gtt_entries(void)
> size = 512;
> }
> size += 4;
> + } else if (IS_G4X) {
> + /* On 4 Series hardware, GTT stolen is seperate from graphics

You have a spelling error here. Should be "separate".

Thanks,
Dmitri

2008-06-18 07:41:41

by Zhenyu Wang

[permalink] [raw]

Subject: Re: [PATCH] [AGP] intel_agp: Add support for Intel 4 series chipsets

---

On 2008.06.18 10:26:10 +0300, Dmitri Vorobiev wrote:
> > + } else if (IS_G4X) {
> > + /* On 4 Series hardware, GTT stolen is seperate from graphics
>
> You have a spelling error here. Should be "separate".
>

Thanks, updated as below with typo and indent fix.

[AGP] intel_agp: Add support for Intel 4 series chipsets

Signed-off-by: Zhenyu Wang <[email protected]>
---
drivers/char/agp/intel-agp.c | 82 ++++++++++++++++++++++++++++++++++++-----
1 files changed, 72 insertions(+), 10 deletions(-)

diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index eeea50a..efd6132 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -34,6 +34,12 @@
#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
+#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
+#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
+#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
+#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
+#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
+#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22

/* cover 915 and 945 variants */
#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -55,6 +61,10 @@
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)

+#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
+ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
+ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
+
extern int agp_memory_reserved;


@@ -80,8 +90,12 @@ extern int agp_memory_reserved;
#define I915_PTEADDR 0x1C
#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
-#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
-#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
+#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
+#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
+#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
+#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
+#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
+#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
#define I915_IFPADDR 0x60

/* Intel 965G registers */
@@ -504,6 +518,10 @@ static void intel_i830_init_gtt_entries(void)
size = 512;
}
size += 4;
+ } else if (IS_G4X) {
+ /* On 4 Series hardware, GTT stolen is separate from graphics
+ * stolen, ignore it in stolen gtt entries counting */
+ size = 0;
} else {
/* On previous hardware, the GTT size was just what was
* required to map the aperture.
@@ -552,30 +570,54 @@ static void intel_i830_init_gtt_entries(void)
break;
case I915_GMCH_GMS_STOLEN_48M:
/* Check it's really I915G */
- if (IS_I915 || IS_I965 || IS_G33)
+ if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
gtt_entries = MB(48) - KB(size);
else
gtt_entries = 0;
break;
case I915_GMCH_GMS_STOLEN_64M:
/* Check it's really I915G */
- if (IS_I915 || IS_I965 || IS_G33)
+ if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
gtt_entries = MB(64) - KB(size);
else
gtt_entries = 0;
break;
case G33_GMCH_GMS_STOLEN_128M:
- if (IS_G33)
+ if (IS_G33 || IS_I965 || IS_G4X)
gtt_entries = MB(128) - KB(size);
else
gtt_entries = 0;
break;
case G33_GMCH_GMS_STOLEN_256M:
- if (IS_G33)
+ if (IS_G33 || IS_I965 || IS_G4X)
gtt_entries = MB(256) - KB(size);
else
gtt_entries = 0;
break;
+ case INTEL_GMCH_GMS_STOLEN_96M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(96) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
+ case INTEL_GMCH_GMS_STOLEN_160M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(160) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
+ case INTEL_GMCH_GMS_STOLEN_224M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(224) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
+ case INTEL_GMCH_GMS_STOLEN_352M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(352) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
default:
gtt_entries = 0;
break;
@@ -1134,6 +1176,20 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
return addr | bridge->driver->masks[type].mask;
}

+static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
+{
+ switch (agp_bridge->dev->device) {
+ case PCI_DEVICE_ID_INTEL_IGD_HB:
+ case PCI_DEVICE_ID_INTEL_IGD_E_HB:
+ case PCI_DEVICE_ID_INTEL_Q45_HB:
+ case PCI_DEVICE_ID_INTEL_G45_HB:
+ *gtt_offset = *gtt_size = MB(2);
+ break;
+ default:
+ *gtt_offset = *gtt_size = KB(512);
+ }
+}
+
/* The intel i965 automatically initializes the agp aperture during POST.
* Use the memory already set aside for in the GTT.
*/
@@ -1154,10 +1210,7 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)

temp &= 0xfff00000;

- if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
- gtt_offset = gtt_size = MB(2);
- else
- gtt_offset = gtt_size = KB(512);
+ intel_i965_get_gtt_range(&gtt_offset, &gtt_size);

intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);

@@ -2063,6 +2116,12 @@ static const struct intel_driver_description {
NULL, &intel_g33_driver },
{ PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
"Intel Integrated Graphics Device", NULL, &intel_i965_driver },
+ { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
+ "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
+ { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
+ "Q45/Q43", NULL, &intel_i965_driver },
+ { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
+ "G45/G43", NULL, &intel_i965_driver },
{ 0, 0, 0, NULL, NULL, NULL }
};

@@ -2254,6 +2313,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
ID(PCI_DEVICE_ID_INTEL_Q35_HB),
ID(PCI_DEVICE_ID_INTEL_Q33_HB),
ID(PCI_DEVICE_ID_INTEL_IGD_HB),
+ ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
+ ID(PCI_DEVICE_ID_INTEL_Q45_HB),
+ ID(PCI_DEVICE_ID_INTEL_G45_HB),
{ }
};

--
1.5.4


--
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2008-06-19 01:02:57

by Zhenyu Wang

[permalink] [raw]

Subject: Re: [PATCH] [AGP] intel_agp: Add support for Intel 4 series chipsets

---

On 2008.06.18 15:34:07 +0800, Zhenyu Wang wrote:
> Thanks, updated as below with typo and indent fix.
>
> [AGP] intel_agp: Add support for Intel 4 series chipsets
>

I believe now that this one might be better to be split,
as it does contain a fix on IGD_GM chipset for extra stolen
memory size available, and it's good to be included in 2.6.26.
New Intel 4 series chipset enabling patch could be queued for
next kernel.

---

[AGP] intel_agp: extra stolen mem size available for IGD_GM chipset

This adds missing stolen memory size detect for IGD_GM, be sure to
detect right size as current X intel driver (2.3.2) which has already
worked out.

Signed-off-by: Zhenyu Wang <[email protected]>
---
drivers/char/agp/intel-agp.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index eeea50a..ba9718f 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -565,13 +565,13 @@ static void intel_i830_init_gtt_entries(void)
gtt_entries = 0;
break;
case G33_GMCH_GMS_STOLEN_128M:
- if (IS_G33)
+ if (IS_G33 || IS_I965)
gtt_entries = MB(128) - KB(size);
else
gtt_entries = 0;
break;
case G33_GMCH_GMS_STOLEN_256M:
- if (IS_G33)
+ if (IS_G33 || IS_I965)
gtt_entries = MB(256) - KB(size);
else
gtt_entries = 0;
--
1.5.4

--
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2008-06-19 01:04:27

by Zhenyu Wang

[permalink] [raw]

Subject: Re: [PATCH] [AGP] intel_agp: Add support for Intel 4 series chipsets

---

On 2008.06.19 08:55:10 +0800, Zhenyu Wang wrote:
> I believe now that this one might be better to be split,
> as it does contain a fix on IGD_GM chipset for extra stolen
> memory size available, and it's good to be included in 2.6.26.
> New Intel 4 series chipset enabling patch could be queued for
> next kernel.
>

[AGP] intel_agp: Add support for Intel 4 series chipsets

Signed-off-by: Zhenyu Wang <[email protected]>
---
drivers/char/agp/intel-agp.c | 84 ++++++++++++++++++++++++++++++++++++------
1 files changed, 72 insertions(+), 12 deletions(-)

diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index ba9718f..189b325 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -34,6 +34,12 @@
#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
+#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
+#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
+#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
+#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
+#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
+#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22

/* cover 915 and 945 variants */
#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -55,6 +61,10 @@
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)

+#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
+ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
+ agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB)
+
extern int agp_memory_reserved;


@@ -80,8 +90,12 @@ extern int agp_memory_reserved;
#define I915_PTEADDR 0x1C
#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
-#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
-#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
+#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
+#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
+#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
+#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
+#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
+#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
#define I915_IFPADDR 0x60

/* Intel 965G registers */
@@ -504,6 +518,10 @@ static void intel_i830_init_gtt_entries(void)
size = 512;
}
size += 4;
+ } else if (IS_G4X) {
+ /* On 4 Series hardware, GTT stolen is separate from graphics
+ * stolen, ignore it in stolen gtt entries counting */
+ size = 0;
} else {
/* On previous hardware, the GTT size was just what was
* required to map the aperture.
@@ -551,31 +569,53 @@ static void intel_i830_init_gtt_entries(void)
gtt_entries = MB(32) - KB(size);
break;
case I915_GMCH_GMS_STOLEN_48M:
- /* Check it's really I915G */
- if (IS_I915 || IS_I965 || IS_G33)
+ if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
gtt_entries = MB(48) - KB(size);
else
gtt_entries = 0;
break;
case I915_GMCH_GMS_STOLEN_64M:
- /* Check it's really I915G */
- if (IS_I915 || IS_I965 || IS_G33)
+ if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
gtt_entries = MB(64) - KB(size);
else
gtt_entries = 0;
break;
case G33_GMCH_GMS_STOLEN_128M:
- if (IS_G33 || IS_I965)
+ if (IS_G33 || IS_I965 || IS_G4X)
gtt_entries = MB(128) - KB(size);
else
gtt_entries = 0;
break;
case G33_GMCH_GMS_STOLEN_256M:
- if (IS_G33 || IS_I965)
+ if (IS_G33 || IS_I965 || IS_G4X)
gtt_entries = MB(256) - KB(size);
else
gtt_entries = 0;
break;
+ case INTEL_GMCH_GMS_STOLEN_96M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(96) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
+ case INTEL_GMCH_GMS_STOLEN_160M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(160) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
+ case INTEL_GMCH_GMS_STOLEN_224M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(224) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
+ case INTEL_GMCH_GMS_STOLEN_352M:
+ if (IS_I965 || IS_G4X)
+ gtt_entries = MB(352) - KB(size);
+ else
+ gtt_entries = 0;
+ break;
default:
gtt_entries = 0;
break;
@@ -1134,6 +1174,20 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
return addr | bridge->driver->masks[type].mask;
}

+static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
+{
+ switch (agp_bridge->dev->device) {
+ case PCI_DEVICE_ID_INTEL_IGD_HB:
+ case PCI_DEVICE_ID_INTEL_IGD_E_HB:
+ case PCI_DEVICE_ID_INTEL_Q45_HB:
+ case PCI_DEVICE_ID_INTEL_G45_HB:
+ *gtt_offset = *gtt_size = MB(2);
+ break;
+ default:
+ *gtt_offset = *gtt_size = KB(512);
+ }
+}
+
/* The intel i965 automatically initializes the agp aperture during POST.
* Use the memory already set aside for in the GTT.
*/
@@ -1154,10 +1208,7 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)

temp &= 0xfff00000;

- if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
- gtt_offset = gtt_size = MB(2);
- else
- gtt_offset = gtt_size = KB(512);
+ intel_i965_get_gtt_range(&gtt_offset, &gtt_size);

intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);

@@ -2063,6 +2114,12 @@ static const struct intel_driver_description {
NULL, &intel_g33_driver },
{ PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
"Intel Integrated Graphics Device", NULL, &intel_i965_driver },
+ { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
+ "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
+ { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
+ "Q45/Q43", NULL, &intel_i965_driver },
+ { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
+ "G45/G43", NULL, &intel_i965_driver },
{ 0, 0, 0, NULL, NULL, NULL }
};

@@ -2254,6 +2311,9 @@ static struct pci_device_id agp_intel_pci_table[] = {
ID(PCI_DEVICE_ID_INTEL_Q35_HB),
ID(PCI_DEVICE_ID_INTEL_Q33_HB),
ID(PCI_DEVICE_ID_INTEL_IGD_HB),
+ ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
+ ID(PCI_DEVICE_ID_INTEL_Q45_HB),
+ ID(PCI_DEVICE_ID_INTEL_G45_HB),
{ }
};

--
1.5.4



--
Open Source Technology Center, Intel ltd.

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