This adds support for break on/off to the EPCA driver, thanks to Digi providing
the needed firmware info. It also adds a pile of OxSemi devices to the 8250_pci
drivers, these being the 'Tornado' series adapters. They actually have a pile
of additional functionality it would be nice to support but this simply teaches
the kernel to recognize them and identify them nicely.
---
Alan Cox (1):
epca: Add infinite break support
Lee Howard (2):
8250: Add more OxSemi devices
8250: Oxford Semiconductor Devices
drivers/char/epca.c | 6 +
drivers/parport/parport_pc.c | 20 +++-
drivers/serial/8250_pci.c | 231 ++++++++++++++++++++++++++++++++++++++++++
include/linux/pci_ids.h | 8 +
4 files changed, 263 insertions(+), 2 deletions(-)
--
"Intel sued Cyrix five times and they never won. Intel they just love lawsuits"
-- Wen Chi Chen, Via's CEO
From: Alan Cox <[email protected]>
The EPCA can support indefinte break lengths and with info from digi that
can now be added
Signed-off-by: Alan Cox <[email protected]>
---
drivers/char/epca.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/char/epca.c b/drivers/char/epca.c
index 4998b27..cf2461d 100644
--- a/drivers/char/epca.c
+++ b/drivers/char/epca.c
@@ -2477,7 +2477,11 @@ static int pc_send_break(struct tty_struct *tty, int msec)
unsigned long flags;
if (msec == -1)
- return -EOPNOTSUPP;
+ msec = 0xFFFF;
+ else if (msec > 0xFFFE)
+ msec = 0xFFFE;
+ else if (msec < 1)
+ msec = 1;
spin_lock_irqsave(&epca_lock, flags);
globalwinon(ch);
From: Lee Howard <[email protected]>
Add support for the OxSemi 'Tornado' devices.
Orginal from Lee Howard
Reformatted and reworked a bit by Alan Cox
Signed-off-by: Lee Howard <[email protected]>
Signed-off-by: Alan Cox <[email protected]>
---
drivers/parport/parport_pc.c | 20 ++++
drivers/serial/8250_pci.c | 211 ++++++++++++++++++++++++++++++++++++++++++
include/linux/pci_ids.h | 8 ++
3 files changed, 238 insertions(+), 1 deletions(-)
diff --git a/drivers/parport/parport_pc.c b/drivers/parport/parport_pc.c
index 8a846ad..96f3bdf 100644
--- a/drivers/parport/parport_pc.c
+++ b/drivers/parport/parport_pc.c
@@ -2791,6 +2791,7 @@ enum parport_pc_pci_cards {
oxsemi_952,
oxsemi_954,
oxsemi_840,
+ oxsemi_pcie_pport,
aks_0100,
mobility_pp,
netmos_9705,
@@ -2868,6 +2869,7 @@ static struct parport_pc_pci {
/* oxsemi_952 */ { 1, { { 0, 1 }, } },
/* oxsemi_954 */ { 1, { { 0, -1 }, } },
/* oxsemi_840 */ { 1, { { 0, 1 }, } },
+ /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
/* aks_0100 */ { 1, { { 0, -1 }, } },
/* mobility_pp */ { 1, { { 0, 1 }, } },
/* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */
@@ -2928,7 +2930,6 @@ static const struct pci_device_id parport_pc_pci_tbl[] = {
{ 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
{ 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
{ 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
- { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
{ PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
{ PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
@@ -2946,8 +2947,25 @@ static const struct pci_device_id parport_pc_pci_tbl[] = {
PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
+ { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
+ { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
+ { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
+ { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
+ { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
+ { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
+ { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
+ { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
{ PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
+ { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
/* NetMos communication controllers */
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index c014ffb..43c990a 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -1100,6 +1100,8 @@ enum pci_board_num_t {
pbn_b0_4_1843200_200,
pbn_b0_8_1843200_200,
+ pbn_b0_1_4000000,
+
pbn_b0_bt_1_115200,
pbn_b0_bt_2_115200,
pbn_b0_bt_8_115200,
@@ -1167,6 +1169,10 @@ enum pci_board_num_t {
pbn_exsys_4055,
pbn_plx_romulus,
pbn_oxsemi,
+ pbn_oxsemi_1_4000000,
+ pbn_oxsemi_2_4000000,
+ pbn_oxsemi_4_4000000,
+ pbn_oxsemi_8_4000000,
pbn_intel_i960,
pbn_sgi_ioc3,
pbn_computone_4,
@@ -1290,6 +1296,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
.base_baud = 1843200,
.uart_offset = 0x200,
},
+ [pbn_b0_1_4000000] = {
+ .flags = FL_BASE0,
+ .num_ports = 1,
+ .base_baud = 4000000,
+ .uart_offset = 8,
+ },
[pbn_b0_bt_1_115200] = {
.flags = FL_BASE0|FL_BASE_BARS,
@@ -1625,6 +1637,35 @@ static struct pciserial_board pci_boards[] __devinitdata = {
.base_baud = 115200,
.uart_offset = 8,
},
+ [pbn_oxsemi_1_4000000] = {
+ .flags = FL_BASE0,
+ .num_ports = 1,
+ .base_baud = 4000000,
+ .uart_offset = 0x200,
+ .first_offset = 0x1000,
+ },
+ [pbn_oxsemi_2_4000000] = {
+ .flags = FL_BASE0,
+ .num_ports = 2,
+ .base_baud = 4000000,
+ .uart_offset = 0x200,
+ .first_offset = 0x1000,
+ },
+ [pbn_oxsemi_4_4000000] = {
+ .flags = FL_BASE0,
+ .num_ports = 4,
+ .base_baud = 4000000,
+ .uart_offset = 0x200,
+ .first_offset = 0x1000,
+ },
+ [pbn_oxsemi_8_4000000] = {
+ .flags = FL_BASE0,
+ .num_ports = 8,
+ .base_baud = 4000000,
+ .uart_offset = 0x200,
+ .first_offset = 0x1000,
+ },
+
/*
* EKF addition for i960 Boards form EKF with serial port.
@@ -1813,6 +1854,34 @@ serial_pci_matches(struct pciserial_board *board,
board->first_offset == guessed->first_offset;
}
+/*
+ * Oxford Semiconductor Inc.
+ * Check that device is part of the Tornado range of devices, then determine
+ * the number of ports available on the device.
+ */
+static int pci_oxsemi_tornado_init(struct pci_dev *dev, struct pciserial_board *board)
+{
+ u8 __iomem *p;
+ unsigned long deviceID;
+ unsigned int number_uarts;
+
+ p = pci_iomap(dev, 0, 5);
+ if (p == NULL)
+ return -ENOMEM;
+
+ deviceID = ioread32(p);
+ /* Tornado device */
+ if (deviceID == 0x07000200) {
+ number_uarts = ioread8(p + 4);
+ board->num_ports = number_uarts;
+ printk(KERN_DEBUG
+ "%d ports detected on Oxford PCI Express device\n",
+ number_uarts);
+ }
+ pci_iounmap(dev, p);
+ return 0;
+}
+
struct serial_private *
pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
{
@@ -1821,6 +1890,12 @@ pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
struct pci_serial_quirk *quirk;
int rc, nr_ports, i;
+ /*
+ * Find number of ports on board
+ */
+ if (dev->vendor == PCI_VENDOR_ID_OXSEMI)
+ pci_oxsemi_tornado_init(dev, board);
+
nr_ports = board->num_ports;
/*
@@ -2300,6 +2375,142 @@ static struct pci_device_id serial_pci_tbl[] = {
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_921600 },
+ /*
+ * Oxford Semiconductor Inc. Tornado PCI express device range.
+ */
+ { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_b0_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_b0_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_b0_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_b0_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_b0_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_b0_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_b0_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_b0_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_2_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_2_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_4_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_4_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_8_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_8_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_1_4000000 },
+
/*
* SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
* from [email protected]
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 8edddc2..df6e42b 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1944,6 +1944,14 @@
#define PCI_VENDOR_ID_OXSEMI 0x1415
#define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403
+#define PCI_DEVICE_ID_OXSEMI_PCIe840 0xC000
+#define PCI_DEVICE_ID_OXSEMI_PCIe840_G 0xC004
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_0 0xC100
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_0_G 0xC104
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1 0xC110
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_G 0xC114
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_U 0xC118
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU 0xC11C
#define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501
#define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511
#define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513
From: Lee Howard <[email protected]>
These have the Mainpine PCI identifier on however
Additional paranoia check for Tornado versions added by Alan Cox
Signed-off-by: Lee Howard <[email protected]>
Signed-off-by: Alan Cox <[email protected]>
---
drivers/serial/8250_pci.c | 30 +++++++++++++++++++++++++-----
1 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
index 43c990a..1198e50 100644
--- a/drivers/serial/8250_pci.c
+++ b/drivers/serial/8250_pci.c
@@ -1865,6 +1865,11 @@ static int pci_oxsemi_tornado_init(struct pci_dev *dev, struct pciserial_board *
unsigned long deviceID;
unsigned int number_uarts;
+ /* OxSemi Tornado devices are all 0xCxxx */
+ if (dev->vendor == PCI_VENDOR_OXSEMI &&
+ (dev->device & 0xF000) != 0xC000)
+ return 0;
+
p = pci_iomap(dev, 0, 5);
if (p == NULL)
return -ENOMEM;
@@ -1893,7 +1898,8 @@ pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
/*
* Find number of ports on board
*/
- if (dev->vendor == PCI_VENDOR_ID_OXSEMI)
+ if (dev->vendor == PCI_VENDOR_ID_OXSEMI ||
+ (dev->vendor == PCI_VENDOR_ID_MAINPINE)
pci_oxsemi_tornado_init(dev, board);
nr_ports = board->num_ports;
@@ -2375,9 +2381,9 @@ static struct pci_device_id serial_pci_tbl[] = {
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_bt_2_921600 },
- /*
- * Oxford Semiconductor Inc. Tornado PCI express device range.
- */
+ /*
+ * Oxford Semiconductor Inc. Tornado PCI express device range.
+ */
{ PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_4000000 },
@@ -2510,7 +2516,21 @@ static struct pci_device_id serial_pci_tbl[] = {
{ PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_oxsemi_1_4000000 },
-
+ /*
+ * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
+ */
+ { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax *.
+ PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
+ pbn_oxsemi_1_4000000 },
+ { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
+ PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
+ pbn_oxsemi_2_4000000 },
+ { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
+ PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
+ pbn_oxsemi_4_4000000 },
+ { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
+ PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
+ pbn_oxsemi_8_4000000 },
/*
* SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
* from [email protected]
This series was apparently never even compile-tested.
drivers/serial/8250_pci.c:2525:37: warning: "/*" within comment
drivers/serial/8250_pci.c: In function ‘pci_oxsemi_tornado_init’:
drivers/serial/8250_pci.c:1869: error: ‘PCI_VENDOR_OXSEMI’ undeclared (first use in this function)
drivers/serial/8250_pci.c:1869: error: (Each undeclared identifier is reported only once
drivers/serial/8250_pci.c:1869: error: for each function it appears in.)
...
Dropped as crap.
Linus
On 291, 10 17, 2008 at 08:28:44PM +0100, Alan Cox wrote:
> From: Lee Howard <[email protected]>
>
> Add support for the OxSemi 'Tornado' devices.
>
> Orginal from Lee Howard
> Reformatted and reworked a bit by Alan Cox
>
>
> Signed-off-by: Lee Howard <[email protected]>
> Signed-off-by: Alan Cox <[email protected]>
> ---
>
> drivers/parport/parport_pc.c | 20 ++++
> drivers/serial/8250_pci.c | 211 ++++++++++++++++++++++++++++++++++++++++++
> include/linux/pci_ids.h | 8 ++
> 3 files changed, 238 insertions(+), 1 deletions(-)
>
>
> diff --git a/drivers/parport/parport_pc.c b/drivers/parport/parport_pc.c
> index 8a846ad..96f3bdf 100644
> --- a/drivers/parport/parport_pc.c
> +++ b/drivers/parport/parport_pc.c
> @@ -2791,6 +2791,7 @@ enum parport_pc_pci_cards {
> oxsemi_952,
> oxsemi_954,
> oxsemi_840,
> + oxsemi_pcie_pport,
> aks_0100,
> mobility_pp,
> netmos_9705,
> @@ -2868,6 +2869,7 @@ static struct parport_pc_pci {
> /* oxsemi_952 */ { 1, { { 0, 1 }, } },
> /* oxsemi_954 */ { 1, { { 0, -1 }, } },
> /* oxsemi_840 */ { 1, { { 0, 1 }, } },
> + /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
> /* aks_0100 */ { 1, { { 0, -1 }, } },
> /* mobility_pp */ { 1, { { 0, 1 }, } },
> /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */
> @@ -2928,7 +2930,6 @@ static const struct pci_device_id parport_pc_pci_tbl[] = {
> { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
> { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
> { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
> - { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
> { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
> PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
> { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
> @@ -2946,8 +2947,25 @@ static const struct pci_device_id parport_pc_pci_tbl[] = {
> PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
> { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
> PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
> PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
> + { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
> /* NetMos communication controllers */
> { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
> PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
> diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
> index c014ffb..43c990a 100644
> --- a/drivers/serial/8250_pci.c
> +++ b/drivers/serial/8250_pci.c
> @@ -1100,6 +1100,8 @@ enum pci_board_num_t {
> pbn_b0_4_1843200_200,
> pbn_b0_8_1843200_200,
>
> + pbn_b0_1_4000000,
> +
> pbn_b0_bt_1_115200,
> pbn_b0_bt_2_115200,
> pbn_b0_bt_8_115200,
> @@ -1167,6 +1169,10 @@ enum pci_board_num_t {
> pbn_exsys_4055,
> pbn_plx_romulus,
> pbn_oxsemi,
> + pbn_oxsemi_1_4000000,
> + pbn_oxsemi_2_4000000,
> + pbn_oxsemi_4_4000000,
> + pbn_oxsemi_8_4000000,
> pbn_intel_i960,
> pbn_sgi_ioc3,
> pbn_computone_4,
> @@ -1290,6 +1296,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
> .base_baud = 1843200,
> .uart_offset = 0x200,
> },
> + [pbn_b0_1_4000000] = {
> + .flags = FL_BASE0,
> + .num_ports = 1,
> + .base_baud = 4000000,
> + .uart_offset = 8,
> + },
>
> [pbn_b0_bt_1_115200] = {
> .flags = FL_BASE0|FL_BASE_BARS,
> @@ -1625,6 +1637,35 @@ static struct pciserial_board pci_boards[] __devinitdata = {
> .base_baud = 115200,
> .uart_offset = 8,
> },
> + [pbn_oxsemi_1_4000000] = {
> + .flags = FL_BASE0,
> + .num_ports = 1,
> + .base_baud = 4000000,
> + .uart_offset = 0x200,
> + .first_offset = 0x1000,
> + },
> + [pbn_oxsemi_2_4000000] = {
> + .flags = FL_BASE0,
> + .num_ports = 2,
> + .base_baud = 4000000,
> + .uart_offset = 0x200,
> + .first_offset = 0x1000,
> + },
> + [pbn_oxsemi_4_4000000] = {
> + .flags = FL_BASE0,
> + .num_ports = 4,
> + .base_baud = 4000000,
> + .uart_offset = 0x200,
> + .first_offset = 0x1000,
> + },
> + [pbn_oxsemi_8_4000000] = {
> + .flags = FL_BASE0,
> + .num_ports = 8,
> + .base_baud = 4000000,
> + .uart_offset = 0x200,
> + .first_offset = 0x1000,
> + },
> +
>
> /*
> * EKF addition for i960 Boards form EKF with serial port.
> @@ -1813,6 +1854,34 @@ serial_pci_matches(struct pciserial_board *board,
> board->first_offset == guessed->first_offset;
> }
>
> +/*
> + * Oxford Semiconductor Inc.
> + * Check that device is part of the Tornado range of devices, then determine
> + * the number of ports available on the device.
> + */
> +static int pci_oxsemi_tornado_init(struct pci_dev *dev, struct pciserial_board *board)
> +{
> + u8 __iomem *p;
> + unsigned long deviceID;
> + unsigned int number_uarts;
> +
> + p = pci_iomap(dev, 0, 5);
> + if (p == NULL)
> + return -ENOMEM;
> +
> + deviceID = ioread32(p);
> + /* Tornado device */
> + if (deviceID == 0x07000200) {
> + number_uarts = ioread8(p + 4);
> + board->num_ports = number_uarts;
> + printk(KERN_DEBUG
> + "%d ports detected on Oxford PCI Express device\n",
> + number_uarts);
> + }
> + pci_iounmap(dev, p);
> + return 0;
> +}
> +
> struct serial_private *
> pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
> {
> @@ -1821,6 +1890,12 @@ pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
> struct pci_serial_quirk *quirk;
> int rc, nr_ports, i;
>
> + /*
> + * Find number of ports on board
> + */
> + if (dev->vendor == PCI_VENDOR_ID_OXSEMI)
> + pci_oxsemi_tornado_init(dev, board);
> +
WTF is this ? Why existing pci_serial_quirks[] infrastructure isn't used here ?
> nr_ports = board->num_ports;
>
> /*
> @@ -2300,6 +2375,142 @@ static struct pci_device_id serial_pci_tbl[] = {
> PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> pbn_b0_bt_2_921600 },
>
> + /*
> + * Oxford Semiconductor Inc. Tornado PCI express device range.
> + */
> + { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_2_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_2_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_4_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_4_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_8_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_8_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> +
> /*
> * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
> * from [email protected]
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 8edddc2..df6e42b 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -1944,6 +1944,14 @@
>
> #define PCI_VENDOR_ID_OXSEMI 0x1415
> #define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403
> +#define PCI_DEVICE_ID_OXSEMI_PCIe840 0xC000
> +#define PCI_DEVICE_ID_OXSEMI_PCIe840_G 0xC004
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_0 0xC100
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_0_G 0xC104
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1 0xC110
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_G 0xC114
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_U 0xC118
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU 0xC11C
> #define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501
> #define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511
> #define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
>
On 291, 10 17, 2008 at 08:28:44PM +0100, Alan Cox wrote:
> From: Lee Howard <[email protected]>
>
> Add support for the OxSemi 'Tornado' devices.
>
> Orginal from Lee Howard
> Reformatted and reworked a bit by Alan Cox
>
>
> Signed-off-by: Lee Howard <[email protected]>
> Signed-off-by: Alan Cox <[email protected]>
> ---
>
> drivers/parport/parport_pc.c | 20 ++++
> drivers/serial/8250_pci.c | 211 ++++++++++++++++++++++++++++++++++++++++++
> include/linux/pci_ids.h | 8 ++
> 3 files changed, 238 insertions(+), 1 deletions(-)
>
>
> diff --git a/drivers/parport/parport_pc.c b/drivers/parport/parport_pc.c
> index 8a846ad..96f3bdf 100644
> --- a/drivers/parport/parport_pc.c
> +++ b/drivers/parport/parport_pc.c
> @@ -2791,6 +2791,7 @@ enum parport_pc_pci_cards {
> oxsemi_952,
> oxsemi_954,
> oxsemi_840,
> + oxsemi_pcie_pport,
> aks_0100,
> mobility_pp,
> netmos_9705,
> @@ -2868,6 +2869,7 @@ static struct parport_pc_pci {
> /* oxsemi_952 */ { 1, { { 0, 1 }, } },
> /* oxsemi_954 */ { 1, { { 0, -1 }, } },
> /* oxsemi_840 */ { 1, { { 0, 1 }, } },
> + /* oxsemi_pcie_pport */ { 1, { { 0, 1 }, } },
> /* aks_0100 */ { 1, { { 0, -1 }, } },
> /* mobility_pp */ { 1, { { 0, 1 }, } },
> /* netmos_9705 */ { 1, { { 0, -1 }, } }, /* untested */
> @@ -2928,7 +2930,6 @@ static const struct pci_device_id parport_pc_pci_tbl[] = {
> { 0x1409, 0x7268, 0x1409, 0x0103, 0, 0, timedia_4008a },
> { 0x1409, 0x7268, 0x1409, 0x0104, 0, 0, timedia_4018 },
> { 0x1409, 0x7268, 0x1409, 0x9018, 0, 0, timedia_9018a },
> - { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
> { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_2P_EPP,
> PCI_ANY_ID, PCI_ANY_ID, 0, 0, syba_2p_epp },
> { PCI_VENDOR_ID_SYBA, PCI_DEVICE_ID_SYBA_1P_ECP,
> @@ -2946,8 +2947,25 @@ static const struct pci_device_id parport_pc_pci_tbl[] = {
> PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_954 },
> { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_12PCI840,
> PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_840 },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe840_G,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_0_G,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_G,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_U,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> + { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU,
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0, oxsemi_pcie_pport },
> { PCI_VENDOR_ID_AKS, PCI_DEVICE_ID_AKS_ALADDINCARD,
> PCI_ANY_ID, PCI_ANY_ID, 0, 0, aks_0100 },
> + { 0x14f2, 0x0121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, mobility_pp },
> /* NetMos communication controllers */
> { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9705,
> PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9705 },
> diff --git a/drivers/serial/8250_pci.c b/drivers/serial/8250_pci.c
> index c014ffb..43c990a 100644
> --- a/drivers/serial/8250_pci.c
> +++ b/drivers/serial/8250_pci.c
> @@ -1100,6 +1100,8 @@ enum pci_board_num_t {
> pbn_b0_4_1843200_200,
> pbn_b0_8_1843200_200,
>
> + pbn_b0_1_4000000,
> +
> pbn_b0_bt_1_115200,
> pbn_b0_bt_2_115200,
> pbn_b0_bt_8_115200,
> @@ -1167,6 +1169,10 @@ enum pci_board_num_t {
> pbn_exsys_4055,
> pbn_plx_romulus,
> pbn_oxsemi,
> + pbn_oxsemi_1_4000000,
> + pbn_oxsemi_2_4000000,
> + pbn_oxsemi_4_4000000,
> + pbn_oxsemi_8_4000000,
> pbn_intel_i960,
> pbn_sgi_ioc3,
> pbn_computone_4,
> @@ -1290,6 +1296,12 @@ static struct pciserial_board pci_boards[] __devinitdata = {
> .base_baud = 1843200,
> .uart_offset = 0x200,
> },
> + [pbn_b0_1_4000000] = {
> + .flags = FL_BASE0,
> + .num_ports = 1,
> + .base_baud = 4000000,
> + .uart_offset = 8,
> + },
>
> [pbn_b0_bt_1_115200] = {
> .flags = FL_BASE0|FL_BASE_BARS,
> @@ -1625,6 +1637,35 @@ static struct pciserial_board pci_boards[] __devinitdata = {
> .base_baud = 115200,
> .uart_offset = 8,
> },
> + [pbn_oxsemi_1_4000000] = {
> + .flags = FL_BASE0,
> + .num_ports = 1,
> + .base_baud = 4000000,
> + .uart_offset = 0x200,
> + .first_offset = 0x1000,
> + },
> + [pbn_oxsemi_2_4000000] = {
> + .flags = FL_BASE0,
> + .num_ports = 2,
> + .base_baud = 4000000,
> + .uart_offset = 0x200,
> + .first_offset = 0x1000,
> + },
> + [pbn_oxsemi_4_4000000] = {
> + .flags = FL_BASE0,
> + .num_ports = 4,
> + .base_baud = 4000000,
> + .uart_offset = 0x200,
> + .first_offset = 0x1000,
> + },
> + [pbn_oxsemi_8_4000000] = {
> + .flags = FL_BASE0,
> + .num_ports = 8,
> + .base_baud = 4000000,
> + .uart_offset = 0x200,
> + .first_offset = 0x1000,
> + },
> +
>
> /*
> * EKF addition for i960 Boards form EKF with serial port.
> @@ -1813,6 +1854,34 @@ serial_pci_matches(struct pciserial_board *board,
> board->first_offset == guessed->first_offset;
> }
>
> +/*
> + * Oxford Semiconductor Inc.
> + * Check that device is part of the Tornado range of devices, then determine
> + * the number of ports available on the device.
> + */
> +static int pci_oxsemi_tornado_init(struct pci_dev *dev, struct pciserial_board *board)
> +{
> + u8 __iomem *p;
> + unsigned long deviceID;
> + unsigned int number_uarts;
> +
> + p = pci_iomap(dev, 0, 5);
> + if (p == NULL)
> + return -ENOMEM;
> +
> + deviceID = ioread32(p);
> + /* Tornado device */
> + if (deviceID == 0x07000200) {
> + number_uarts = ioread8(p + 4);
> + board->num_ports = number_uarts;
Why not just return number of ports here ?
> + printk(KERN_DEBUG
> + "%d ports detected on Oxford PCI Express device\n",
> + number_uarts);
Is this printk really necessary ?
> + }
> + pci_iounmap(dev, p);
> + return 0;
> +}
> +
> struct serial_private *
> pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
> {
> @@ -1821,6 +1890,12 @@ pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
> struct pci_serial_quirk *quirk;
> int rc, nr_ports, i;
>
> + /*
> + * Find number of ports on board
> + */
> + if (dev->vendor == PCI_VENDOR_ID_OXSEMI)
> + pci_oxsemi_tornado_init(dev, board);
> +
WTF is this ? Why existing pci_serial_quirks[] infrastructure cannot be used here ?
> nr_ports = board->num_ports;
>
> /*
> @@ -2300,6 +2375,142 @@ static struct pci_device_id serial_pci_tbl[] = {
> PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> pbn_b0_bt_2_921600 },
>
> + /*
> + * Oxford Semiconductor Inc. Tornado PCI express device range.
> + */
> + { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_b0_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_2_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_2_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_4_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_4_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_8_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_8_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> + { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
> + PCI_ANY_ID, PCI_ANY_ID, 0, 0,
> + pbn_oxsemi_1_4000000 },
> +
> /*
> * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
> * from [email protected]
> diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
> index 8edddc2..df6e42b 100644
> --- a/include/linux/pci_ids.h
> +++ b/include/linux/pci_ids.h
> @@ -1944,6 +1944,14 @@
>
> #define PCI_VENDOR_ID_OXSEMI 0x1415
> #define PCI_DEVICE_ID_OXSEMI_12PCI840 0x8403
> +#define PCI_DEVICE_ID_OXSEMI_PCIe840 0xC000
> +#define PCI_DEVICE_ID_OXSEMI_PCIe840_G 0xC004
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_0 0xC100
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_0_G 0xC104
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1 0xC110
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_G 0xC114
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_U 0xC118
> +#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU 0xC11C
> #define PCI_DEVICE_ID_OXSEMI_16PCI954 0x9501
> #define PCI_DEVICE_ID_OXSEMI_16PCI95N 0x9511
> #define PCI_DEVICE_ID_OXSEMI_16PCI954PP 0x9513
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
>
> > + number_uarts = ioread8(p + 4);
> > + board->num_ports = number_uarts;
>
> Why not just return number of ports here ?
That would leak mappings
>
> > + printk(KERN_DEBUG
> > + "%d ports detected on Oxford PCI Express device\n",
> > + number_uarts);
>
> Is this printk really necessary ?
For the moment yes.
> WTF is this ? Why existing pci_serial_quirks[] infrastructure cannot be used here ?
Russell already fixed that and the change went upstream.
Andrey,
PLEASE don't quote 200 lines and then add a single line in the middle.
It's hard to even find what you wanted to say, and once anybody finds it,
they're certainly no longer interested.
Linus