2009-01-28 20:45:51

by Paul Walmsley

Subject: [PATCH B 00/10] OMAP clock, B of F: clockdomain, powerdomain updates

This series is the second of six to bring the mainline kernel OMAP
clock code up-to-date with the linux-omap tree.

Major changes in this series:

- Fix clockdomain, powerdomain code and data to match the hardware
- Add PRCM clockdomains
- Add DPLL clockdomains, powerdomains
- Mark all OMAP clocks with clockdomains
- Combine pwrdm, clkdm names and pointers into unions

Some patches have been "compressed" together, as requested by rmk -
original commit IDs are in the patch descriptions.

Compile-tested on OSK5912 (OMAP1), H4 and 2430SDP (OMAP2), and
BeagleBoard (OMAP3). Boot-tested on 2430SDP and BeagleBoard.

Applies on top of series A, posted earlier.


- Paul

---

Jouni Hogander (1):
OMAP3: PM: Emu_pwrdm is switched off by hardware even when sdti is in use

Paul Walmsley (8):
OMAP2/3 clockdomains: autodeps should respect platform flags
OMAP3 powerdomains: remove RET from SGX power states list
OMAP3 pwrdm: add CORE SAR handling (for USBTLL module)
OMAP2/3 clock: add clockdomains to all remaining clocks; fix clkdm init
OMAP3 PRCM: add DPLL1-5 powerdomains, clockdomains; mark clocks
OMAP2/3 clockdomains: add CM, PRM, virt_opp_clkdm clockdomains
OMAP2/3 clockdomains: combine pwrdm, pwrdm_name into union in struct clockdomain
OMAP2/3 clock: combine clkdm, clkdm_name into union in struct clk

Tomi Valkeinen (1):
OMAP: wait for pwrdm transition after clk_enable()


arch/arm/mach-omap2/clock.c | 26 +-
arch/arm/mach-omap2/clock24xx.c | 2
arch/arm/mach-omap2/clock24xx.h | 278 ++++++++++---------
arch/arm/mach-omap2/clock34xx.h | 369 +++++++++++++++----------
arch/arm/mach-omap2/clockdomain.c | 58 ++--
arch/arm/mach-omap2/clockdomains.h | 125 ++++++--
arch/arm/mach-omap2/powerdomains.h | 8 -
arch/arm/mach-omap2/powerdomains34xx.h | 61 ++++
arch/arm/plat-omap/include/mach/clock.h | 6
arch/arm/plat-omap/include/mach/clockdomain.h | 24 +-
arch/arm/plat-omap/include/mach/powerdomain.h | 4
11 files changed, 586 insertions(+), 375 deletions(-)

text data bss dec hex filename
3241423 164192 100912 3506527 35815f vmlinux.beagle.orig
3241711 163872 100912 3506495 35813f vmlinux.beagle

2009-01-28 20:43:34

by Paul Walmsley

Subject: [PATCH B 01/10] OMAP2/3 clock: combine clkdm, clkdm_name into union in struct clk

struct clk contains a struct clockdomain *clkdm and const char
*clkdm_name. The clkdm_name is only used at initialization to look up
the appropriate clkdm pointer. Combining these into a union saves
about 850 bytes on 3430SDP. This patch should not cause any change in
kernel function.

Boot-tested on 3430SDP ES2; compile-tested with n800_defconfig.

linux-omap source commit is 0e5194e1a84c219bebbb78f305b7a8eabc4a3656.

Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
---
arch/arm/mach-omap2/clock.c | 22 +--
arch/arm/mach-omap2/clock24xx.h | 264 ++++++++++++++++---------------
arch/arm/mach-omap2/clock34xx.h | 256 +++++++++++++++---------------
arch/arm/plat-omap/include/mach/clock.h | 6 -
4 files changed, 275 insertions(+), 273 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 55c5d67..7aa09f5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -77,17 +77,17 @@ void omap2_init_clk_clkdm(struct clk *clk)
{
struct clockdomain *clkdm;

- if (!clk->clkdm_name)
+ if (!clk->clkdm.name)
return;

- clkdm = clkdm_lookup(clk->clkdm_name);
+ clkdm = clkdm_lookup(clk->clkdm.name);
if (clkdm) {
pr_debug("clock: associated clk %s to clkdm %s\n",
- clk->name, clk->clkdm_name);
- clk->clkdm = clkdm;
+ clk->name, clk->clkdm.name);
+ clk->clkdm.ptr = clkdm;
} else {
pr_debug("clock: could not associate clk %s to "
- "clkdm %s\n", clk->name, clk->clkdm_name);
+ "clkdm %s\n", clk->name, clk->clkdm.name);
}
}

@@ -333,8 +333,8 @@ void omap2_clk_disable(struct clk *clk)
_omap2_clk_disable(clk);
if (clk->parent)
omap2_clk_disable(clk->parent);
- if (clk->clkdm)
- omap2_clkdm_clk_disable(clk->clkdm, clk);
+ if (clk->clkdm.ptr)
+ omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);

}
}
@@ -352,14 +352,14 @@ int omap2_clk_enable(struct clk *clk)
return ret;
}

- if (clk->clkdm)
- omap2_clkdm_clk_enable(clk->clkdm, clk);
+ if (clk->clkdm.ptr)
+ omap2_clkdm_clk_enable(clk->clkdm.ptr, clk);

ret = _omap2_clk_enable(clk);

if (ret != 0) {
- if (clk->clkdm)
- omap2_clkdm_clk_disable(clk->clkdm, clk);
+ if (clk->clkdm.ptr)
+ omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);

if (clk->parent) {
omap2_clk_disable(clk->parent);
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 2bf16ee..68e3667 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -633,7 +633,7 @@ static struct clk func_32k_ck = {
.rate = 32000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &propagate_rate,
};

@@ -642,7 +642,7 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
.name = "osc_ck",
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.enable = &omap2_enable_osc_ck,
.disable = &omap2_disable_osc_ck,
.recalc = &omap2_osc_clk_recalc,
@@ -654,7 +654,7 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &omap2_sys_clk_recalc,
};

@@ -663,7 +663,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &propagate_rate,
};

@@ -695,7 +695,7 @@ static struct clk dpll_ck = {
.dpll_data = &dpll_dd,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &omap2_dpllcore_recalc,
.set_rate = &omap2_reprogram_dpllcore,
};
@@ -706,7 +706,7 @@ static struct clk apll96_ck = {
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
.enable = &omap2_clk_fixed_enable,
@@ -720,7 +720,7 @@ static struct clk apll54_ck = {
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
.enable = &omap2_clk_fixed_enable,
@@ -755,7 +755,7 @@ static struct clk func_54m_ck = {
.parent = &apll54_ck, /* can also be alt_clk */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_54M_SOURCE,
@@ -768,7 +768,7 @@ static struct clk core_ck = {
.parent = &dpll_ck, /* can also be 32k */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -795,7 +795,7 @@ static struct clk func_96m_ck = {
.parent = &apll96_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP2430_96M_SOURCE,
@@ -828,7 +828,7 @@ static struct clk func_48m_ck = {
.parent = &apll96_ck, /* 96M or Alt */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_48M_SOURCE,
@@ -844,7 +844,7 @@ static struct clk func_12m_ck = {
.fixed_div = 4,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &omap2_fixed_divisor_recalc,
};

@@ -897,7 +897,7 @@ static struct clk sys_clkout_src = {
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | OFFSET_GR_MOD,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -928,7 +928,7 @@ static struct clk sys_clkout = {
.parent = &sys_clkout_src,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
.clksel = sys_clkout_clksel,
@@ -942,7 +942,7 @@ static struct clk sys_clkout2_src = {
.name = "sys_clkout2_src",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -965,7 +965,7 @@ static struct clk sys_clkout2 = {
.parent = &sys_clkout2_src,
.flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
OFFSET_GR_MOD,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
.clksel = sys_clkout2_clksel,
@@ -978,7 +978,7 @@ static struct clk emul_ck = {
.name = "emul_ck",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
.enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
.recalc = &followparent_recalc,
@@ -1015,7 +1015,7 @@ static struct clk mpu_ck = { /* Control cpu */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
- .clkdm_name = "mpu_clkdm",
+ .clkdm = { .name = "mpu_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = _CM_REG_OFFSET(MPU_MOD, CM_CLKSEL),
.clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
@@ -1057,7 +1057,7 @@ static struct clk dsp_fck = {
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
- .clkdm_name = "dsp_clkdm",
+ .clkdm = { .name = "dsp_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
.clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
@@ -1123,7 +1123,7 @@ static struct clk iva1_ifck = {
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT |
RATE_PROPAGATES | DELAYED_APP,
- .clkdm_name = "iva1_clkdm",
+ .clkdm = { .name = "iva1_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP2420_EN_IVA_COP_SHIFT,
.clksel_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_CLKSEL),
@@ -1139,7 +1139,7 @@ static struct clk iva1_mpu_int_ifck = {
.name = "iva1_mpu_int_ifck",
.parent = &iva1_ifck,
.flags = CLOCK_IN_OMAP242X,
- .clkdm_name = "iva1_clkdm",
+ .clkdm = { .name = "iva1_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP24XX_DSP_MOD, CM_FCLKEN),
.enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
.fixed_div = 2,
@@ -1187,7 +1187,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
.clksel = core_l3_clksel,
@@ -1215,7 +1215,7 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP | CONFIG_PARTICIPANT,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP24XX_EN_USB_SHIFT,
.clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
@@ -1249,7 +1249,7 @@ static struct clk l4_ck = { /* used both as an ick and fck */
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
.clksel = l4_clksel,
@@ -1287,7 +1287,7 @@ static struct clk ssi_ssr_sst_fck = {
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP24XX_EN_SSI_SHIFT,
.clksel_reg = _CM_REG_OFFSET(CORE_MOD, CM_CLKSEL1),
@@ -1305,7 +1305,7 @@ static struct clk ssi_ssr_sst_fck = {
static struct clk ssi_l4_ick = {
.name = "ssi_l4_ick",
.parent = &l4_ck,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP24XX_EN_SSI_SHIFT,
@@ -1336,7 +1336,7 @@ static struct clk gfx_3d_fck = {
.name = "gfx_3d_fck",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "gfx_clkdm",
+ .clkdm = { .name = "gfx_clkdm" },
.enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_3D_SHIFT,
.clksel_reg = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
@@ -1351,7 +1351,7 @@ static struct clk gfx_2d_fck = {
.name = "gfx_2d_fck",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "gfx_clkdm",
+ .clkdm = { .name = "gfx_clkdm" },
.enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_2D_SHIFT,
.clksel_reg = _CM_REG_OFFSET(GFX_MOD, CM_CLKSEL),
@@ -1366,7 +1366,7 @@ static struct clk gfx_ick = {
.name = "gfx_ick", /* From l3 */
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "gfx_clkdm",
+ .clkdm = { .name = "gfx_clkdm" },
.enable_reg = _CM_REG_OFFSET(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
.recalc = &followparent_recalc,
@@ -1396,7 +1396,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
.name = "mdm_ick",
.parent = &core_ck,
.flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT,
- .clkdm_name = "mdm_clkdm",
+ .clkdm = { .name = "mdm_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_ICLKEN),
.enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
.clksel_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_CLKSEL),
@@ -1411,7 +1411,7 @@ static struct clk mdm_osc_ck = {
.name = "mdm_osc_ck",
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "mdm_clkdm",
+ .clkdm = { .name = "mdm_clkdm" },
.enable_reg = _CM_REG_OFFSET(OMAP2430_MDM_MOD, CM_FCLKEN),
.enable_bit = OMAP2430_EN_OSC_SHIFT,
.recalc = &followparent_recalc,
@@ -1456,7 +1456,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
.name = "dss_ick",
.parent = &l4_ck, /* really both l3 and l4 */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_DSS1_SHIFT,
.recalc = &followparent_recalc,
@@ -1467,7 +1467,7 @@ static struct clk dss1_fck = {
.parent = &core_ck, /* Core or sys */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_DSS1_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1500,7 +1500,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
.parent = &sys_ck, /* fixed at sys_ck or 48MHz */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
DELAYED_APP,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_DSS2_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1514,7 +1514,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */
.name = "dss_54m_fck", /* 54m tv clk */
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_TV_SHIFT,
.recalc = &followparent_recalc,
@@ -1542,7 +1542,7 @@ static struct clk gpt1_ick = {
.name = "gpt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.recalc = &followparent_recalc,
@@ -1552,7 +1552,7 @@ static struct clk gpt1_fck = {
.name = "gpt1_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_GPT1_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1568,7 +1568,7 @@ static struct clk gpt2_ick = {
.name = "gpt2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT2_SHIFT,
.recalc = &followparent_recalc,
@@ -1578,7 +1578,7 @@ static struct clk gpt2_fck = {
.name = "gpt2_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT2_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1592,7 +1592,7 @@ static struct clk gpt3_ick = {
.name = "gpt3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT3_SHIFT,
.recalc = &followparent_recalc,
@@ -1602,7 +1602,7 @@ static struct clk gpt3_fck = {
.name = "gpt3_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT3_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1616,7 +1616,7 @@ static struct clk gpt4_ick = {
.name = "gpt4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT4_SHIFT,
.recalc = &followparent_recalc,
@@ -1626,7 +1626,7 @@ static struct clk gpt4_fck = {
.name = "gpt4_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT4_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1640,7 +1640,7 @@ static struct clk gpt5_ick = {
.name = "gpt5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT5_SHIFT,
.recalc = &followparent_recalc,
@@ -1650,7 +1650,7 @@ static struct clk gpt5_fck = {
.name = "gpt5_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT5_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1664,7 +1664,7 @@ static struct clk gpt6_ick = {
.name = "gpt6_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT6_SHIFT,
.recalc = &followparent_recalc,
@@ -1674,7 +1674,7 @@ static struct clk gpt6_fck = {
.name = "gpt6_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT6_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1697,7 +1697,7 @@ static struct clk gpt7_fck = {
.name = "gpt7_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT7_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1711,7 +1711,7 @@ static struct clk gpt8_ick = {
.name = "gpt8_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT8_SHIFT,
.recalc = &followparent_recalc,
@@ -1721,7 +1721,7 @@ static struct clk gpt8_fck = {
.name = "gpt8_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT8_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1735,7 +1735,7 @@ static struct clk gpt9_ick = {
.name = "gpt9_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT9_SHIFT,
.recalc = &followparent_recalc,
@@ -1745,7 +1745,7 @@ static struct clk gpt9_fck = {
.name = "gpt9_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT9_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1759,7 +1759,7 @@ static struct clk gpt10_ick = {
.name = "gpt10_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT10_SHIFT,
.recalc = &followparent_recalc,
@@ -1769,7 +1769,7 @@ static struct clk gpt10_fck = {
.name = "gpt10_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT10_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1783,7 +1783,7 @@ static struct clk gpt11_ick = {
.name = "gpt11_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT11_SHIFT,
.recalc = &followparent_recalc,
@@ -1793,7 +1793,7 @@ static struct clk gpt11_fck = {
.name = "gpt11_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT11_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1807,7 +1807,7 @@ static struct clk gpt12_ick = {
.name = "gpt12_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_GPT12_SHIFT,
.recalc = &followparent_recalc,
@@ -1817,7 +1817,7 @@ static struct clk gpt12_fck = {
.name = "gpt12_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_GPT12_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -1832,7 +1832,7 @@ static struct clk mcbsp1_ick = {
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.recalc = &followparent_recalc,
@@ -1843,7 +1843,7 @@ static struct clk mcbsp1_fck = {
.id = 1,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.recalc = &followparent_recalc,
@@ -1854,7 +1854,7 @@ static struct clk mcbsp2_ick = {
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.recalc = &followparent_recalc,
@@ -1865,7 +1865,7 @@ static struct clk mcbsp2_fck = {
.id = 2,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.recalc = &followparent_recalc,
@@ -1876,7 +1876,7 @@ static struct clk mcbsp3_ick = {
.id = 3,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
.recalc = &followparent_recalc,
@@ -1887,7 +1887,7 @@ static struct clk mcbsp3_fck = {
.id = 3,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
.recalc = &followparent_recalc,
@@ -1898,7 +1898,7 @@ static struct clk mcbsp4_ick = {
.id = 4,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
.recalc = &followparent_recalc,
@@ -1909,7 +1909,7 @@ static struct clk mcbsp4_fck = {
.id = 4,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
.recalc = &followparent_recalc,
@@ -1920,7 +1920,7 @@ static struct clk mcbsp5_ick = {
.id = 5,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
.recalc = &followparent_recalc,
@@ -1931,7 +1931,7 @@ static struct clk mcbsp5_fck = {
.id = 5,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
.recalc = &followparent_recalc,
@@ -1941,7 +1941,7 @@ static struct clk mcspi1_ick = {
.name = "mcspi_ick",
.id = 1,
.parent = &l4_ck,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
@@ -1953,7 +1953,7 @@ static struct clk mcspi1_fck = {
.id = 1,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
.recalc = &followparent_recalc,
@@ -1964,7 +1964,7 @@ static struct clk mcspi2_ick = {
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.recalc = &followparent_recalc,
@@ -1975,7 +1975,7 @@ static struct clk mcspi2_fck = {
.id = 2,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.recalc = &followparent_recalc,
@@ -1986,7 +1986,7 @@ static struct clk mcspi3_ick = {
.id = 3,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
.recalc = &followparent_recalc,
@@ -1997,7 +1997,7 @@ static struct clk mcspi3_fck = {
.id = 3,
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
.recalc = &followparent_recalc,
@@ -2007,7 +2007,7 @@ static struct clk uart1_ick = {
.name = "uart1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_UART1_SHIFT,
.recalc = &followparent_recalc,
@@ -2017,7 +2017,7 @@ static struct clk uart1_fck = {
.name = "uart1_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_UART1_SHIFT,
.recalc = &followparent_recalc,
@@ -2027,7 +2027,7 @@ static struct clk uart2_ick = {
.name = "uart2_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_UART2_SHIFT,
.recalc = &followparent_recalc,
@@ -2037,7 +2037,7 @@ static struct clk uart2_fck = {
.name = "uart2_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_UART2_SHIFT,
.recalc = &followparent_recalc,
@@ -2047,7 +2047,7 @@ static struct clk uart3_ick = {
.name = "uart3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP24XX_EN_UART3_SHIFT,
.recalc = &followparent_recalc,
@@ -2057,7 +2057,7 @@ static struct clk uart3_fck = {
.name = "uart3_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP24XX_EN_UART3_SHIFT,
.recalc = &followparent_recalc,
@@ -2067,7 +2067,7 @@ static struct clk gpios_ick = {
.name = "gpios_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &followparent_recalc,
@@ -2077,7 +2077,7 @@ static struct clk gpios_fck = {
.name = "gpios_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &followparent_recalc,
@@ -2087,7 +2087,7 @@ static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
@@ -2097,7 +2097,7 @@ static struct clk mpu_wdt_fck = {
.name = "mpu_wdt_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
@@ -2108,7 +2108,7 @@ static struct clk sync_32k_ick = {
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
.recalc = &followparent_recalc,
@@ -2118,7 +2118,7 @@ static struct clk wdt1_ick = {
.name = "wdt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_WDT1_SHIFT,
.recalc = &followparent_recalc,
@@ -2129,7 +2129,7 @@ static struct clk omapctrl_ick = {
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
.recalc = &followparent_recalc,
@@ -2139,7 +2139,7 @@ static struct clk icr_ick = {
.name = "icr_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP2430_EN_ICR_SHIFT,
.recalc = &followparent_recalc,
@@ -2149,7 +2149,7 @@ static struct clk cam_ick = {
.name = "cam_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_CAM_SHIFT,
.recalc = &followparent_recalc,
@@ -2164,7 +2164,7 @@ static struct clk cam_fck = {
.name = "cam_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_CAM_SHIFT,
.recalc = &followparent_recalc,
@@ -2174,7 +2174,7 @@ static struct clk mailboxes_ick = {
.name = "mailboxes_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
.recalc = &followparent_recalc,
@@ -2184,7 +2184,7 @@ static struct clk wdt4_ick = {
.name = "wdt4_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_WDT4_SHIFT,
.recalc = &followparent_recalc,
@@ -2194,7 +2194,7 @@ static struct clk wdt4_fck = {
.name = "wdt4_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_WDT4_SHIFT,
.recalc = &followparent_recalc,
@@ -2204,7 +2204,7 @@ static struct clk wdt3_ick = {
.name = "wdt3_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_WDT3_SHIFT,
.recalc = &followparent_recalc,
@@ -2214,7 +2214,7 @@ static struct clk wdt3_fck = {
.name = "wdt3_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_WDT3_SHIFT,
.recalc = &followparent_recalc,
@@ -2224,7 +2224,7 @@ static struct clk mspro_ick = {
.name = "mspro_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
.recalc = &followparent_recalc,
@@ -2234,7 +2234,7 @@ static struct clk mspro_fck = {
.name = "mspro_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
.recalc = &followparent_recalc,
@@ -2244,7 +2244,7 @@ static struct clk mmc_ick = {
.name = "mmc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_MMC_SHIFT,
.recalc = &followparent_recalc,
@@ -2254,7 +2254,7 @@ static struct clk mmc_fck = {
.name = "mmc_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_MMC_SHIFT,
.recalc = &followparent_recalc,
@@ -2264,7 +2264,7 @@ static struct clk fac_ick = {
.name = "fac_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_FAC_SHIFT,
.recalc = &followparent_recalc,
@@ -2274,7 +2274,7 @@ static struct clk fac_fck = {
.name = "fac_fck",
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_FAC_SHIFT,
.recalc = &followparent_recalc,
@@ -2284,7 +2284,7 @@ static struct clk eac_ick = {
.name = "eac_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_EAC_SHIFT,
.recalc = &followparent_recalc,
@@ -2294,7 +2294,7 @@ static struct clk eac_fck = {
.name = "eac_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_EAC_SHIFT,
.recalc = &followparent_recalc,
@@ -2304,7 +2304,7 @@ static struct clk hdq_ick = {
.name = "hdq_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP24XX_EN_HDQ_SHIFT,
.recalc = &followparent_recalc,
@@ -2314,7 +2314,7 @@ static struct clk hdq_fck = {
.name = "hdq_fck",
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP24XX_EN_HDQ_SHIFT,
.recalc = &followparent_recalc,
@@ -2325,7 +2325,7 @@ static struct clk i2c2_ick = {
.id = 2,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_I2C2_SHIFT,
.recalc = &followparent_recalc,
@@ -2336,7 +2336,7 @@ static struct clk i2c2_fck = {
.id = 2,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_I2C2_SHIFT,
.recalc = &followparent_recalc,
@@ -2347,7 +2347,7 @@ static struct clk i2chs2_fck = {
.id = 2,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
.recalc = &followparent_recalc,
@@ -2358,7 +2358,7 @@ static struct clk i2c1_ick = {
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_I2C1_SHIFT,
.recalc = &followparent_recalc,
@@ -2369,7 +2369,7 @@ static struct clk i2c1_fck = {
.id = 1,
.parent = &func_12m_ck,
.flags = CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_I2C1_SHIFT,
.recalc = &followparent_recalc,
@@ -2380,7 +2380,7 @@ static struct clk i2chs1_fck = {
.id = 1,
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
.recalc = &followparent_recalc,
@@ -2391,7 +2391,7 @@ static struct clk gpmc_fck = {
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2399,7 +2399,7 @@ static struct clk sdma_fck = {
.name = "sdma_fck",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2407,7 +2407,7 @@ static struct clk sdma_ick = {
.name = "sdma_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2415,7 +2415,7 @@ static struct clk vlynq_ick = {
.name = "vlynq_ick",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
.recalc = &followparent_recalc,
@@ -2450,7 +2450,7 @@ static struct clk vlynq_fck = {
.name = "vlynq_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP242X | DELAYED_APP,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -2466,7 +2466,7 @@ static struct clk sdrc_ick = {
.name = "sdrc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP2430_EN_SDRC_SHIFT,
.recalc = &followparent_recalc,
@@ -2476,7 +2476,7 @@ static struct clk des_ick = {
.name = "des_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = OMAP24XX_EN_DES_SHIFT,
.recalc = &followparent_recalc,
@@ -2486,7 +2486,7 @@ static struct clk sha_ick = {
.name = "sha_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = OMAP24XX_EN_SHA_SHIFT,
.recalc = &followparent_recalc,
@@ -2496,7 +2496,7 @@ static struct clk rng_ick = {
.name = "rng_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = OMAP24XX_EN_RNG_SHIFT,
.recalc = &followparent_recalc,
@@ -2506,7 +2506,7 @@ static struct clk aes_ick = {
.name = "aes_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = OMAP24XX_EN_AES_SHIFT,
.recalc = &followparent_recalc,
@@ -2516,7 +2516,7 @@ static struct clk pka_ick = {
.name = "pka_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_ICLKEN4),
.enable_bit = OMAP24XX_EN_PKA_SHIFT,
.recalc = &followparent_recalc,
@@ -2526,7 +2526,7 @@ static struct clk usb_fck = {
.name = "usb_fck",
.parent = &func_48m_ck,
.flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP24XX_EN_USB_SHIFT,
.recalc = &followparent_recalc,
@@ -2536,7 +2536,7 @@ static struct clk usbhs_ick = {
.name = "usbhs_ick",
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_USBHS_SHIFT,
.recalc = &followparent_recalc,
@@ -2546,7 +2546,7 @@ static struct clk mmchs1_ick = {
.name = "mmchs_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
.recalc = &followparent_recalc,
@@ -2556,7 +2556,7 @@ static struct clk mmchs1_fck = {
.name = "mmchs_fck",
.parent = &func_96m_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
.recalc = &followparent_recalc,
@@ -2567,7 +2567,7 @@ static struct clk mmchs2_ick = {
.id = 1,
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
.recalc = &followparent_recalc,
@@ -2587,7 +2587,7 @@ static struct clk gpio5_ick = {
.name = "gpio5_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_GPIO5_SHIFT,
.recalc = &followparent_recalc,
@@ -2597,7 +2597,7 @@ static struct clk gpio5_fck = {
.name = "gpio5_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_GPIO5_SHIFT,
.recalc = &followparent_recalc,
@@ -2607,7 +2607,7 @@ static struct clk mdm_intc_ick = {
.name = "mdm_intc_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, CM_ICLKEN2),
.enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
.recalc = &followparent_recalc,
@@ -2617,7 +2617,7 @@ static struct clk mmchsdb1_fck = {
.name = "mmchsdb_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
.recalc = &followparent_recalc,
@@ -2628,7 +2628,7 @@ static struct clk mmchsdb2_fck = {
.id = 1,
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP243X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.enable_reg = _CM_REG_OFFSET(CORE_MOD, OMAP24XX_CM_FCLKEN2),
.enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
.recalc = &followparent_recalc,
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 419b09f..147a8b2 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1088,7 +1088,7 @@ static struct clk mpu_ck = {
.clksel = mpu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "mpu_clkdm",
+ .clkdm = { .name = "mpu_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1166,7 +1166,7 @@ static struct clk iva2_ck = {
.clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
.clksel = iva2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
- .clkdm_name = "iva2_clkdm",
+ .clkdm = { .name = "iva2_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1181,7 +1181,7 @@ static struct clk l3_ick = {
.clksel = div2_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1199,7 +1199,7 @@ static struct clk l4_ick = {
.clksel = div2_l3_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,

};
@@ -1249,7 +1249,7 @@ static struct clk gfx_l3_fck = {
.clksel = gfx_l3_clksel,
.flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "gfx_3430es1_clkdm",
+ .clkdm = { .name = "gfx_3430es1_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1257,7 +1257,7 @@ static struct clk gfx_l3_ick = {
.name = "gfx_l3_ick",
.parent = &gfx_l3_ck,
.flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK,
- .clkdm_name = "gfx_3430es1_clkdm",
+ .clkdm = { .name = "gfx_3430es1_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1268,7 +1268,7 @@ static struct clk gfx_cg1_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
- .clkdm_name = "gfx_3430es1_clkdm",
+ .clkdm = { .name = "gfx_3430es1_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1279,7 +1279,7 @@ static struct clk gfx_cg2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(GFX_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES1_EN_3D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
- .clkdm_name = "gfx_3430es1_clkdm",
+ .clkdm = { .name = "gfx_3430es1_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1312,7 +1312,7 @@ static struct clk sgx_fck = {
.clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
.clksel = sgx_clksel,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "sgx_clkdm",
+ .clkdm = { .name = "sgx_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1323,7 +1323,7 @@ static struct clk sgx_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "sgx_clkdm",
+ .clkdm = { .name = "sgx_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1336,7 +1336,7 @@ static struct clk d2d_26m_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
- .clkdm_name = "d2d_clkdm",
+ .clkdm = { .name = "d2d_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1356,7 +1356,7 @@ static struct clk gpt10_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1370,7 +1370,7 @@ static struct clk gpt11_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1408,7 +1408,7 @@ static struct clk core_96m_fck = {
.parent = &omap_96m_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1419,7 +1419,7 @@ static struct clk mmchs3_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1430,7 +1430,7 @@ static struct clk mmchs2_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1440,7 +1440,7 @@ static struct clk mspro_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1450,7 +1450,7 @@ static struct clk mmchs1_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1461,7 +1461,7 @@ static struct clk i2c3_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1472,7 +1472,7 @@ static struct clk i2c2_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1483,7 +1483,7 @@ static struct clk i2c1_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1517,7 +1517,7 @@ static struct clk mcbsp5_fck = {
.clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
.clksel = mcbsp_15_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1531,7 +1531,7 @@ static struct clk mcbsp1_fck = {
.clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
.clksel = mcbsp_15_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1542,7 +1542,7 @@ static struct clk core_48m_fck = {
.parent = &omap_48m_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1620,7 +1620,7 @@ static struct clk core_12m_fck = {
.parent = &omap_12m_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1659,7 +1659,7 @@ static struct clk ssi_ssr_fck = {
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1685,7 +1685,7 @@ static struct clk core_l3_ick = {
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1695,7 +1695,7 @@ static struct clk hsotgusb_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1705,7 +1705,7 @@ static struct clk sdrc_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SDRC_SHIFT,
.flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1714,7 +1714,7 @@ static struct clk gpmc_fck = {
.parent = &core_l3_ick,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
ENABLE_ON_INIT,
- .clkdm_name = "core_l3_clkdm",
+ .clkdm = { .name = "core_l3_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1745,7 +1745,7 @@ static struct clk core_l4_ick = {
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1755,7 +1755,7 @@ static struct clk usbtll_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
.enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1766,7 +1766,7 @@ static struct clk mmchs3_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1777,7 +1777,7 @@ static struct clk icr_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_ICR_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1787,7 +1787,7 @@ static struct clk aes2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_AES2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1797,7 +1797,7 @@ static struct clk sha12_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SHA12_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1807,7 +1807,7 @@ static struct clk des2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_DES2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1818,7 +1818,7 @@ static struct clk mmchs2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1828,7 +1828,7 @@ static struct clk mmchs1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MMC1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1838,7 +1838,7 @@ static struct clk mspro_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MSPRO_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1848,7 +1848,7 @@ static struct clk hdq_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HDQ_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1859,7 +1859,7 @@ static struct clk mcspi4_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1870,7 +1870,7 @@ static struct clk mcspi3_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1881,7 +1881,7 @@ static struct clk mcspi2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1892,7 +1892,7 @@ static struct clk mcspi1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1903,7 +1903,7 @@ static struct clk i2c3_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1914,7 +1914,7 @@ static struct clk i2c2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1925,7 +1925,7 @@ static struct clk i2c1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_I2C1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1935,7 +1935,7 @@ static struct clk uart2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1945,7 +1945,7 @@ static struct clk uart1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_UART1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1955,7 +1955,7 @@ static struct clk gpt11_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT11_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1965,7 +1965,7 @@ static struct clk gpt10_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_GPT10_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1976,7 +1976,7 @@ static struct clk mcbsp5_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1987,7 +1987,7 @@ static struct clk mcbsp1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1997,7 +1997,7 @@ static struct clk fac_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
.flags = CLOCK_IN_OMAP3430ES1,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2007,7 +2007,7 @@ static struct clk mailboxes_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2027,7 +2027,7 @@ static struct clk ssi_l4_ick = {
.parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2037,7 +2037,7 @@ static struct clk ssi_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2127,7 +2127,7 @@ static struct clk dss1_alwon_fck = {
.clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
.clksel = dss1_alwon_fck_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2138,7 +2138,7 @@ static struct clk dss_tv_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2149,7 +2149,7 @@ static struct clk dss_96m_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2160,7 +2160,7 @@ static struct clk dss2_alwon_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2172,7 +2172,7 @@ static struct clk dss_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "dss_clkdm",
+ .clkdm = { .name = "dss_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2194,7 +2194,7 @@ static struct clk cam_mclk = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "cam_clkdm",
+ .clkdm = { .name = "cam_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2206,7 +2206,7 @@ static struct clk cam_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "cam_clkdm",
+ .clkdm = { .name = "cam_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2217,7 +2217,7 @@ static struct clk csi2_96m_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_CSI2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "cam_clkdm",
+ .clkdm = { .name = "cam_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2230,7 +2230,7 @@ static struct clk usbhost_120m_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "usbhost_clkdm",
+ .clkdm = { .name = "usbhost_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2241,7 +2241,7 @@ static struct clk usbhost_48m_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "usbhost_clkdm",
+ .clkdm = { .name = "usbhost_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2253,7 +2253,7 @@ static struct clk usbhost_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "usbhost_clkdm",
+ .clkdm = { .name = "usbhost_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2305,7 +2305,7 @@ static struct clk gpt1_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2314,7 +2314,7 @@ static struct clk wkup_32k_fck = {
.init = &omap2_init_clk_clkdm,
.parent = &omap_32k_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2324,7 +2324,7 @@ static struct clk gpio1_dbck = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2334,7 +2334,7 @@ static struct clk wdt2_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2342,7 +2342,7 @@ static struct clk wkup_l4_ick = {
.name = "wkup_l4_ick",
.parent = &sys_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2354,7 +2354,7 @@ static struct clk usim_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2364,7 +2364,7 @@ static struct clk wdt2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2374,7 +2374,7 @@ static struct clk wdt1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2384,7 +2384,7 @@ static struct clk gpio1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2394,7 +2394,7 @@ static struct clk omap_32ksync_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2405,7 +2405,7 @@ static struct clk gpt12_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2415,7 +2415,7 @@ static struct clk gpt1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "wkup_clkdm",
+ .clkdm = { .name = "wkup_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2429,7 +2429,7 @@ static struct clk per_96m_fck = {
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2439,7 +2439,7 @@ static struct clk per_48m_fck = {
.init = &omap2_init_clk_clkdm,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2449,7 +2449,7 @@ static struct clk uart3_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2462,7 +2462,7 @@ static struct clk gpt2_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2475,7 +2475,7 @@ static struct clk gpt3_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2488,7 +2488,7 @@ static struct clk gpt4_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2501,7 +2501,7 @@ static struct clk gpt5_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2514,7 +2514,7 @@ static struct clk gpt6_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2527,7 +2527,7 @@ static struct clk gpt7_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2540,7 +2540,7 @@ static struct clk gpt8_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2553,14 +2553,14 @@ static struct clk gpt9_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

static struct clk per_32k_alwon_fck = {
.name = "per_32k_alwon_fck",
.parent = &omap_32k_fck,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.recalc = &followparent_recalc,
};
@@ -2571,7 +2571,7 @@ static struct clk gpio6_dbck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2581,7 +2581,7 @@ static struct clk gpio5_dbck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2591,7 +2591,7 @@ static struct clk gpio4_dbck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2601,7 +2601,7 @@ static struct clk gpio3_dbck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2611,7 +2611,7 @@ static struct clk gpio2_dbck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2621,7 +2621,7 @@ static struct clk wdt3_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2630,7 +2630,7 @@ static struct clk per_l4_ick = {
.parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2640,7 +2640,7 @@ static struct clk gpio6_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2650,7 +2650,7 @@ static struct clk gpio5_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2660,7 +2660,7 @@ static struct clk gpio4_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2670,7 +2670,7 @@ static struct clk gpio3_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2680,7 +2680,7 @@ static struct clk gpio2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2690,7 +2690,7 @@ static struct clk wdt3_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2700,7 +2700,7 @@ static struct clk uart3_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_UART3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2710,7 +2710,7 @@ static struct clk gpt9_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT9_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2720,7 +2720,7 @@ static struct clk gpt8_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT8_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2730,7 +2730,7 @@ static struct clk gpt7_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT7_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2740,7 +2740,7 @@ static struct clk gpt6_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT6_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2750,7 +2750,7 @@ static struct clk gpt5_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT5_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2760,7 +2760,7 @@ static struct clk gpt4_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2770,7 +2770,7 @@ static struct clk gpt3_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2780,7 +2780,7 @@ static struct clk gpt2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2791,7 +2791,7 @@ static struct clk mcbsp2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2802,7 +2802,7 @@ static struct clk mcbsp3_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2813,7 +2813,7 @@ static struct clk mcbsp4_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2833,7 +2833,7 @@ static struct clk mcbsp2_fck = {
.clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2847,7 +2847,7 @@ static struct clk mcbsp3_fck = {
.clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2861,7 +2861,7 @@ static struct clk mcbsp4_fck = {
.clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
.clksel = mcbsp_234_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "per_clkdm",
+ .clkdm = { .name = "per_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2909,7 +2909,7 @@ static struct clk emu_src_ck = {
.clksel_mask = OMAP3430_MUX_CTRL_MASK,
.clksel = emu_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2933,7 +2933,7 @@ static struct clk pclk_fck = {
.clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
.clksel = pclk_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2956,7 +2956,7 @@ static struct clk pclkx2_fck = {
.clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
.clksel = pclkx2_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2972,7 +2972,7 @@ static struct clk atclk_fck = {
.clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
.clksel = atclk_emu_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2983,7 +2983,7 @@ static struct clk traceclk_src_fck = {
.clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
.clksel = emu_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -3006,7 +3006,7 @@ static struct clk traceclk_fck = {
.clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
.clksel = traceclk_clksel,
.flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
- .clkdm_name = "emu_clkdm",
+ .clkdm = { .name = "emu_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -3036,7 +3036,7 @@ static struct clk sr_l4_ick = {
.name = "sr_l4_ick",
.parent = &l4_ick,
.flags = CLOCK_IN_OMAP343X,
- .clkdm_name = "core_l4_clkdm",
+ .clkdm = { .name = "core_l4_clkdm" },
.recalc = &followparent_recalc,
};

diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index d78d3a7..c6762e9 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -81,8 +81,10 @@ struct clk {
u32 clksel_mask;
const struct clksel *clksel;
struct dpll_data *dpll_data;
- const char *clkdm_name;
- struct clockdomain *clkdm;
+ union {
+ const char *name;
+ struct clockdomain *ptr;
+ } clkdm;
#else
__u8 rate_offset;
__u8 src_offset;

2009-01-28 20:43:17

by Paul Walmsley

Subject: [PATCH B 02/10] OMAP2/3 clockdomains: combine pwrdm, pwrdm_name into union in struct clockdomain

struct clockdomain contains a struct powerdomain *pwrdm and const char
*pwrdm_name. The pwrdm_name is only used at initialization to look up
the appropriate pwrdm pointer. Combining these into a union saves
about 100 bytes on 3430SDP. This patch should not cause any change in
kernel function.

Boot-tested on 3430SDP ES2.

linux-omap source commit is 718fc6cd4db902aa2242a736cc3feb8744a4c71a.

Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
---
arch/arm/mach-omap2/clockdomain.c | 58 +++++++++++--------------
arch/arm/mach-omap2/clockdomains.h | 54 ++++++++++++-----------
arch/arm/plat-omap/include/mach/clockdomain.h | 24 ++++++----
3 files changed, 68 insertions(+), 68 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 4c3ce9c..882809d 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -71,14 +71,14 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep)
if (!omap_chip_is(autodep->omap_chip))
return;

- pwrdm = pwrdm_lookup(autodep->pwrdm_name);
+ pwrdm = pwrdm_lookup(autodep->pwrdm.name);
if (!pwrdm) {
pr_debug("clockdomain: _autodep_lookup: powerdomain %s "
- "does not exist\n", autodep->pwrdm_name);
+ "does not exist\n", autodep->pwrdm.name);
WARN_ON(1);
return;
}
- autodep->pwrdm = pwrdm;
+ autodep->pwrdm.ptr = pwrdm;

return;
}
@@ -95,16 +95,13 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
{
struct clkdm_pwrdm_autodep *autodep;

- for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
- if (!autodep->pwrdm)
- continue;
-
+ for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
pr_debug("clockdomain: adding %s sleepdep/wkdep for "
- "pwrdm %s\n", autodep->pwrdm_name,
- clkdm->pwrdm->name);
+ "pwrdm %s\n", autodep->pwrdm.ptr->name,
+ clkdm->pwrdm.ptr->name);

- pwrdm_add_sleepdep(clkdm->pwrdm, autodep->pwrdm);
- pwrdm_add_wkdep(clkdm->pwrdm, autodep->pwrdm);
+ pwrdm_add_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
+ pwrdm_add_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
}
}

@@ -120,16 +117,13 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
{
struct clkdm_pwrdm_autodep *autodep;

- for (autodep = autodeps; autodep->pwrdm_name; autodep++) {
- if (!autodep->pwrdm)
- continue;
-
+ for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
pr_debug("clockdomain: removing %s sleepdep/wkdep for "
- "pwrdm %s\n", autodep->pwrdm_name,
- clkdm->pwrdm->name);
+ "pwrdm %s\n", autodep->pwrdm.ptr->name,
+ clkdm->pwrdm.ptr->name);

- pwrdm_del_sleepdep(clkdm->pwrdm, autodep->pwrdm);
- pwrdm_del_wkdep(clkdm->pwrdm, autodep->pwrdm);
+ pwrdm_del_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
+ pwrdm_del_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr);
}
}

@@ -179,7 +173,7 @@ void clkdm_init(struct clockdomain **clkdms,

autodeps = init_autodeps;
if (autodeps)
- for (autodep = autodeps; autodep->pwrdm_name; autodep++)
+ for (autodep = autodeps; autodep->pwrdm.ptr; autodep++)
_autodep_lookup(autodep);
}

@@ -202,13 +196,13 @@ int clkdm_register(struct clockdomain *clkdm)
if (!omap_chip_is(clkdm->omap_chip))
return -EINVAL;

- pwrdm = pwrdm_lookup(clkdm->pwrdm_name);
+ pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
if (!pwrdm) {
pr_debug("clockdomain: clkdm_register %s: powerdomain %s "
- "does not exist\n", clkdm->name, clkdm->pwrdm_name);
+ "does not exist\n", clkdm->name, clkdm->pwrdm.name);
return -EINVAL;
}
- clkdm->pwrdm = pwrdm;
+ clkdm->pwrdm.ptr = pwrdm;

mutex_lock(&clkdm_mutex);
/* Verify that the clockdomain is not already registered */
@@ -242,7 +236,7 @@ int clkdm_unregister(struct clockdomain *clkdm)
if (!clkdm)
return -EINVAL;

- pwrdm_del_clkdm(clkdm->pwrdm, clkdm);
+ pwrdm_del_clkdm(clkdm->pwrdm.ptr, clkdm);

mutex_lock(&clkdm_mutex);
list_del(&clkdm->node);
@@ -327,7 +321,7 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
if (!clkdm)
return NULL;

- return clkdm->pwrdm;
+ return clkdm->pwrdm.ptr;
}


@@ -348,7 +342,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
if (!clkdm)
return -EINVAL;

- v = cm_read_mod_reg(clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
+ v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
v &= clkdm->clktrctrl_mask;
v >>= __ffs(clkdm->clktrctrl_mask);

@@ -380,7 +374,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
if (cpu_is_omap24xx()) {

cm_set_mod_reg_bits(OMAP24XX_FORCESTATE,
- clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
+ clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);

} else if (cpu_is_omap34xx()) {

@@ -388,7 +382,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
__ffs(clkdm->clktrctrl_mask));

cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
- clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
+ clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);

} else {
BUG();
@@ -422,7 +416,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
if (cpu_is_omap24xx()) {

cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE,
- clkdm->pwrdm->prcm_offs, PM_PWSTCTRL);
+ clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL);

} else if (cpu_is_omap34xx()) {

@@ -430,7 +424,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
__ffs(clkdm->clktrctrl_mask));

cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v,
- clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
+ clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);

} else {
BUG();
@@ -478,7 +472,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)

cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
v << __ffs(clkdm->clktrctrl_mask),
- clkdm->pwrdm->prcm_offs,
+ clkdm->pwrdm.ptr->prcm_offs,
CM_CLKSTCTRL);
}

@@ -516,7 +510,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)

cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
v << __ffs(clkdm->clktrctrl_mask),
- clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL);
+ clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);

if (atomic_read(&clkdm->usecount) > 0)
_clkdm_del_autodeps(clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index cd86dcc..e17c369 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -19,7 +19,7 @@
/* This is an implicit clockdomain - it is never defined as such in TRM */
static struct clockdomain wkup_clkdm = {
.name = "wkup_clkdm",
- .pwrdm_name = "wkup_pwrdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};

@@ -31,7 +31,7 @@ static struct clockdomain wkup_clkdm = {

static struct clockdomain mpu_2420_clkdm = {
.name = "mpu_clkdm",
- .pwrdm_name = "mpu_pwrdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -39,7 +39,7 @@ static struct clockdomain mpu_2420_clkdm = {

static struct clockdomain iva1_2420_clkdm = {
.name = "iva1_clkdm",
- .pwrdm_name = "dsp_pwrdm",
+ .pwrdm = { .name = "dsp_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -56,7 +56,7 @@ static struct clockdomain iva1_2420_clkdm = {

static struct clockdomain mpu_2430_clkdm = {
.name = "mpu_clkdm",
- .pwrdm_name = "mpu_pwrdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -64,7 +64,7 @@ static struct clockdomain mpu_2430_clkdm = {

static struct clockdomain mdm_clkdm = {
.name = "mdm_clkdm",
- .pwrdm_name = "mdm_pwrdm",
+ .pwrdm = { .name = "mdm_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -81,7 +81,7 @@ static struct clockdomain mdm_clkdm = {

static struct clockdomain dsp_clkdm = {
.name = "dsp_clkdm",
- .pwrdm_name = "dsp_pwrdm",
+ .pwrdm = { .name = "dsp_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -89,7 +89,7 @@ static struct clockdomain dsp_clkdm = {

static struct clockdomain gfx_24xx_clkdm = {
.name = "gfx_clkdm",
- .pwrdm_name = "gfx_pwrdm",
+ .pwrdm = { .name = "gfx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -97,7 +97,7 @@ static struct clockdomain gfx_24xx_clkdm = {

static struct clockdomain core_l3_24xx_clkdm = {
.name = "core_l3_clkdm",
- .pwrdm_name = "core_pwrdm",
+ .pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -105,7 +105,7 @@ static struct clockdomain core_l3_24xx_clkdm = {

static struct clockdomain core_l4_24xx_clkdm = {
.name = "core_l4_clkdm",
- .pwrdm_name = "core_pwrdm",
+ .pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -113,7 +113,7 @@ static struct clockdomain core_l4_24xx_clkdm = {

static struct clockdomain dss_24xx_clkdm = {
.name = "dss_clkdm",
- .pwrdm_name = "core_pwrdm",
+ .pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
@@ -130,7 +130,7 @@ static struct clockdomain dss_24xx_clkdm = {

static struct clockdomain mpu_34xx_clkdm = {
.name = "mpu_clkdm",
- .pwrdm_name = "mpu_pwrdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -138,7 +138,7 @@ static struct clockdomain mpu_34xx_clkdm = {

static struct clockdomain neon_clkdm = {
.name = "neon_clkdm",
- .pwrdm_name = "neon_pwrdm",
+ .pwrdm = { .name = "neon_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -146,7 +146,7 @@ static struct clockdomain neon_clkdm = {

static struct clockdomain iva2_clkdm = {
.name = "iva2_clkdm",
- .pwrdm_name = "iva2_pwrdm",
+ .pwrdm = { .name = "iva2_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -154,7 +154,7 @@ static struct clockdomain iva2_clkdm = {

static struct clockdomain gfx_3430es1_clkdm = {
.name = "gfx_clkdm",
- .pwrdm_name = "gfx_pwrdm",
+ .pwrdm = { .name = "gfx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
@@ -162,7 +162,7 @@ static struct clockdomain gfx_3430es1_clkdm = {

static struct clockdomain sgx_clkdm = {
.name = "sgx_clkdm",
- .pwrdm_name = "sgx_pwrdm",
+ .pwrdm = { .name = "sgx_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
@@ -177,7 +177,7 @@ static struct clockdomain sgx_clkdm = {
*/
static struct clockdomain d2d_clkdm = {
.name = "d2d_clkdm",
- .pwrdm_name = "core_pwrdm",
+ .pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -185,7 +185,7 @@ static struct clockdomain d2d_clkdm = {

static struct clockdomain core_l3_34xx_clkdm = {
.name = "core_l3_clkdm",
- .pwrdm_name = "core_pwrdm",
+ .pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -193,7 +193,7 @@ static struct clockdomain core_l3_34xx_clkdm = {

static struct clockdomain core_l4_34xx_clkdm = {
.name = "core_l4_clkdm",
- .pwrdm_name = "core_pwrdm",
+ .pwrdm = { .name = "core_pwrdm" },
.flags = CLKDM_CAN_HWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -201,7 +201,7 @@ static struct clockdomain core_l4_34xx_clkdm = {

static struct clockdomain dss_34xx_clkdm = {
.name = "dss_clkdm",
- .pwrdm_name = "dss_pwrdm",
+ .pwrdm = { .name = "dss_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -209,7 +209,7 @@ static struct clockdomain dss_34xx_clkdm = {

static struct clockdomain cam_clkdm = {
.name = "cam_clkdm",
- .pwrdm_name = "cam_pwrdm",
+ .pwrdm = { .name = "cam_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -217,7 +217,7 @@ static struct clockdomain cam_clkdm = {

static struct clockdomain usbhost_clkdm = {
.name = "usbhost_clkdm",
- .pwrdm_name = "usbhost_pwrdm",
+ .pwrdm = { .name = "usbhost_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
@@ -225,7 +225,7 @@ static struct clockdomain usbhost_clkdm = {

static struct clockdomain per_clkdm = {
.name = "per_clkdm",
- .pwrdm_name = "per_pwrdm",
+ .pwrdm = { .name = "per_pwrdm" },
.flags = CLKDM_CAN_HWSUP_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -233,7 +233,7 @@ static struct clockdomain per_clkdm = {

static struct clockdomain emu_clkdm = {
.name = "emu_clkdm",
- .pwrdm_name = "emu_pwrdm",
+ .pwrdm = { .name = "emu_pwrdm" },
.flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -247,14 +247,16 @@ static struct clockdomain emu_clkdm = {

static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
{
- .pwrdm_name = "mpu_pwrdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
{
- .pwrdm_name = "iva2_pwrdm",
+ .pwrdm = { .name = "iva2_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
},
- { NULL }
+ {
+ .pwrdm = { .name = NULL },
+ }
};

/*
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h
index 1f51f01..b9d0dd2 100644
--- a/arch/arm/plat-omap/include/mach/clockdomain.h
+++ b/arch/arm/plat-omap/include/mach/clockdomain.h
@@ -1,5 +1,5 @@
/*
- * linux/include/asm-arm/arch-omap/clockdomain.h
+ * arch/arm/plat-omap/include/mach/clockdomain.h
*
* OMAP2/3 clockdomain framework functions
*
@@ -48,11 +48,13 @@
*/
struct clkdm_pwrdm_autodep {

- /* Name of the powerdomain to add a wkdep/sleepdep on */
- const char *pwrdm_name;
+ union {
+ /* Name of the powerdomain to add a wkdep/sleepdep on */
+ const char *name;

- /* Powerdomain pointer (looked up at clkdm_init() time) */
- struct powerdomain *pwrdm;
+ /* Powerdomain pointer (looked up at clkdm_init() time) */
+ struct powerdomain *ptr;
+ } pwrdm;

/* OMAP chip types that this clockdomain dep is valid on */
const struct omap_chip_id omap_chip;
@@ -64,8 +66,13 @@ struct clockdomain {
/* Clockdomain name */
const char *name;

- /* Powerdomain enclosing this clockdomain */
- const char *pwrdm_name;
+ union {
+ /* Powerdomain enclosing this clockdomain */
+ const char *name;
+
+ /* Powerdomain pointer assigned at clkdm_register() */
+ struct powerdomain *ptr;
+ } pwrdm;

/* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */
const u16 clktrctrl_mask;
@@ -79,9 +86,6 @@ struct clockdomain {
/* Usecount tracking */
atomic_t usecount;

- /* Powerdomain pointer assigned at clkdm_register() */
- struct powerdomain *pwrdm;
-
struct list_head node;

};

2009-01-28 20:43:53

by Paul Walmsley

Subject: [PATCH B 03/10] OMAP2/3 clockdomains: add CM, PRM, virt_opp_clkdm clockdomains

Add clockdomains for the CM and PRM. These replace "wkup_clkdm", a
placeholder clockdomain which does not exist on the hardware. Add a
clockdomain for virtual OPP clocks, "virt_opp_clkdm". Mark all clocks
in the clock tree with a valid clockdomain.

The following TI documents are used as reference:

OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 TRM Version Q
OMAP34xx Multimedia Device Silicon Revision 3.0 Version I TRM
OMAP34xx Multimedia High Security (HS) Device Silicon Revision 3.0 Security
Addendum Version B TRM

This patch includes an earlier fix to sys_clkout2's clockdomain by
Tomi Valkeinen <[email protected]>.

linux-omap source commits are a4061e5422dae1433264b40178f73dc6f1d6d748,
859207f04c6b64ee714a65a58ee629ddde91bfa8, and
f34f5bdd731fe828241d729fd465612a56d7e35f.

Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
Signed-off-by: Tomi Valkeinen <[email protected]>
---
arch/arm/mach-omap2/clock24xx.h | 49 ++++++++++--------
arch/arm/mach-omap2/clock34xx.h | 70 ++++++++++++++++++-------
arch/arm/mach-omap2/clockdomains.h | 30 +++++++++--
arch/arm/plat-omap/include/mach/powerdomain.h | 4 +
4 files changed, 106 insertions(+), 47 deletions(-)

diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 68e3667..50c3e01 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -633,7 +633,7 @@ static struct clk func_32k_ck = {
.rate = 32000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -642,7 +642,7 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
.name = "osc_ck",
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable = &omap2_enable_osc_ck,
.disable = &omap2_disable_osc_ck,
.recalc = &omap2_osc_clk_recalc,
@@ -654,7 +654,7 @@ static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_sys_clk_recalc,
};

@@ -663,7 +663,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -695,7 +695,7 @@ static struct clk dpll_ck = {
.dpll_data = &dpll_dd,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_dpllcore_recalc,
.set_rate = &omap2_reprogram_dpllcore,
};
@@ -706,7 +706,7 @@ static struct clk apll96_ck = {
.rate = 96000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
.enable = &omap2_clk_fixed_enable,
@@ -720,7 +720,7 @@ static struct clk apll54_ck = {
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
.enable = &omap2_clk_fixed_enable,
@@ -755,7 +755,7 @@ static struct clk func_54m_ck = {
.parent = &apll54_ck, /* can also be alt_clk */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_54M_SOURCE,
@@ -768,7 +768,7 @@ static struct clk core_ck = {
.parent = &dpll_ck, /* can also be 32k */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | RATE_PROPAGATES,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -795,7 +795,7 @@ static struct clk func_96m_ck = {
.parent = &apll96_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP2430_96M_SOURCE,
@@ -828,7 +828,7 @@ static struct clk func_48m_ck = {
.parent = &apll96_ck, /* 96M or Alt */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.init = &omap2_init_clksel_parent,
.clksel_reg = _CM_REG_OFFSET(PLL_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_48M_SOURCE,
@@ -844,15 +844,16 @@ static struct clk func_12m_ck = {
.fixed_div = 4,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | PARENT_CONTROLS_CLOCK,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_fixed_divisor_recalc,
};

/* Secure timer, only available in secure mode */
static struct clk wdt1_osc_ck = {
- .name = "ck_wdt1_osc",
+ .name = "wdt1_osc_ck",
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -897,7 +898,7 @@ static struct clk sys_clkout_src = {
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | OFFSET_GR_MOD,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -928,7 +929,7 @@ static struct clk sys_clkout = {
.parent = &sys_clkout_src,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
PARENT_CONTROLS_CLOCK | OFFSET_GR_MOD,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
.clksel = sys_clkout_clksel,
@@ -942,7 +943,7 @@ static struct clk sys_clkout2_src = {
.name = "sys_clkout2_src",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES | OFFSET_GR_MOD,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.enable_bit = OMAP2420_CLKOUT2_EN_SHIFT,
.init = &omap2_init_clksel_parent,
@@ -965,7 +966,7 @@ static struct clk sys_clkout2 = {
.parent = &sys_clkout2_src,
.flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK |
OFFSET_GR_MOD,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.clksel_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKOUT_CTRL_OFFSET),
.clksel_mask = OMAP2420_CLKOUT2_DIV_MASK,
.clksel = sys_clkout2_clksel,
@@ -978,7 +979,7 @@ static struct clk emul_ck = {
.name = "emul_ck",
.parent = &func_54m_ck,
.flags = CLOCK_IN_OMAP242X | OFFSET_GR_MOD,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "cm_clkdm" },
.enable_reg = _GR_MOD_OFFSET(OMAP24XX_PRCM_CLKEMUL_CTRL_OFFSET),
.enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
.recalc = &followparent_recalc,
@@ -2077,27 +2078,29 @@ static struct clk gpios_fck = {
.name = "gpios_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
.recalc = &followparent_recalc,
};

+/* aka WDT2 - REVISIT: we should split wu_l4_iclk from l4_ck */
static struct clk mpu_wdt_ick = {
.name = "mpu_wdt_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
};

+/* aka WDT2 */
static struct clk mpu_wdt_fck = {
.name = "mpu_wdt_fck",
.parent = &func_32k_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.recalc = &followparent_recalc,
@@ -2114,11 +2117,12 @@ static struct clk sync_32k_ick = {
.recalc = &followparent_recalc,
};

+/* REVISIT: parent is really wu_l4_iclk */
static struct clk wdt1_ick = {
.name = "wdt1_ick",
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
- .clkdm = { .name = "core_l4_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.enable_reg = _CM_REG_OFFSET(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP24XX_EN_WDT1_SHIFT,
.recalc = &followparent_recalc,
@@ -2652,6 +2656,7 @@ static struct clk virt_prcm_set = {
.name = "virt_prcm_set",
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP,
+ .clkdm = { .name = "virt_opp_clkdm" },
.parent = &mpu_ck, /* Indexed by mpu speed, no parent */
.recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
.set_rate = &omap2_select_table_rate,
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 147a8b2..ca432e0 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -70,6 +70,7 @@ static struct clk omap_32k_fck = {
.rate = 32768,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -78,6 +79,7 @@ static struct clk secure_32k_fck = {
.rate = 32768,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -87,6 +89,7 @@ static struct clk virt_12m_ck = {
.rate = 12000000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -95,6 +98,7 @@ static struct clk virt_13m_ck = {
.rate = 13000000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -103,6 +107,7 @@ static struct clk virt_16_8m_ck = {
.rate = 16800000,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -111,6 +116,7 @@ static struct clk virt_19_2m_ck = {
.rate = 19200000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -119,6 +125,7 @@ static struct clk virt_26m_ck = {
.rate = 26000000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -127,6 +134,7 @@ static struct clk virt_38_4m_ck = {
.rate = 38400000,
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -181,6 +189,7 @@ static struct clk osc_sys_ck = {
/* REVISIT: deal with autoextclkmode? */
.flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -205,19 +214,26 @@ static struct clk sys_ck = {
.clksel_mask = OMAP_SYSCLKDIV_MASK,
.clksel = sys_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

static struct clk sys_altclk = {
.name = "sys_altclk",
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &propagate_rate,
};

-/* Optional external clock input for some McBSPs */
+/*
+ * Optional external clock input for some McBSPs
+ * Apparently this is not really in prm_clkdm, but rather is fed into
+ * both CORE and PER separately.
+ */
static struct clk mcbsp_clks = {
.name = "mcbsp_clks",
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &propagate_rate,
};

@@ -229,6 +245,7 @@ static struct clk sys_clkout1 = {
.enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
.enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
.flags = CLOCK_IN_OMAP343X,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -509,6 +526,7 @@ static struct clk core_ck = {
.clksel = core_ck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -673,6 +691,7 @@ static struct clk omap_96m_alwon_fck = {
.clksel = omap_96m_alwon_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -681,6 +700,7 @@ static struct clk cm_96m_fck = {
.parent = &omap_96m_alwon_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -709,6 +729,7 @@ static struct clk omap_96m_fck = {
.clksel = omap_96m_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -751,6 +772,7 @@ static struct clk virt_omap_54m_fck = {
.clksel = virt_omap_54m_fck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -778,6 +800,7 @@ static struct clk omap_54m_fck = {
.clksel = omap_54m_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -805,6 +828,7 @@ static struct clk omap_48m_fck = {
.clksel = omap_48m_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -814,6 +838,7 @@ static struct clk omap_12m_fck = {
.fixed_div = 4,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_fixed_divisor_recalc,
};

@@ -1007,6 +1032,7 @@ static struct clk clkout2_src_ck = {
.clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
.clksel = clkout2_src_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1031,6 +1057,7 @@ static struct clk sys_clkout2 = {
.clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
.clksel = sys_clkout2_clksel,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1041,6 +1068,7 @@ static struct clk corex2_fck = {
.parent = &dpll3_m2x2_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -1051,10 +1079,6 @@ static const struct clksel div2_core_clksel[] = {
{ .parent = NULL }
};

-/*
- * REVISIT: Are these in DPLL power domain or CM power domain? docs
- * may be inconsistent here?
- */
static struct clk dpll1_fck = {
.name = "dpll1_fck",
.parent = &core_ck,
@@ -1064,6 +1088,7 @@ static struct clk dpll1_fck = {
.clksel = div2_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1139,6 +1164,7 @@ static struct clk dpll2_fck = {
.clksel = div2_core_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1217,6 +1243,7 @@ static struct clk rm_ick = {
.clksel_mask = OMAP3430_CLKSEL_RM_MASK,
.clksel = div2_l4_clksel,
.flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -1380,6 +1407,7 @@ static struct clk cpefuse_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
.enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
+ .clkdm = { .name = "cm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2138,7 +2166,7 @@ static struct clk dss_tv_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "dss_clkdm" },
+ .clkdm = { .name = "dss_clkdm" }, /* XXX: in cm_clkdm? */
.recalc = &followparent_recalc,
};

@@ -2292,6 +2320,7 @@ static struct clk usim_fck = {
.clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
.clksel = usim_clksel,
.flags = CLOCK_IN_OMAP3430ES2,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2305,7 +2334,7 @@ static struct clk gpt1_fck = {
.clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
.clksel = omap343x_gpt_clksel,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -2314,7 +2343,7 @@ static struct clk wkup_32k_fck = {
.init = &omap2_init_clk_clkdm,
.parent = &omap_32k_fck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2324,7 +2353,7 @@ static struct clk gpio1_dbck = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2334,7 +2363,7 @@ static struct clk wdt2_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2342,7 +2371,7 @@ static struct clk wkup_l4_ick = {
.name = "wkup_l4_ick",
.parent = &sys_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2354,7 +2383,7 @@ static struct clk usim_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
.flags = CLOCK_IN_OMAP3430ES2,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2364,7 +2393,7 @@ static struct clk wdt2_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT2_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2374,7 +2403,7 @@ static struct clk wdt1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_WDT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2384,7 +2413,7 @@ static struct clk gpio1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPIO1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2394,18 +2423,17 @@ static struct clk omap_32ksync_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

-/* XXX This clock no longer exists in 3430 TRM rev F */
static struct clk gpt12_ick = {
.name = "gpt12_ick",
.parent = &wkup_l4_ick,
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT12_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -2415,7 +2443,7 @@ static struct clk gpt1_ick = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_EN_GPT1_SHIFT,
.flags = CLOCK_IN_OMAP343X,
- .clkdm = { .name = "wkup_clkdm" },
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -3019,6 +3047,7 @@ static struct clk sr1_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR1_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -3029,6 +3058,7 @@ static struct clk sr2_fck = {
.enable_reg = _OMAP34XX_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_SR2_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -3047,6 +3077,7 @@ static struct clk gpt12_fck = {
.name = "gpt12_fck",
.parent = &secure_32k_fck,
.flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

@@ -3054,6 +3085,7 @@ static struct clk wdt1_fck = {
.name = "wdt1_fck",
.parent = &secure_32k_fck,
.flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
+ .clkdm = { .name = "prm_clkdm" },
.recalc = &followparent_recalc,
};

diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index e17c369..e8320ee 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -14,15 +14,35 @@

/*
* OMAP2/3-common clockdomains
+ *
+ * Even though the 2420 has a single PRCM module from the
+ * interconnect's perspective, internally it does appear to have
+ * separate PRM and CM clockdomains. The usual test case is
+ * sys_clkout/sys_clkout2.
*/

-/* This is an implicit clockdomain - it is never defined as such in TRM */
-static struct clockdomain wkup_clkdm = {
- .name = "wkup_clkdm",
+static struct clockdomain prm_clkdm = {
+ .name = "prm_clkdm",
.pwrdm = { .name = "wkup_pwrdm" },
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
};

+static struct clockdomain cm_clkdm = {
+ .name = "cm_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
+};
+
+/*
+ * virt_opp_clkdm is intended solely for use with virtual OPP clocks,
+ * e.g., virt_prcm_set, until OPP handling is rationalized.
+ */
+static struct clockdomain virt_opp_clkdm = {
+ .name = "virt_opp_clkdm",
+ .pwrdm = { .name = "wkup_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
+};
+
/*
* 2420-only clockdomains
*/
@@ -265,7 +285,9 @@ static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {

static struct clockdomain *clockdomains_omap[] = {

- &wkup_clkdm,
+ &cm_clkdm,
+ &prm_clkdm,
+ &virt_opp_clkdm,

#ifdef CONFIG_ARCH_OMAP2420
&mpu_2420_clkdm,
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h
index 4948cb7..69c9e67 100644
--- a/arch/arm/plat-omap/include/mach/powerdomain.h
+++ b/arch/arm/plat-omap/include/mach/powerdomain.h
@@ -50,9 +50,9 @@

/*
* Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain is probably the worst case.
+ * CORE powerdomain on OMAP3 is the worst case
*/
-#define PWRDM_MAX_CLKDMS 3
+#define PWRDM_MAX_CLKDMS 4

/* XXX A completely arbitrary number. What is reasonable here? */
#define PWRDM_TRANSITION_BAILOUT 100000

2009-01-28 20:44:21

by Paul Walmsley

Subject: [PATCH B 04/10] OMAP3 PRCM: add DPLL1-5 powerdomains, clockdomains; mark clocks

Each DPLL exists in its own powerdomain (cf 34xx TRM figure 4-18) and
clockdomain; so, create powerdomain and clockdomain structures for them.
Mark each DPLL clock as belonging to their respective DPLL clockdomain.
cf. 34xx TRM Table 4-27 (among other references).

linux-omap source commits are acdb615850b9b4f7d1ab68133a16be8c8c0e7419 and
a8798a48f33e9268dcc7f30a4b4a3ce4220fe0c9.

Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
---
arch/arm/mach-omap2/clock34xx.h | 27 +++++++++++++++++++++++++
arch/arm/mach-omap2/clockdomains.h | 35 ++++++++++++++++++++++++++++++++
arch/arm/mach-omap2/powerdomains.h | 5 +++++
arch/arm/mach-omap2/powerdomains34xx.h | 31 ++++++++++++++++++++++++++++
4 files changed, 98 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index ca432e0..e1650f2 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -316,6 +316,7 @@ static struct clk dpll1_ck = {
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
+ .clkdm = { .name = "dpll1_clkdm" },
.recalc = &omap3_dpll_recalc,
};

@@ -328,6 +329,7 @@ static struct clk dpll1_x2_ck = {
.parent = &dpll1_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll1_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};

@@ -350,6 +352,7 @@ static struct clk dpll1_x2m2_ck = {
.clksel = div16_dpll1_x2m2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll1_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -387,6 +390,7 @@ static struct clk dpll2_ck = {
.disable = &omap3_noncore_dpll_disable,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
+ .clkdm = { .name = "dpll2_clkdm" },
.recalc = &omap3_dpll_recalc,
};

@@ -409,6 +413,7 @@ static struct clk dpll2_m2_ck = {
.clksel = div16_dpll2_m2x2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll2_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -440,6 +445,7 @@ static struct clk dpll3_ck = {
.dpll_data = &dpll3_dd,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
.round_rate = &omap2_dpll_round_rate,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap3_dpll_recalc,
};

@@ -452,6 +458,7 @@ static struct clk dpll3_x2_ck = {
.parent = &dpll3_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};

@@ -509,6 +516,7 @@ static struct clk dpll3_m2_ck = {
.clksel = div31_dpll3m2_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -544,6 +552,7 @@ static struct clk dpll3_m2x2_ck = {
.clksel = dpll3_m2x2_ck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -563,6 +572,7 @@ static struct clk dpll3_m3_ck = {
.clksel = div16_dpll3_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -573,6 +583,7 @@ static struct clk dpll3_m3x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};

@@ -591,6 +602,7 @@ static struct clk emu_core_alwon_ck = {
.clksel = emu_core_alwon_ck_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll3_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -626,6 +638,7 @@ static struct clk dpll4_ck = {
.disable = &omap3_noncore_dpll_disable,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_dpll_recalc,
};

@@ -639,6 +652,7 @@ static struct clk dpll4_x2_ck = {
.parent = &dpll4_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};

@@ -657,6 +671,7 @@ static struct clk dpll4_m2_ck = {
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -667,6 +682,7 @@ static struct clk dpll4_m2x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_96M_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};

@@ -743,6 +759,7 @@ static struct clk dpll4_m3_ck = {
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -754,6 +771,7 @@ static struct clk dpll4_m3x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};

@@ -852,6 +870,7 @@ static struct clk dpll4_m4_ck = {
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
.set_rate = &omap2_clksel_set_rate,
.round_rate = &omap2_clksel_round_rate,
@@ -864,6 +883,7 @@ static struct clk dpll4_m4x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};

@@ -877,6 +897,7 @@ static struct clk dpll4_m5_ck = {
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -887,6 +908,7 @@ static struct clk dpll4_m5x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};

@@ -900,6 +922,7 @@ static struct clk dpll4_m6_ck = {
.clksel = div16_dpll4_clksel,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap2_clksel_recalc,
};

@@ -911,6 +934,7 @@ static struct clk dpll4_m6x2_ck = {
.enable_reg = _OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &omap3_clkoutx2_recalc,
};

@@ -919,6 +943,7 @@ static struct clk emu_per_alwon_ck = {
.parent = &dpll4_m6x2_ck,
.flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll4_clkdm" },
.recalc = &followparent_recalc,
};

@@ -955,6 +980,7 @@ static struct clk dpll5_ck = {
.disable = &omap3_noncore_dpll_disable,
.round_rate = &omap2_dpll_round_rate,
.set_rate = &omap3_noncore_dpll_set_rate,
+ .clkdm = { .name = "dpll5_clkdm" },
.recalc = &omap3_dpll_recalc,
};

@@ -972,6 +998,7 @@ static struct clk dpll5_m2_ck = {
.clksel = div16_dpll5_clksel,
.flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
PARENT_CONTROLS_CLOCK,
+ .clkdm = { .name = "dpll5_clkdm" },
.recalc = &omap2_clksel_recalc,
};

diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index e8320ee..bafa650 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -259,6 +259,36 @@ static struct clockdomain emu_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

+static struct clockdomain dpll1_clkdm = {
+ .name = "dpll1_clkdm",
+ .pwrdm = { .name = "dpll1_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll2_clkdm = {
+ .name = "dpll2_clkdm",
+ .pwrdm = { .name = "dpll2_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll3_clkdm = {
+ .name = "dpll3_clkdm",
+ .pwrdm = { .name = "dpll3_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll4_clkdm = {
+ .name = "dpll4_clkdm",
+ .pwrdm = { .name = "dpll4_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct clockdomain dpll5_clkdm = {
+ .name = "dpll5_clkdm",
+ .pwrdm = { .name = "dpll5_pwrdm" },
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+};
+
#endif /* CONFIG_ARCH_OMAP34XX */

/*
@@ -321,6 +351,11 @@ static struct clockdomain *clockdomains_omap[] = {
&usbhost_clkdm,
&per_clkdm,
&emu_clkdm,
+ &dpll1_clkdm,
+ &dpll2_clkdm,
+ &dpll3_clkdm,
+ &dpll4_clkdm,
+ &dpll5_clkdm,
#endif

NULL,
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 1e151fa..1329443 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -178,6 +178,11 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
&emu_pwrdm,
&sgx_pwrdm,
&usbhost_pwrdm,
+ &dpll1_pwrdm,
+ &dpll2_pwrdm,
+ &dpll3_pwrdm,
+ &dpll4_pwrdm,
+ &dpll5_pwrdm,
#endif

NULL
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 3a8e4fb..7b63fa0 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -322,6 +322,37 @@ static struct powerdomain usbhost_pwrdm = {
},
};

+static struct powerdomain dpll1_pwrdm = {
+ .name = "dpll1_pwrdm",
+ .prcm_offs = MPU_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll2_pwrdm = {
+ .name = "dpll2_pwrdm",
+ .prcm_offs = OMAP3430_IVA2_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll3_pwrdm = {
+ .name = "dpll3_pwrdm",
+ .prcm_offs = PLL_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll4_pwrdm = {
+ .name = "dpll4_pwrdm",
+ .prcm_offs = PLL_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+static struct powerdomain dpll5_pwrdm = {
+ .name = "dpll5_pwrdm",
+ .prcm_offs = PLL_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
+};
+
+
#endif /* CONFIG_ARCH_OMAP34XX */

2009-01-28 20:44:40

by Paul Walmsley

Subject: [PATCH B 06/10] OMAP3 pwrdm: add CORE SAR handling (for USBTLL module)

34xx TRM Delta G->H notes that the CORE powerdomain has a hardware
save-and-restore (SAR) control bit for the USBTLL module, similar to
the USBHOST powerdomain SAR bit. Split the existing core_34xx struct
powerdomain into two structs, one for ES1 and one for ES2, and add the
PWRDM_HAS_HDWR_SAR flag to the ES2 powerdomain.

Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
---
arch/arm/mach-omap2/powerdomains.h | 3 ++-
arch/arm/mach-omap2/powerdomains34xx.h | 23 +++++++++++++++++++++--
2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h
index 1329443..51623e2 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains.h
@@ -171,7 +171,8 @@ static struct powerdomain *powerdomains_omap[] __initdata = {
&iva2_pwrdm,
&mpu_34xx_pwrdm,
&neon_pwrdm,
- &core_34xx_pwrdm,
+ &core_34xx_es1_pwrdm,
+ &core_34xx_es2_pwrdm,
&cam_pwrdm,
&dss_pwrdm,
&per_pwrdm,
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 7b63fa0..446a1ed 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -200,12 +200,31 @@ static struct powerdomain mpu_34xx_pwrdm = {
};

/* No wkdeps or sleepdeps for 34xx core apparently */
-static struct powerdomain core_34xx_pwrdm = {
+static struct powerdomain core_34xx_es1_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = CORE_MOD,
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .dep_bit = OMAP3430_EN_CORE_SHIFT,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
+ [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
+ [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
+ },
+};
+
+/* No wkdeps or sleepdeps for 34xx core apparently */
+static struct powerdomain core_34xx_es2_pwrdm = {
+ .name = "core_pwrdm",
+ .prcm_offs = CORE_MOD,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
.pwrsts = PWRSTS_OFF_RET_ON,
.dep_bit = OMAP3430_EN_CORE_SHIFT,
+ .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */

2009-01-28 20:46:18

by Paul Walmsley

Subject: [PATCH B 08/10] OMAP: wait for pwrdm transition after clk_enable()

From: Tomi Valkeinen <[email protected]>

Enabling clock in a disabled power domain causes the power domain to be
turned on. However, the power transition is not always finished when
clk_enable() returns and this randomly crashes the kernel when an
interrupt happens right after the clk_enable, and the kernel tries to
read the irq status register for that domain.

Why the irq status register is inaccessible, I don't know. Also it
doesn't seem to be related to the module being not powered up, but to
the transition itself.

The same could perhaps happen after clk_disable also, but I have not
witnessed that.

The problem affects at least dss, cam and sgx clocks.

This change waits for the transition to be finished before returning
from omap2_clkdm_clk_enable().

Signed-off-by: Tomi Valkeinen <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
---
arch/arm/mach-omap2/clockdomain.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 882809d..ad6dfe4 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -561,6 +561,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
else
omap2_clkdm_wakeup(clkdm);

+ pwrdm_wait_transition(clkdm->pwrdm.ptr);
+
return 0;
}

2009-01-28 20:46:36

by Paul Walmsley

Subject: [PATCH B 07/10] OMAP3 powerdomains: remove RET from SGX power states list

The SGX device on OMAP3 does not support retention, so remove RET from the
list of possible SGX power states. Problem debugged by Richard Woodruff
<[email protected]>.

Signed-off-by: Richard Woodruff <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
---
arch/arm/mach-omap2/powerdomains34xx.h | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h
index 446a1ed..edfad42 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains34xx.h
@@ -255,6 +255,11 @@ static struct powerdomain dss_pwrdm = {
},
};

+/*
+ * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
+ * possible SGX powerstate, the SGX device itself does not support
+ * retention.
+ */
static struct powerdomain sgx_pwrdm = {
.name = "sgx_pwrdm",
.prcm_offs = OMAP3430ES2_SGX_MOD,
@@ -262,7 +267,7 @@ static struct powerdomain sgx_pwrdm = {
.wkdep_srcs = gfx_sgx_wkdeps,
.sleepdep_srcs = cam_gfx_sleepdeps,
/* XXX This is accurate for 3430 SGX, but what about GFX? */
- .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts = PWRSTS_OFF_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET,
.banks = 1,
.pwrsts_mem_ret = {

2009-01-28 20:52:22

by Paul Walmsley

Subject: [PATCH B 10/10] OMAP3: PM: Emu_pwrdm is switched off by hardware even when sdti is in use

From: Jouni Hogander <[email protected]>

Using sdti doesn't keep emu_pwrdm on if hardware supervised pwrdm
transitions are used. This causes sdti stop to work when power
management is initialized and hardware supervised pwrdm control is
enabled. This patch disables hardware supervised pwrdm control for
emu_pwrdm. Now emu_pwrdm is switched off on boot by software when it
is not used.

Signed-off-by: Jouni Hogander <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
---
arch/arm/mach-omap2/clockdomains.h | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
index bafa650..3d4eaca 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -251,10 +251,14 @@ static struct clockdomain per_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

+/*
+ * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
+ * switched of even if sdti is in use
+ */
static struct clockdomain emu_clkdm = {
.name = "emu_clkdm",
.pwrdm = { .name = "emu_pwrdm" },
- .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
+ .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

2009-01-28 20:54:15

by Paul Walmsley

Subject: [PATCH B 09/10] OMAP2/3 clockdomains: autodeps should respect platform flags

Fix the clockdomain autodep code to respect omap_chip platform flags.

Resolves "Unable to handle kernel paging request at virtual address
5f75706d" panic during power management initialization on OMAP2.

Signed-off-by: Paul Walmsley <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
---
arch/arm/mach-omap2/clockdomain.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ad6dfe4..f713d0b 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -96,6 +96,9 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
struct clkdm_pwrdm_autodep *autodep;

for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
+ if (!omap_chip_is(autodep->omap_chip))
+ continue;
+
pr_debug("clockdomain: adding %s sleepdep/wkdep for "
"pwrdm %s\n", autodep->pwrdm.ptr->name,
clkdm->pwrdm.ptr->name);
@@ -118,6 +121,9 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
struct clkdm_pwrdm_autodep *autodep;

for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) {
+ if (!omap_chip_is(autodep->omap_chip))
+ continue;
+
pr_debug("clockdomain: removing %s sleepdep/wkdep for "
"pwrdm %s\n", autodep->pwrdm.ptr->name,
clkdm->pwrdm.ptr->name);

2009-01-29 02:21:51

by Woodruff, Richard

Subject: RE: [PATCH B 06/10] OMAP3 pwrdm: add CORE SAR handling (for USBTLL module)

> 34xx TRM Delta G->H notes that the CORE powerdomain has a hardware
> save-and-restore (SAR) control bit for the USBTLL module, similar to
> the USBHOST powerdomain SAR bit. Split the existing core_34xx struct
> powerdomain into two structs, one for ES1 and one for ES2, and add the
> PWRDM_HAS_HDWR_SAR flag to the ES2 powerdomain.
>
> Signed-off-by: Paul Walmsley <[email protected]>
> Signed-off-by: Tony Lindgren <[email protected]>
> +
> +/* No wkdeps or sleepdeps for 34xx core apparently */
> +static struct powerdomain core_34xx_es2_pwrdm = {
> + .name = "core_pwrdm",
> + .prcm_offs = CORE_MOD,
> + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
> .pwrsts = PWRSTS_OFF_RET_ON,
> .dep_bit = OMAP3430_EN_CORE_SHIFT,
> + .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
> .banks = 2,
> .pwrsts_mem_ret = {
> [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */

TLLSAR is not functional till ES3.1 (and beyound). Is it possible to flag it this way?

If you try and use it your system will deadlock on 2nd OFF mode transition due to hardware bug.

Regards,
Richard W.
????{.n?+???????+%?????ݶ??w??{.n?+????{??G?????{ay?ʇڙ?,j??f???h?????????z_??(?階?ݢj"???m??????G????????????&???~???iO???z??v?^?m????????????I?

2009-01-29 07:47:48

by Paul Walmsley

Subject: RE: [PATCH B 06/10] OMAP3 pwrdm: add CORE SAR handling (for USBTLL module)

Hi Richard,

On Wed, 28 Jan 2009, Woodruff, Richard wrote:

> > 34xx TRM Delta G->H notes that the CORE powerdomain has a hardware
> > save-and-restore (SAR) control bit for the USBTLL module, similar to
> > the USBHOST powerdomain SAR bit. Split the existing core_34xx struct
> > powerdomain into two structs, one for ES1 and one for ES2, and add the
> > PWRDM_HAS_HDWR_SAR flag to the ES2 powerdomain.
> >
> > Signed-off-by: Paul Walmsley <[email protected]>
> > Signed-off-by: Tony Lindgren <[email protected]>
> > +
> > +/* No wkdeps or sleepdeps for 34xx core apparently */
> > +static struct powerdomain core_34xx_es2_pwrdm = {
> > + .name = "core_pwrdm",
> > + .prcm_offs = CORE_MOD,
> > + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
> > .pwrsts = PWRSTS_OFF_RET_ON,
> > .dep_bit = OMAP3430_EN_CORE_SHIFT,
> > + .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
> > .banks = 2,
> > .pwrsts_mem_ret = {
> > [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
>
> TLLSAR is not functional till ES3.1 (and beyound). Is it possible to flag it this way?

Yes, it's easy in this case. Thanks for the note. I will send along an
updated patch for this.

> If you try and use it your system will deadlock on 2nd OFF mode transition due to hardware bug.


- Paul

2009-01-29 09:16:04

by Paul Walmsley

Subject: RE: [PATCH B 06/10] OMAP3 pwrdm: add CORE SAR handling (for USBTLL module)

Hi Richard,

On Thu, 29 Jan 2009, Paul Walmsley wrote:

> > TLLSAR is not functional till ES3.1 (and beyound). Is it possible to flag it this way?
>
> Yes, it's easy in this case. Thanks for the note. I will send along an
> updated patch for this.

N.B. - fixxing this required a separate change to the omap_chip flag
system, so I'll send the two necessary patches to the linux-omap mailing
list for further testing.

- Paul

2009-01-31 11:55:45

by Russell King - ARM Linux

Subject: Re: [PATCH B 01/10] OMAP2/3 clock: combine clkdm, clkdm_name into union in struct clk

On Tue, Jan 27, 2009 at 07:44:08PM -0700, Paul Walmsley wrote:
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index 55c5d67..7aa09f5 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -77,17 +77,17 @@ void omap2_init_clk_clkdm(struct clk *clk)
> {
> struct clockdomain *clkdm;
>
> - if (!clk->clkdm_name)
> + if (!clk->clkdm.name)
> return;
>
> - clkdm = clkdm_lookup(clk->clkdm_name);
> + clkdm = clkdm_lookup(clk->clkdm.name);
> if (clkdm) {
> pr_debug("clock: associated clk %s to clkdm %s\n",
> - clk->name, clk->clkdm_name);
> - clk->clkdm = clkdm;
> + clk->name, clk->clkdm.name);
> + clk->clkdm.ptr = clkdm;
> } else {
> pr_debug("clock: could not associate clk %s to "
> - "clkdm %s\n", clk->name, clk->clkdm_name);
> + "clkdm %s\n", clk->name, clk->clkdm.name);
> }

This is unsafe - if the clock domain can not be found, you leave the
union pointing at the string, and there's no way for this to prevent
the clock from being registered.

The result is that:

> - if (clk->clkdm)
> - omap2_clkdm_clk_disable(clk->clkdm, clk);
> + if (clk->clkdm.ptr)
> + omap2_clkdm_clk_disable(clk->clkdm.ptr, clk);

and similar places will pass the pointer to the string, potentially
causing an oops, or worse, data corruption due to scribbing over
someone elses memory.

So I don't think this patch is acceptable as-is.

2009-01-31 12:01:32

by Russell King - ARM Linux

Subject: Re: [PATCH B 02/10] OMAP2/3 clockdomains: combine pwrdm, pwrdm_name into union in struct clockdomain

On Tue, Jan 27, 2009 at 07:44:11PM -0700, Paul Walmsley wrote:
> struct clockdomain contains a struct powerdomain *pwrdm and const char
> *pwrdm_name. The pwrdm_name is only used at initialization to look up
> the appropriate pwrdm pointer. Combining these into a union saves
> about 100 bytes on 3430SDP. This patch should not cause any change in
> kernel function.

For the same reasons as B1, this would seem to be unsafe.

2009-01-31 14:09:55

by Russell King - ARM Linux

Subject: Re: [PATCH B 03/10] OMAP2/3 clockdomains: add CM, PRM, virt_opp_clkdm clockdomains

On Tue, Jan 27, 2009 at 07:44:15PM -0700, Paul Walmsley wrote:
> Add clockdomains for the CM and PRM. These replace "wkup_clkdm", a
> placeholder clockdomain which does not exist on the hardware. Add a
> clockdomain for virtual OPP clocks, "virt_opp_clkdm". Mark all clocks
> in the clock tree with a valid clockdomain.
>
> The following TI documents are used as reference:
>
> OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 TRM Version Q
> OMAP34xx Multimedia Device Silicon Revision 3.0 Version I TRM
> OMAP34xx Multimedia High Security (HS) Device Silicon Revision 3.0 Security
> Addendum Version B TRM
>
> This patch includes an earlier fix to sys_clkout2's clockdomain by
> Tomi Valkeinen <[email protected]>.
>
> linux-omap source commits are a4061e5422dae1433264b40178f73dc6f1d6d748,
> 859207f04c6b64ee714a65a58ee629ddde91bfa8, and
> f34f5bdd731fe828241d729fd465612a56d7e35f.

Given my comments on F6, I've so far avoided merging 859207f.

2009-01-31 14:17:25

by Russell King - ARM Linux

Subject: Re: [PATCH B 04/10] OMAP3 PRCM: add DPLL1-5 powerdomains, clockdomains; mark clocks

On Tue, Jan 27, 2009 at 07:44:18PM -0700, Paul Walmsley wrote:
> Each DPLL exists in its own powerdomain (cf 34xx TRM figure 4-18) and
> clockdomain; so, create powerdomain and clockdomain structures for them.
> Mark each DPLL clock as belonging to their respective DPLL clockdomain.
> cf. 34xx TRM Table 4-27 (among other references).

I don't really see the need to mark all these clocks as having a domain.
Yes, it makes sense to mark the actual DPLL clocks themselves with the
relevent DPLL domain. However, it makes no sense to mark the children
as well.

Why? When we enable a clock, we walk up the tree enabling the domains
first. So, even if we're enabling a child clock, we will walk the tree
up to the DPLL and enable the clock domain before we do anything at all.

Sure, if a clock has a multiplexer and that multiplexer is in a different
clock domain from its parent, it makes sense to. But otherwise it doesn't.

2009-01-31 14:22:43

by Russell King - ARM Linux

Subject: Re: [PATCH B 06/10] OMAP3 pwrdm: add CORE SAR handling (for USBTLL module)

On Thu, Jan 29, 2009 at 02:15:44AM -0700, Paul Walmsley wrote:
> Hi Richard,
>
> On Thu, 29 Jan 2009, Paul Walmsley wrote:
>
> > > TLLSAR is not functional till ES3.1 (and beyound). Is it possible to flag it this way?
> >
> > Yes, it's easy in this case. Thanks for the note. I will send along an
> > updated patch for this.
>
> N.B. - fixxing this required a separate change to the omap_chip flag
> system, so I'll send the two necessary patches to the linux-omap mailing
> list for further testing.

I'll hold off on this patch then.