On Samstag 28 Februar 2009 23:43:51 Yinghai Lu wrote:
> please check this one
> v1 is pulled by Linus from Jesse's pci tree already, and v3 is needed
> to be applied on top of v1
>
> YH
Hi,
yes, this works nicely now. Thanks. (Are you still interested in all the infos
you requested in your last email?) But have you looked at the original patch?
It might be that your current one is not enough to cover all models. In the
original NVidia one following bridges were enabled:
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_C51_MEMC0 0x02F0
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_C51_MEMC1 0x02F1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_C51_MEMC2 0x02F2
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_C51_MEMC3 0x02F3
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_C51_MEMC4 0x02F4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_C51_MEMC5 0x02F5
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_C51_MEMC6 0x02F6
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_C51_MEMC7 0x02F7
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_MEMC 0x0369
As you can see, the one on my board is the MEMC0. I don't know which revisions
have the other ones. The MEMC case had a special bahaviour in the original
patch also:
+ bridge_dev = NULL;
+ while ((bridge_dev = pci_get_device(PCI_VENDOR_ID_NVIDIA,
+ PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_MEMC, bridge_dev))
+ != NULL) {
+ pci_enable_msi_ht_cap(bridge_dev);
+ }
Cheers,
Prakash
[PATCH] Enable HT MSI mapping on all known needed NVidia host bridges
v3 of Yinghai Lu's work only enables HT MSI mapping for one specific host bridge.
Do this also for all known needed ones as specified by NVidia's original patch.
Signed-off-by: Prakash Punnoor <[email protected]>
--- drivers/pci/quirks.c.current 2009-03-01 08:42:31.321660493 +0100
+++ drivers/pci/quirks.c 2009-03-01 08:47:47.267657376 +0100
@@ -2189,8 +2189,20 @@
return __nv_msi_ht_cap_quirk(dev, 0);
}
-/* werid?, c51/mcp51 need c51 ht msi to be enable to make mcp51 ht msi working */
+/* Enable HT MSI mapping on following host brigdes */
+/* C51 host bridges */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f0, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f1, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f2, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f3, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f4, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f5, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f6, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f7, nv_msi_ht_cap_quirk_all);
+/* MCP55 host bridge */
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0369, nv_msi_ht_cap_quirk_all);
+
+/* Enable MSI mapping on all regular devices */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Prakash Punnoor wrote:
> [PATCH] Enable HT MSI mapping on all known needed NVidia host bridges
>
> v3 of Yinghai Lu's work only enables HT MSI mapping for one specific host bridge.
> Do this also for all known needed ones as specified by NVidia's original patch.
>
> Signed-off-by: Prakash Punnoor <[email protected]>
>
> --- drivers/pci/quirks.c.current 2009-03-01 08:42:31.321660493 +0100
> +++ drivers/pci/quirks.c 2009-03-01 08:47:47.267657376 +0100
> @@ -2189,8 +2189,20 @@
> return __nv_msi_ht_cap_quirk(dev, 0);
> }
>
> -/* werid?, c51/mcp51 need c51 ht msi to be enable to make mcp51 ht msi working */
> +/* Enable HT MSI mapping on following host brigdes */
> +/* C51 host bridges */
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f0, nv_msi_ht_cap_quirk_all);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f1, nv_msi_ht_cap_quirk_all);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f2, nv_msi_ht_cap_quirk_all);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f3, nv_msi_ht_cap_quirk_all);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f4, nv_msi_ht_cap_quirk_all);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f5, nv_msi_ht_cap_quirk_all);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f6, nv_msi_ht_cap_quirk_all);
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f7, nv_msi_ht_cap_quirk_all);
> +/* MCP55 host bridge */
> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0369, nv_msi_ht_cap_quirk_all);
we may not need this one.
mcp55 is some kind of mcp51 equivent, so we dont't HT MSI for 0x0369
YH
> +
> +/* Enable MSI mapping on all regular devices */
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
>
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
[PATCH] Enable HT MSI mapping on all known needed NVidia host bridges, V2
v3 of Yinghai Lu's work only enables HT MSI mapping for one specific host bridge.
Do this also for all C51 ones as specified by NVidia's original patch.
Signed-off-by: Prakash Punnoor <[email protected]>
--- drivers/pci/quirks.c.current 2009-03-01 08:42:31.321660493 +0100
+++ drivers/pci/quirks.c 2009-03-01 09:27:13.061407474 +0100
@@ -2189,8 +2189,17 @@
return __nv_msi_ht_cap_quirk(dev, 0);
}
-/* werid?, c51/mcp51 need c51 ht msi to be enable to make mcp51 ht msi working */
+/* Enable HT MSI mapping on C51 host brigdes */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f0, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f1, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f2, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f3, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f4, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f5, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f6, nv_msi_ht_cap_quirk_all);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x02f7, nv_msi_ht_cap_quirk_all);
+
+/* Enable HT MSI mapping on all regular devices */
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Hmmm,
2.6.29-rc7 is released, but the last two patches here in the thread have not
been picked up. Why?
Regards,
Prakash
Prakash Punnoor wrote:
> Hmmm,
>
> 2.6.29-rc7 is released, but the last two patches here in the thread have not
> been picked up. Why?
>
Jesse is on vacation...
YH
On Wed, Mar 04, 2009 at 08:15:37AM +0100, Prakash Punnoor wrote:
> Hmmm,
>
> 2.6.29-rc7 is released, but the last two patches here in the thread have not
> been picked up. Why?
I'm watching the PCI tree while Jesse is away and I didn't realise these
patches were urgent to include. I'll put them in a git tree and send
Linus a pull request. I just saw him wandering around with his
suitcase, so I think he'll be back home and processing pull requests
this evening.
--
Matthew Wilcox Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours. We can't possibly take such
a retrograde step."
On Wed, Mar 04, 2009 at 08:15:37AM +0100, Prakash Punnoor wrote:
> 2.6.29-rc7 is released, but the last two patches here in the thread have not
> been picked up. Why?
Oh, I meant to say ... we're at -rc7. What is the danger here of this
fixing your machine but breaking somebody else's? Is there something we
can minimally do that fixes your machine today and then put in a patch
for 30-rc1 that is likely to fix other machines?
--
Matthew Wilcox Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours. We can't possibly take such
a retrograde step."
Matthew Wilcox wrote:
> On Wed, Mar 04, 2009 at 08:15:37AM +0100, Prakash Punnoor wrote:
>> 2.6.29-rc7 is released, but the last two patches here in the thread have not
>> been picked up. Why?
>
> Oh, I meant to say ... we're at -rc7. What is the danger here of this
> fixing your machine but breaking somebody else's? Is there something we
> can minimally do that fixes your machine today and then put in a patch
> for 30-rc1 that is likely to fix other machines?
>
please don't apply v3 and prakash patch at this point.
will have one better v4 this weekend.
YH
On Donnerstag 05 M?rz 2009 18:15:14 Matthew Wilcox wrote:
> On Wed, Mar 04, 2009 at 08:15:37AM +0100, Prakash Punnoor wrote:
> > 2.6.29-rc7 is released, but the last two patches here in the thread have
> > not been picked up. Why?
>
> Oh, I meant to say ... we're at -rc7. What is the danger here of this
> fixing your machine but breaking somebody else's?
There is a danger that less host bridges get HT MSI enabled by the quirk -
which might need it after all.
> Is there something we
> can minimally do that fixes your machine today and then put in a patch
> for 30-rc1 that is likely to fix other machines?
Something like this would be minimal and works for me:
--- drivers/pci/quirks.c.old 2009-03-06 00:34:40.996532222 +0100
+++ drivers/pci/quirks.c 2009-03-06 00:37:06.915532269 +0100
@@ -2141,6 +2141,10 @@
int pos;
int found;
+ /* Enabling HT MSI mapping on this device breaks MCP51 */
+ if (dev->device == 0x270)
+ return;
+
/* check if there is HT MSI cap or enabled on this device */
found = ht_check_msi_mapping(dev);
On Fri, Mar 06, 2009 at 12:45:12AM +0100, Prakash Punnoor wrote:
> Something like this would be minimal and works for me:
Looks appropriate for a -rc7 fix. Unless anyone argues, I'll put this
in the pci-fixes tree that I'll push out tomorrow.
--
Matthew Wilcox Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours. We can't possibly take such
a retrograde step."
please check v4:
[PATCH] pci: don't enable too much HT MSI mapping -v4
Impact: fix bug
Prakash reported that his c51-mcp51 system ondie sound card doesn't work MSI
but if he hack out the HT-MSI on mcp51, the MSI will work well with sound card.
this patch rework the nv_msi_ht_cap_quirk()
and will only try to avoid to enable ht_msi on device following that root dev,
and don't touch that root dev
v3: will enable c51...
v4: will enable c51 kind of without leaf too.
Reported-by: Prakash Punnoor <[email protected]>
Signed-off-by: Yinghai Lu <[email protected]>
---
drivers/pci/quirks.c | 116 ++++++++++++++++++++++++++++++++++++---------------
1 file changed, 83 insertions(+), 33 deletions(-)
Index: linux-2.6/drivers/pci/quirks.c
===================================================================
--- linux-2.6.orig/drivers/pci/quirks.c
+++ linux-2.6/drivers/pci/quirks.c
@@ -2053,6 +2053,65 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NV
PCI_DEVICE_ID_NVIDIA_NVENET_15,
nvenet_msi_disable);
+static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
+{
+ int pos, ttl = 48;
+ int found = 0;
+
+ /* check if there is HT MSI cap or enabled on this device */
+ pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
+ while (pos && ttl--) {
+ u8 flags;
+
+ if (found < 1)
+ found = 1;
+ if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
+ &flags) == 0) {
+ if (flags & HT_MSI_FLAGS_ENABLE) {
+ if (found < 2) {
+ found = 2;
+ break;
+ }
+ }
+ }
+ pos = pci_find_next_ht_capability(dev, pos,
+ HT_CAPTYPE_MSI_MAPPING);
+ }
+
+ return found;
+}
+
+static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
+{
+ struct pci_dev *dev;
+ int pos;
+ int i, dev_no;
+ int found = 0;
+
+ dev_no = host_bridge->devfn >> 3;
+ for (i = dev_no + 1; i < 0x20; i++) {
+ dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
+ if (!dev)
+ continue;
+
+ /* found next host bridge ?*/
+ pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
+ if (pos != 0) {
+ pci_dev_put(dev);
+ break;
+ }
+
+ if (ht_check_msi_mapping(dev)) {
+ found = 1;
+ pci_dev_put(dev);
+ break;
+ }
+ pci_dev_put(dev);
+ }
+
+ return found;
+}
+
static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
{
struct pci_dev *host_bridge;
@@ -2077,6 +2136,10 @@ static void __devinit nv_ht_enable_msi_m
if (!found)
return;
+ /* don't enable host_bridge with leaf directly here */
+ if (host_bridge == dev && host_bridge_with_leaf(host_bridge))
+ goto out;
+
/* root did that ! */
if (msi_ht_cap_enabled(host_bridge))
goto out;
@@ -2097,7 +2160,7 @@ static void __devinit ht_disable_msi_map
if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
&flags) == 0) {
- dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
+ dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
flags & ~HT_MSI_FLAGS_ENABLE);
@@ -2107,35 +2170,7 @@ static void __devinit ht_disable_msi_map
}
}
-static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
-{
- int pos, ttl = 48;
- int found = 0;
-
- /* check if there is HT MSI cap or enabled on this device */
- pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
- while (pos && ttl--) {
- u8 flags;
-
- if (found < 1)
- found = 1;
- if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
- &flags) == 0) {
- if (flags & HT_MSI_FLAGS_ENABLE) {
- if (found < 2) {
- found = 2;
- break;
- }
- }
- }
- pos = pci_find_next_ht_capability(dev, pos,
- HT_CAPTYPE_MSI_MAPPING);
- }
-
- return found;
-}
-
-static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
+static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
{
struct pci_dev *host_bridge;
int pos;
@@ -2164,7 +2199,10 @@ static void __devinit nv_msi_ht_cap_quir
/* Host bridge is to HT */
if (found == 1) {
/* it is not enabled, try to enable it */
- nv_ht_enable_msi_mapping(dev);
+ if (all)
+ ht_enable_msi_mapping(dev);
+ else
+ nv_ht_enable_msi_mapping(dev);
}
return;
}
@@ -2176,8 +2214,20 @@ static void __devinit nv_msi_ht_cap_quir
/* Host bridge is not to HT, disable HT MSI mapping on this device */
ht_disable_msi_mapping(dev);
}
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
+
+static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
+{
+ return __nv_msi_ht_cap_quirk(dev, 1);
+}
+
+static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
+{
+ return __nv_msi_ht_cap_quirk(dev, 0);
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
{
On Freitag 06 M?rz 2009 05:15:45 Yinghai Lu wrote:
> please check v4:
v4 also works for me - nice. In case v4 doesn't get merged but instead the
minimal version, this should be added also:
[patch, trivial] Fix typo in message while disabling HT MSI mapping
Signed-off-by: Prakash Punnoor <[email protected]>
--- drivers/pci/quirks.c.old 2009-03-06 00:34:40.996532222 +0100
+++ drivers/pci/quirks.c 2009-03-06 10:06:19.251037862 +0100
@@ -2097,7 +2097,7 @@
if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
&flags) == 0) {
- dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
+ dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
flags & ~HT_MSI_FLAGS_ENABLE);
Impact: fix bug
Prakash reported that his c51-mcp51 system ondie sound card doesn't work MSI
but if he hack out the HT-MSI on mcp51, the MSI will work well with sound card.
this patch rework the nv_msi_ht_cap_quirk()
and will only try to avoid to enable ht_msi on device following that root dev,
and don't touch that root dev
v3: will enable c51...
v4: will enable c51 kind of without leaf too.
v5: update to mainline
Reported-by: Prakash Punnoor <[email protected]>
Signed-off-by: Yinghai Lu <[email protected]>
---
drivers/pci/quirks.c | 118 +++++++++++++++++++++++++++++++++++----------------
1 file changed, 82 insertions(+), 36 deletions(-)
Index: linux-2.6/drivers/pci/quirks.c
===================================================================
--- linux-2.6.orig/drivers/pci/quirks.c
+++ linux-2.6/drivers/pci/quirks.c
@@ -2078,6 +2078,65 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NV
PCI_DEVICE_ID_NVIDIA_NVENET_15,
nvenet_msi_disable);
+static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
+{
+ int pos, ttl = 48;
+ int found = 0;
+
+ /* check if there is HT MSI cap or enabled on this device */
+ pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
+ while (pos && ttl--) {
+ u8 flags;
+
+ if (found < 1)
+ found = 1;
+ if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
+ &flags) == 0) {
+ if (flags & HT_MSI_FLAGS_ENABLE) {
+ if (found < 2) {
+ found = 2;
+ break;
+ }
+ }
+ }
+ pos = pci_find_next_ht_capability(dev, pos,
+ HT_CAPTYPE_MSI_MAPPING);
+ }
+
+ return found;
+}
+
+static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
+{
+ struct pci_dev *dev;
+ int pos;
+ int i, dev_no;
+ int found = 0;
+
+ dev_no = host_bridge->devfn >> 3;
+ for (i = dev_no + 1; i < 0x20; i++) {
+ dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
+ if (!dev)
+ continue;
+
+ /* found next host bridge ?*/
+ pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
+ if (pos != 0) {
+ pci_dev_put(dev);
+ break;
+ }
+
+ if (ht_check_msi_mapping(dev)) {
+ found = 1;
+ pci_dev_put(dev);
+ break;
+ }
+ pci_dev_put(dev);
+ }
+
+ return found;
+}
+
static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
{
struct pci_dev *host_bridge;
@@ -2102,6 +2161,10 @@ static void __devinit nv_ht_enable_msi_m
if (!found)
return;
+ /* don't enable host_bridge with leaf directly here */
+ if (host_bridge == dev && host_bridge_with_leaf(host_bridge))
+ goto out;
+
/* root did that ! */
if (msi_ht_cap_enabled(host_bridge))
goto out;
@@ -2132,44 +2195,12 @@ static void __devinit ht_disable_msi_map
}
}
-static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
-{
- int pos, ttl = 48;
- int found = 0;
-
- /* check if there is HT MSI cap or enabled on this device */
- pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
- while (pos && ttl--) {
- u8 flags;
-
- if (found < 1)
- found = 1;
- if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
- &flags) == 0) {
- if (flags & HT_MSI_FLAGS_ENABLE) {
- if (found < 2) {
- found = 2;
- break;
- }
- }
- }
- pos = pci_find_next_ht_capability(dev, pos,
- HT_CAPTYPE_MSI_MAPPING);
- }
-
- return found;
-}
-
-static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
+static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
{
struct pci_dev *host_bridge;
int pos;
int found;
- /* Enabling HT MSI mapping on this device breaks MCP51 */
- if (dev->device == 0x270)
- return;
-
/* check if there is HT MSI cap or enabled on this device */
found = ht_check_msi_mapping(dev);
@@ -2193,7 +2224,10 @@ static void __devinit nv_msi_ht_cap_quir
/* Host bridge is to HT */
if (found == 1) {
/* it is not enabled, try to enable it */
- nv_ht_enable_msi_mapping(dev);
+ if (all)
+ ht_enable_msi_mapping(dev);
+ else
+ nv_ht_enable_msi_mapping(dev);
}
return;
}
@@ -2205,8 +2239,20 @@ static void __devinit nv_msi_ht_cap_quir
/* Host bridge is not to HT, disable HT MSI mapping on this device */
ht_disable_msi_mapping(dev);
}
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
+
+static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
+{
+ return __nv_msi_ht_cap_quirk(dev, 1);
+}
+
+static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
+{
+ return __nv_msi_ht_cap_quirk(dev, 0);
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
{
On Fri, 20 Mar 2009 19:29:41 -0700
Yinghai Lu <[email protected]> wrote:
>
> Impact: fix bug
>
> Prakash reported that his c51-mcp51 system ondie sound card doesn't
> work MSI but if he hack out the HT-MSI on mcp51, the MSI will work
> well with sound card.
>
> this patch rework the nv_msi_ht_cap_quirk()
> and will only try to avoid to enable ht_msi on device following that
> root dev, and don't touch that root dev
>
> v3: will enable c51...
> v4: will enable c51 kind of without leaf too.
> v5: update to mainline
>
> Reported-by: Prakash Punnoor <[email protected]>
> Signed-off-by: Yinghai Lu <[email protected]>
>
Applied, thanks. Prakash if you get a chance can you try testing my
linux-next branch (or just linux-next in general tomorrow) to make sure
this is still ok for you?
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center
On Freitag 27 M?rz 2009 00:10:01 Jesse Barnes wrote:
> On Fri, 20 Mar 2009 19:29:41 -0700
>
> Yinghai Lu <[email protected]> wrote:
> > Impact: fix bug
> >
> > Prakash reported that his c51-mcp51 system ondie sound card doesn't
> > work MSI but if he hack out the HT-MSI on mcp51, the MSI will work
> > well with sound card.
> >
> > this patch rework the nv_msi_ht_cap_quirk()
> > and will only try to avoid to enable ht_msi on device following that
> > root dev, and don't touch that root dev
> >
> > v3: will enable c51...
> > v4: will enable c51 kind of without leaf too.
> > v5: update to mainline
> >
> > Reported-by: Prakash Punnoor <[email protected]>
> > Signed-off-by: Yinghai Lu <[email protected]>
>
> Applied, thanks. Prakash if you get a chance can you try testing my
> linux-next branch (or just linux-next in general tomorrow) to make sure
> this is still ok for you?
>
> Thanks,
Finally I am able to test the linux-next branch of pci tree after Jesse gave
some help with git.(Is it correct that the kernel calls itself 2.6.28-rc8? I
looked into quirks.c and it seems to be correctly patched.) Unfortunately it
doesn't seem to work for me (and I am wondering why as the old v4 version
seemed to work ontop of one of the 2.6.29-rc versions):
dmesg|grep HT
pci 0000:00:00.0: Found disabled HT MSI Mapping
pci 0000:00:03.0: Enabling HT MSI Mapping
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:0e.0: Enabling HT MSI Mapping
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:0f.0: Enabling HT MSI Mapping
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:10.0: Enabling HT MSI Mapping
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:10.1: Enabling HT MSI Mapping
Device 09.0 doesn't get enabled (good) but 00.0 also not (bad). Then my Intel
HDA cannot use MSI.
Regards,
Prakash
On Samstag 28 M?rz 2009 13:34:44 Prakash Punnoor wrote:
> On Freitag 27 M?rz 2009 00:10:01 Jesse Barnes wrote:
> > On Fri, 20 Mar 2009 19:29:41 -0700
> >
> > Yinghai Lu <[email protected]> wrote:
> > > Impact: fix bug
> > >
> > > Prakash reported that his c51-mcp51 system ondie sound card doesn't
> > > work MSI but if he hack out the HT-MSI on mcp51, the MSI will work
> > > well with sound card.
> > >
> > > this patch rework the nv_msi_ht_cap_quirk()
> > > and will only try to avoid to enable ht_msi on device following that
> > > root dev, and don't touch that root dev
> > >
> > > v3: will enable c51...
> > > v4: will enable c51 kind of without leaf too.
> > > v5: update to mainline
> > >
> > > Reported-by: Prakash Punnoor <[email protected]>
> > > Signed-off-by: Yinghai Lu <[email protected]>
> >
> > Applied, thanks. Prakash if you get a chance can you try testing my
> > linux-next branch (or just linux-next in general tomorrow) to make sure
> > this is still ok for you?
> >
> > Thanks,
>
> Finally I am able to test the linux-next branch of pci tree after Jesse
> gave some help with git.(Is it correct that the kernel calls itself
> 2.6.28-rc8? I looked into quirks.c and it seems to be correctly patched.)
> Unfortunately it doesn't seem to work for me (and I am wondering why as the
> old v4 version seemed to work ontop of one of the 2.6.29-rc versions):
>
> dmesg|grep HT
> pci 0000:00:00.0: Found disabled HT MSI Mapping
> pci 0000:00:03.0: Enabling HT MSI Mapping
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:0e.0: Enabling HT MSI Mapping
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:0f.0: Enabling HT MSI Mapping
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:10.0: Enabling HT MSI Mapping
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:10.1: Enabling HT MSI Mapping
>
> Device 09.0 doesn't get enabled (good) but 00.0 also not (bad). Then my
> Intel HDA cannot use MSI.
I sprinkeld a few debugging messages around in the code and looking at that
I don't see how the code can enable NMSI for device 00.0, but not for 09.0:
Both will exit here:
if (host_bridge == dev && host_bridge_with_leaf(host_bridge))
in nv_ht_enable_msi_mapping, so it seems host_bridge_with_leaf returns true
for both. I think because my hw configuration changed a bit (inserted one
PCIe card) comparing to last time I tested old v4 version, this doesn't work
anymore - so the leaf check alone is not realiable, I guess. For me adding
something like this, makes it work: (I hope the description makes sense, as
I am just refering to the function names and trying to guess its meanings.)
Patch is against linux-next branch of pci tree.
[patch] pci: enable MSI on host bridge without checking for leaves
On C51 the host bridge needs to be enabled, but the MCP51 host bridge not.
So don't check for leaves on the main host bridge.
Signed-off-by: Prakash Punnoor <[email protected]>
--- drivers/pci/quirks.c.old 2009-03-28 14:06:07.249250095 +0100
+++ drivers/pci/quirks.c 2009-03-28 14:22:35.027510230 +0100
@@ -2292,8 +2292,10 @@ static void __devinit __nv_msi_ht_cap_qu
if (pos != 0) {
/* Host bridge is to HT */
if (found == 1) {
- /* it is not enabled, try to enable it */
- if (all)
+ /* it is not enabled, try to enable it;
+ * don't check for leaves on host bridge
+ */
+ if (all || host_bridge->devfn == dev->devfn)
ht_enable_msi_mapping(dev);
else
nv_ht_enable_msi_mapping(dev);
Prakash Punnoor wrote:
> On Samstag 28 M?rz 2009 13:34:44 Prakash Punnoor wrote:
>> On Freitag 27 M?rz 2009 00:10:01 Jesse Barnes wrote:
>>> On Fri, 20 Mar 2009 19:29:41 -0700
>>>
>>> Yinghai Lu <[email protected]> wrote:
>>>> Impact: fix bug
>>>>
>>>> Prakash reported that his c51-mcp51 system ondie sound card doesn't
>>>> work MSI but if he hack out the HT-MSI on mcp51, the MSI will work
>>>> well with sound card.
>>>>
>>>> this patch rework the nv_msi_ht_cap_quirk()
>>>> and will only try to avoid to enable ht_msi on device following that
>>>> root dev, and don't touch that root dev
>>>>
>>>> v3: will enable c51...
>>>> v4: will enable c51 kind of without leaf too.
>>>> v5: update to mainline
>>>>
>>>> Reported-by: Prakash Punnoor <[email protected]>
>>>> Signed-off-by: Yinghai Lu <[email protected]>
>>> Applied, thanks. Prakash if you get a chance can you try testing my
>>> linux-next branch (or just linux-next in general tomorrow) to make sure
>>> this is still ok for you?
>>>
>>> Thanks,
>> Finally I am able to test the linux-next branch of pci tree after Jesse
>> gave some help with git.(Is it correct that the kernel calls itself
>> 2.6.28-rc8? I looked into quirks.c and it seems to be correctly patched.)
>> Unfortunately it doesn't seem to work for me (and I am wondering why as the
>> old v4 version seemed to work ontop of one of the 2.6.29-rc versions):
>>
>> dmesg|grep HT
>> pci 0000:00:00.0: Found disabled HT MSI Mapping
>> pci 0000:00:03.0: Enabling HT MSI Mapping
>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> pci 0000:00:0e.0: Enabling HT MSI Mapping
>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> pci 0000:00:0f.0: Enabling HT MSI Mapping
>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> pci 0000:00:10.0: Enabling HT MSI Mapping
>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> pci 0000:00:10.1: Enabling HT MSI Mapping
>>
>> Device 09.0 doesn't get enabled (good) but 00.0 also not (bad). Then my
>> Intel HDA cannot use MSI.
>
> I sprinkeld a few debugging messages around in the code and looking at that
> I don't see how the code can enable NMSI for device 00.0, but not for 09.0:
>
> Both will exit here:
>
> if (host_bridge == dev && host_bridge_with_leaf(host_bridge))
>
> in nv_ht_enable_msi_mapping, so it seems host_bridge_with_leaf returns true
> for both. I think because my hw configuration changed a bit (inserted one
> PCIe card) comparing to last time I tested old v4 version, this doesn't work
> anymore - so the leaf check alone is not realiable, I guess. For me adding
> something like this, makes it work: (I hope the description makes sense, as
> I am just refering to the function names and trying to guess its meanings.)
>
> Patch is against linux-next branch of pci tree.
>
> [patch] pci: enable MSI on host bridge without checking for leaves
>
> On C51 the host bridge needs to be enabled, but the MCP51 host bridge not.
> So don't check for leaves on the main host bridge.
>
> Signed-off-by: Prakash Punnoor <[email protected]>
>
> --- drivers/pci/quirks.c.old 2009-03-28 14:06:07.249250095 +0100
> +++ drivers/pci/quirks.c 2009-03-28 14:22:35.027510230 +0100
> @@ -2292,8 +2292,10 @@ static void __devinit __nv_msi_ht_cap_qu
> if (pos != 0) {
> /* Host bridge is to HT */
> if (found == 1) {
> - /* it is not enabled, try to enable it */
> - if (all)
> + /* it is not enabled, try to enable it;
> + * don't check for leaves on host bridge
> + */
> + if (all || host_bridge->devfn == dev->devfn)
> ht_enable_msi_mapping(dev);
> else
> nv_ht_enable_msi_mapping(dev);
>
seems it is not right, it may enable your 09.0 again.
YH
On Sat, Mar 28, 2009 at 6:31 AM, Prakash Punnoor <[email protected]> wrote:
> On Samstag 28 M?rz 2009 13:34:44 Prakash Punnoor wrote:
>> On Freitag 27 M?rz 2009 00:10:01 Jesse Barnes wrote:
>> > On Fri, 20 Mar 2009 19:29:41 -0700
>> >
>> > Yinghai Lu <[email protected]> wrote:
>> > > Impact: fix bug
>> > >
>> > > Prakash reported that his c51-mcp51 system ondie sound card doesn't
>> > > work MSI but if he hack out the HT-MSI on mcp51, the MSI will work
>> > > well with sound card.
>> > >
>> > > this patch rework the nv_msi_ht_cap_quirk()
>> > > and will only try to avoid to enable ht_msi on device following that
>> > > root dev, and don't touch that root dev
>> > >
>> > > v3: will enable c51...
>> > > v4: will enable c51 kind of without leaf too.
>> > > v5: update to mainline
>> > >
>> > > Reported-by: Prakash Punnoor <[email protected]>
>> > > Signed-off-by: Yinghai Lu <[email protected]>
>> >
>> > Applied, thanks. ?Prakash if you get a chance can you try testing my
>> > linux-next branch (or just linux-next in general tomorrow) to make sure
>> > this is still ok for you?
>> >
>> > Thanks,
>>
>> Finally I am able to test the linux-next branch of pci tree after Jesse
>> gave some help with git.(Is it correct that the kernel calls itself
>> 2.6.28-rc8? I looked into quirks.c and it seems to be correctly patched.)
>> Unfortunately it doesn't seem to work for me (and I am wondering why as the
>> old v4 version seemed to work ontop of one of the 2.6.29-rc versions):
>>
>> dmesg|grep HT
>> pci 0000:00:00.0: Found disabled HT MSI Mapping
>> pci 0000:00:03.0: Enabling HT MSI Mapping
>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> pci 0000:00:0e.0: Enabling HT MSI Mapping
>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> pci 0000:00:0f.0: Enabling HT MSI Mapping
>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> pci 0000:00:10.0: Enabling HT MSI Mapping
>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> pci 0000:00:10.1: Enabling HT MSI Mapping
>>
>> Device 09.0 doesn't get enabled (good) but 00.0 also not (bad). Then my
>> Intel HDA cannot use MSI.
>
> I sprinkeld a few debugging messages around in the code and looking at that
> I don't see how the code can enable NMSI for device 00.0, but not for 09.0:
>
> Both will exit here:
>
> if (host_bridge == dev && host_bridge_with_leaf(host_bridge))
>
where is
0000:00:03.0: Enabling HT MSI Mapping
from?
last time you report:
A full lspci listing:
00:00.0 RAM memory: nVidia Corporation C51 Host Bridge (rev a2)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0
Capabilities: [44] HyperTransport: Slave or Primary Interface
Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL-
Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn-
LSEn- ExtCTL- 64b-
Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn-
LWO=16bit DwFcOutEn-
Link Control 1: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn-
LSEn+ ExtCTL- 64b-
Link Config 1: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn-
LWO=8bit DwFcOutEn-
Revision ID: 1.03
Link Frequency 0: 1.0GHz
Link Error 0: <Prot- <Ovfl- <EOC- CTLTm-
Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+
1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend-
Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD-
Link Frequency 1: 800MHz
Link Error 1: <Prot- <Ovfl- <EOC- CTLTm-
Link Frequency Capability 1: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+
1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend-
Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE-
PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE-
Prefetchable memory behind bridge Upper: 00-00
Bus Number: 00
Capabilities: [e0] HyperTransport: MSI Mapping Enable+ Fixed-
Mapping Address Base: 00000000fee00000
00: de 10 f0 02 06 00 b0 00 a2 00 00 05 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00
40: 43 10 c0 81 08 e0 e0 01 22 00 11 11 22 20 11 00
50: 23 06 7f 80 03 05 7f 80 00 00 03 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 06 15 05 00
70: 44 44 41 00 d0 09 00 00 11 00 00 00 11 11 88 00
80: 23 99 88 00 1f 00 64 0c 03 00 00 00 7f 00 00 00
90: 70 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 61 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 08 00 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 10
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:00.1 RAM memory: nVidia Corporation C51 Memory Controller 0 (rev a2)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR+ FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR+ <PERR- INTx-
00: de 10 fa 02 00 01 20 40 a2 00 00 05 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 10 00 21 21 14 00 11 11 00 00 03 00 00 00
60: 21 88 13 02 de 8f e1 1f 08 72 4e 10 02 3f 00 20
70: 10 32 54 0a 10 00 00 00 a0 00 00 00 34 00 31 01
80: 00 00 00 00 00 00 00 00 00 00 50 3f 90 3f 00 00
90: 00 28 00 fe fd 00 00 00 fc ff ff ff ff 03 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 28 00 fe fd 01 01 a0 01 4f 00 00 80 f9 fd 00
e0: 00 00 c9 fe 00 00 00 00 00 fc ff ff 00 00 00 00
f0: 00 00 00 00 c7 02 32 00 00 00 00 00 00 00 00 00
00:00.2 RAM memory: nVidia Corporation C51 Memory Controller 1 (rev a2)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
00: de 10 fe 02 00 00 20 00 a2 00 00 05 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 43 10 c0 81 1f 20 1c 20 1f 20 c0 21 00 00 00 00
50: 36 00 38 c9 01 00 00 00 3b 00 3d c9 02 1f 1c 80
60: 02 1f 1c 00 00 00 00 00 02 10 1c a0 02 0c 1c 90
70: 02 10 1c 90 02 14 1c 90 02 0c 1c 80 02 10 1c 80
80: 02 14 1c 80 02 18 1c 80 02 1c 1c 80 01 10 1c 80
90: 02 14 1c 80 11 00 11 00 32 01 00 00 00 00 00 00
a0: c2 00 40 01 10 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 41 23 05 08
c0: fd ff ff ff ff ff ff ff 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:00.3 RAM memory: nVidia Corporation C51 Memory Controller 5 (rev a2)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
00: de 10 f8 02 00 00 a0 00 a2 00 00 05 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00
40: 43 10 c0 81 00 00 00 00 02 10 1c 80 02 10 1c a0
50: 02 0c 1c 90 02 10 1c 90 02 14 1c 90 02 0c 1c 80
60: 02 10 1c 80 02 14 1c 80 02 18 1c 80 02 1c 1c 80
70: 01 10 1c 80 1f 20 c0 81 00 00 00 00 3e 30 40 c9
80: 01 00 00 00 44 30 46 c9 02 1f 1c 80 70 20 00 40
90: 89 da 01 09 00 00 00 00 11 00 10 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 08 00 00 00 18 1a 00 00 10 00 02 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 0f 01 00 05 00 00 00 00
d0: 00 00 f0 03 00 04 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 60 ea 10 10 18 00 00 20 00 00 00 00 00 00 00 00
00:00.4 RAM memory: nVidia Corporation C51 Memory Controller 4 (rev a2)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0
00: de 10 f9 02 06 00 a0 00 a2 00 00 05 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00
40: ef dd 7b 2f f7 de 7b 2f f7 de 7b 2f f7 02 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00
70: 0a 00 00 00 03 00 00 00 25 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 05 00 00 00 04 00 00 00
90: 03 04 00 00 01 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: ff 7f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:00.5 RAM memory: nVidia Corporation C51 Host Bridge (rev a2)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0
Capabilities: [44] #00 [00fe]
Capabilities: [fc] #00 [0000]
00: de 10 ff 02 06 00 b0 00 a2 00 00 05 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00
40: 17 00 00 00 00 fe fe 00 00 fe fe 00 00 fe fe 00
50: 00 fe fe 00 00 fe fe 00 00 fe fe 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:00.6 RAM memory: nVidia Corporation C51 Memory Controller 3 (rev a2)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR+ FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
00: de 10 7f 02 02 01 20 00 a2 00 00 05 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 08 00 00 00 00 00 00 00 00 80 cb fe 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:00.7 RAM memory: nVidia Corporation C51 Memory Controller 2 (rev a2)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
00: de 10 7e 02 00 00 20 00 a2 00 00 05 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 43 10 c0 81 11 00 00 00 75 07 00 00 11 00 00 00
50: 75 06 00 00 40 00 60 00 40 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 04
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00 04
b0: ff ff 03 00 10 11 00 00 ac 10 20 00 30 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:05.0 VGA compatible controller: nVidia Corporation C51PV [GeForce 6150]
(rev a2) (prog-if 00 [VGA controller])
Subsystem: ASUSTeK Computer Inc. A8N-VM CSM
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0
Interrupt: pin A routed to IRQ 16
Region 0: Memory at fc000000 (32-bit, non-prefetchable) [size=16M]
Region 1: Memory at d0000000 (64-bit, prefetchable) [size=256M]
Region 3: Memory at fb000000 (64-bit, non-prefetchable) [size=16M]
[virtual] Expansion ROM at f0000000 [disabled] [size=128K]
Capabilities: [48] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Mask- 64bit+ Count=1/1 Enable-
Address: 0000000000000000 Data: 0000
Kernel driver in use: nvidia
Kernel modules: nvidia
00: de 10 40 02 07 00 b0 00 a2 00 00 03 00 00 00 00
10: 00 00 00 fc 0c 00 00 d0 00 00 00 00 04 00 00 fb
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 cd 81
30: 00 00 00 00 48 00 00 00 00 00 00 00 05 01 00 00
40: 43 10 cd 81 00 00 00 00 01 50 02 00 00 00 00 00
50: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 01 00 00 00 04 00 00 00 00 00 00 00 01 00 00 00
70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
a0: 00 00 90 01 00 00 00 08 00 00 00 00 ff ff ff ff
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
00:09.0 RAM memory: nVidia Corporation MCP51 Host Bridge (rev a2)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0
Capabilities: [44] HyperTransport: Slave or Primary Interface
Command: BaseUnitID=9 UnitCnt=15 MastHost- DefDir- DUL-
Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn-
LSEn+ ExtCTL- 64b-
Link Config 0: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn-
LWO=8bit DwFcOutEn-
Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn-
LSEn- ExtCTL- 64b-
Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn-
LWO=8bit DwFcOutEn-
Revision ID: 1.03
Link Frequency 0: 800MHz
Link Error 0: <Prot- <Ovfl- <EOC- CTLTm-
Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+
1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend-
Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD-
Link Frequency 1: 200MHz
Link Error 1: <Prot- <Ovfl- <EOC- CTLTm-
Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz-
1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend-
Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE-
PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE-
Prefetchable memory behind bridge Upper: 00-00
Bus Number: 00
Capabilities: [e0] HyperTransport: MSI Mapping Enable- Fixed-
Mapping Address Base: 00000000fee00000
00: de 10 70 02 06 00 b0 00 a2 00 00 05 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 00 00
40: 43 10 c0 81 08 e0 e9 01 22 20 00 00 d0 00 00 00
50: 23 05 7f 80 03 00 00 00 00 00 03 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 06 15 05 00
70: 44 44 44 00 d0 09 00 00 11 00 00 00 11 11 55 00
80: 23 55 55 00 fa 00 64 0c 03 00 00 00 7f 00 00 00
90: 70 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 08 00 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:0a.0 ISA bridge: nVidia Corporation MCP51 LPC Bridge (rev a3)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0
00: de 10 60 02 0f 00 a0 00 a3 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00
40: 43 10 c0 81 00 f0 ff fe fa 3e ff 00 fa 3e ff 00
50: fa 3e ff 00 00 5a 62 02 00 00 00 01 00 00 ff ff
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f9 ff
70: 10 00 ff ff c5 00 00 00 00 00 05 19 00 00 00 03
80: 09 80 00 2d 01 21 00 00 c0 00 00 01 00 00 00 00
90: 00 00 00 00 00 00 00 00 21 47 65 b7 ef cd 00 00
a0: 03 00 10 c1 00 00 00 00 00 00 00 00 00 00 00 00
b0: 90 02 ef 02 00 08 5f 08 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00
00:0a.1 SMBus: nVidia Corporation MCP51 SMBus (rev a3)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 255
Region 4: I/O ports at 4c00 [size=64]
Region 5: I/O ports at 4c40 [size=64]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: de 10 64 02 01 00 b0 00 a3 00 05 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 4c 00 00 41 4c 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 01 00 00
40: 43 10 c0 81 01 00 02 c0 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 01 40 00 00 01 44 00 00 01 48 00 00 00 00 00 00
70: 01 00 00 00 00 00 c8 fe 00 00 fe fe 01 20 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: d4 30 80 01 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 10 10 04 00 00 a0 00 00 80 30 00 00 41 44 44 11
f0: 5a ff 5f bf 00 00 00 c0 10 00 00 00 00 00 00 00
00:0a.2 RAM memory: nVidia Corporation MCP51 Memory Controller 0 (rev a3)
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx+
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
00: de 10 72 02 00 04 a0 00 a3 00 00 05 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 10 00 00 10 00 00 10 10
50: 10 10 10 10 00 00 00 00 00 00 00 00 00 00 00 00
60: 02 03 00 00 12 00 00 00 02 00 00 00 10 01 12 00
70: 32 33 00 00 03 00 00 00 00 00 00 00 12 01 00 00
80: 10 00 00 00 00 00 00 00 00 00 00 00 30 02 00 00
90: 00 00 00 00 01 20 00 00 01 00 00 00 00 09 00 00
a0: 01 02 00 00 00 10 00 00 05 00 00 00 01 00 00 00
b0: 00 10 00 80 01 00 00 80 00 00 00 00 02 00 00 00
c0: 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:0b.0 USB Controller: nVidia Corporation MCP51 USB Controller (rev a3)
(prog-if 10 [OHCI])
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0 (750ns min, 250ns max)
Interrupt: pin A routed to IRQ 23
Region 0: Memory at fe02f000 (32-bit, non-prefetchable) [size=4K]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Kernel driver in use: ohci_hcd
00: de 10 6d 02 07 00 b0 00 a3 10 03 0c 00 00 80 00
10: 00 f0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 01 03 01
40: 43 10 c0 81 01 00 02 fe 00 00 00 00 00 00 00 00
50: 00 00 00 00 1d 47 40 00 10 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:0b.1 USB Controller: nVidia Corporation MCP51 USB Controller (rev a3)
(prog-if 20 [EHCI])
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0 (750ns min, 250ns max)
Interrupt: pin B routed to IRQ 20
Region 0: Memory at fe02e000 (32-bit, non-prefetchable) [size=256]
Capabilities: [44] Debug port: BAR=1 offset=0098
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Kernel driver in use: ehci_hcd
00: de 10 6e 02 06 00 b0 00 a3 20 03 0c 00 00 80 00
10: 00 e0 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 c0 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 02 03 01
40: 43 10 c0 81 0a 80 98 20 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 20 20 01 00 00 60 18 85 03 3c 0a 01 00 00 00 00
70: 00 00 08 05 00 10 20 80 89 3d b6 22 77 25 64 00
80: 01 00 02 fe 00 00 00 00 00 00 00 00 15 16 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00
b0: 00 11 22 33 00 00 00 00 ff 00 00 00 00 00 00 00
c0: 10 10 2d 0d 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00
00:0d.0 IDE interface: nVidia Corporation MCP51 IDE (rev a1) (prog-if 8a
[Master SecP PriP])
Subsystem: Device f043:81c0
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0 (750ns min, 250ns max)
Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8]
Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1]
Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8]
Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1]
Region 4: I/O ports at f400 [size=16]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Kernel driver in use: pata_amd
00: de 10 65 02 05 00 b0 00 a1 8a 01 01 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 f4 00 00 00 00 00 00 00 00 00 00 43 f0 c0 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01
40: 43 f0 c0 81 01 00 02 00 00 00 00 00 00 00 00 00
50: 03 f0 01 00 00 00 00 00 99 99 99 20 2a 00 a8 20
60: 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 90 20 21 00 00 02 10 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00
00:0e.0 IDE interface: nVidia Corporation MCP51 Serial ATA Controller (rev a1)
(prog-if 85 [Master SecO PriO])
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0 (750ns min, 250ns max)
Interrupt: pin A routed to IRQ 22
Region 0: I/O ports at 09f0 [size=8]
Region 1: I/O ports at 0bf0 [size=4]
Region 2: I/O ports at 0970 [size=8]
Region 3: I/O ports at 0b70 [size=4]
Region 4: I/O ports at e000 [size=16]
Region 5: Memory at fe02d000 (32-bit, non-prefetchable) [size=4K]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [b0] MSI: Mask- 64bit+ Count=1/4 Enable-
Address: 0000000000000000 Data: 0000
Capabilities: [cc] HyperTransport: MSI Mapping Enable+ Fixed+
Kernel driver in use: sata_nv
00: de 10 66 02 07 00 b0 00 a1 85 01 01 00 00 00 00
10: f1 09 00 00 f1 0b 00 00 71 09 00 00 71 0b 00 00
20: 01 e0 00 00 00 d0 02 fe 00 00 00 00 43 10 c0 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 03 01
40: 43 10 c0 81 01 b0 02 00 00 00 00 00 00 00 00 00
50: 07 00 00 00 00 00 00 00 a8 a8 a8 20 6a 00 99 20
60: 00 00 00 c0 51 0c 00 00 00 0f 06 42 00 00 00 00
70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 00
80: 00 00 00 c0 00 50 36 22 00 00 08 80 9e f7 2d 3b
90: 00 00 58 1b 00 00 00 00 06 00 06 10 00 00 01 01
a0: 14 10 00 2a 00 00 00 00 00 00 00 00 33 33 00 02
b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 03 a8
d0: 01 00 02 6b 42 00 00 00 00 00 00 00 00 00 00 e0
e0: 01 00 02 6b 42 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 0c 00 00 00 00 00
00:0f.0 IDE interface: nVidia Corporation MCP51 Serial ATA Controller (rev a1)
(prog-if 85 [Master SecO PriO])
Subsystem: ASUSTeK Computer Inc. Device 81c0
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0 (750ns min, 250ns max)
Interrupt: pin A routed to IRQ 21
Region 0: I/O ports at 09e0 [size=8]
Region 1: I/O ports at 0be0 [size=4]
Region 2: I/O ports at 0960 [size=8]
Region 3: I/O ports at 0b60 [size=4]
Region 4: I/O ports at cc00 [size=16]
Region 5: Memory at fe02c000 (32-bit, non-prefetchable) [size=4K]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [b0] MSI: Mask- 64bit+ Count=1/4 Enable-
Address: 0000000000000000 Data: 0000
Capabilities: [cc] HyperTransport: MSI Mapping Enable+ Fixed+
Kernel driver in use: sata_nv
00: de 10 67 02 07 00 b0 00 a1 85 01 01 00 00 00 00
10: e1 09 00 00 e1 0b 00 00 61 09 00 00 61 0b 00 00
20: 01 cc 00 00 00 c0 02 fe 00 00 00 00 43 10 c0 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 03 01
40: 43 10 c0 81 01 b0 02 00 00 00 00 00 00 00 00 00
50: 07 00 00 00 00 00 00 00 a8 a8 a8 20 6a 00 99 20
60: 00 00 00 c0 51 0c 00 00 00 0f 06 42 00 00 00 00
70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 00
80: 00 00 00 c0 db 46 60 f0 00 00 c6 2c ad 4c f4 fa
90: 00 00 15 20 00 00 00 00 06 00 06 10 00 00 01 01
a0: 14 10 00 00 00 00 00 00 00 00 00 00 33 33 00 02
b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 03 a8
d0: 01 00 02 6b 42 00 00 00 00 00 00 00 90 00 00 00
e0: 01 00 02 6b 42 00 00 00 00 00 00 00 0e 00 f0 07
f0: 00 00 00 00 00 00 00 00 00 00 0c 00 00 00 00 00
00:10.0 PCI bridge: nVidia Corporation MCP51 PCI Bridge (rev a2) (prog-if 01
[Subtractive decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0
Bus: primary=00, secondary=01, subordinate=01, sec-latency=128
I/O behind bridge: 0000b000-0000bfff
Memory behind bridge: fdd00000-fddfffff
Prefetchable memory behind bridge: fde00000-fdefffff
Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort-
<MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn-
Capabilities: [b8] Subsystem: Gammagraphx, Inc. (or missing ID) Device 0000
Capabilities: [8c] HyperTransport: MSI Mapping Enable+ Fixed-
Mapping Address Base: 00000000fee00000
00: de 10 6f 02 07 00 b0 00 a2 01 04 06 00 00 81 00
10: 00 00 00 00 00 00 00 00 00 01 01 80 b0 b0 80 02
20: d0 fd d0 fd e0 fd e0 fd 00 00 00 00 00 00 00 00
30: 00 00 00 00 b8 00 00 00 00 00 00 00 ff 00 04 02
40: 00 00 03 00 01 00 02 00 07 00 00 00 00 00 44 00
50: 00 00 fe cf 00 00 00 00 ff 1f ff 1f 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 01 a8
90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00
a0: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 ff ff 00 00 0d 8c 00 00 00 00 00 00
c0: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:10.1 Audio device: nVidia Corporation MCP51 High Definition Audio (rev a2)
Subsystem: ASUSTeK Computer Inc. Device 81cb
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0 (500ns min, 1250ns max)
Interrupt: pin B routed to IRQ 24
Region 0: Memory at fe024000 (32-bit, non-prefetchable) [size=16K]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Mask+ 64bit+ Count=1/1 Enable+
Address: 00000000fee0300c Data: 4169
Masking: 00000000 Pending: 00000000
Capabilities: [6c] HyperTransport: MSI Mapping Enable+ Fixed+
Kernel driver in use: HDA Intel
00: de 10 6c 02 06 04 b0 00 a2 00 03 04 00 00 80 00
10: 00 40 02 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 cb 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 02 02 05
40: 43 10 cb 81 01 50 02 c0 00 00 00 00 01 01 0f 00
50: 05 6c 81 01 0c 30 e0 fe 00 00 00 00 69 41 00 00
60: 00 00 00 00 00 00 00 00 0f 00 00 00 08 00 03 a8
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 46 00 29 00 00 00 00 00 00
00:14.0 Bridge: nVidia Corporation MCP51 Ethernet Controller (rev a3)
Subsystem: ASUSTeK Computer Inc. Device 816a
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0 (250ns min, 5000ns max)
Interrupt: pin A routed to IRQ 23
Region 0: Memory at fe02b000 (32-bit, non-prefetchable) [size=4K]
Region 1: I/O ports at c800 [size=8]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable+ DSel=0 DScale=0 PME-
Kernel driver in use: forcedeth
00: de 10 69 02 07 00 b0 00 a3 00 80 06 00 00 00 00
10: 00 b0 02 fe 01 c8 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 6a 81
30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 01 14
40: 43 10 6a 81 01 00 02 fe 00 01 00 00 0b 00 00 10
50: 05 6c 84 01 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 0f 00 00 00 08 00 02 a8
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 11 00 00 00 42 01 00 00 00 00 00 00
00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
HyperTransport Technology Configuration
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Capabilities: [80] HyperTransport: Host or Secondary Interface
Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL-
Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn-
LSEn- ExtCTL- 64b-
Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn-
LWO=16bit DwFcOutEn-
Revision ID: 1.02
Link Frequency: 1.0GHz
Link Error: <Prot- <Ovfl- <EOC- CTLTm-
Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+
1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend-
Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE-
00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
40: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00
60: 00 00 01 00 e4 00 00 00 20 c8 20 0f 0c 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 08 00 01 21 20 00 11 11 22 06 75 80 02 00 00 00
90: 69 01 61 01 00 00 01 00 07 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
Address Map
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 03 00 00 00 00 00 2f 01 00 00 00 00 01 00 00 00
50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00
60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00
70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00
80: 03 0a 00 00 00 0b 00 00 00 00 00 00 00 00 00 00
90: 03 00 d0 00 00 ff df 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 03 00 f0 00 00 02 fe 00
b0: 03 00 e0 00 80 1f e0 00 00 00 00 00 00 00 00 00
c0: 13 b0 00 00 00 f0 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 03 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00
f0: 01 30 00 d0 00 00 00 00 00 00 00 00 00 00 00 00
00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM
Controller
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 00 00 00 01 02 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: e0 3d f8 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 46 00 00 00 00 00 00 00
80: 05 00 00 00 00 00 00 00 24 f2 7d 0c 20 13 22 00
90: 10 0c 01 00 5b 80 10 77 24 00 00 80 20 25 2b 00
a0: ef 02 00 0c 00 00 00 00 00 00 00 00 00 00 00 00
b0: a4 1e 87 29 88 00 00 00 b4 35 61 00 ea bf 0f 1f
c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 61 90 8c 27 00 14 48 00 48 ac 1a 0b 94 fe 81 99
e0: 7d 99 f5 b3 d9 3e 80 04 03 f2 93 16 fa b7 fb a5
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
Miscellaneous Control
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Capabilities: [f0] Secure device <?>
00: 22 10 03 11 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00
40: 00 01 00 00 40 00 10 0a 00 00 00 00 00 00 00 00
50: 80 e4 a8 85 19 00 00 00 00 00 00 00 00 00 26 08
60: 4a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 11 01 32 51 21 40 70 50 00 2a 00 08 17 21 00 00
80: 00 00 07 23 13 21 13 21 00 00 00 00 00 00 00 00
90: 03 00 00 00 10 00 00 00 00 ac 2f 01 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 30 35 22
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 01 a7 0d 00 00 00 c0 08 26 26 26 00
e0: 00 00 00 00 20 1a 52 00 19 17 00 00 00 00 00 00
f0: 0f 00 10 00 00 00 00 00 00 00 00 00 b2 0f 04 00
01:05.0 FireWire (IEEE 1394): Texas Instruments TSB43AB22/A IEEE-1394a-2000
Controller (PHY/Link) (prog-if 10 [OHCI])
Subsystem: ASUSTeK Computer Inc. K8N4-E Mainboard
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping-
SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 32 (500ns min, 1000ns max), Cache Line Size: 32 bytes
Interrupt: pin A routed to IRQ 255
Region 0: Memory at fddff000 (32-bit, non-prefetchable) [size=2K]
Region 1: Memory at fddf8000 (32-bit, non-prefetchable) [size=16K]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 4c 10 23 80 06 00 10 02 00 10 00 0c 08 20 00 00
10: 00 f0 df fd 00 80 df fd 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 8b 80
30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 01 02 04
40: 00 00 00 00 01 00 02 7e 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 88 00 00 00
f0: 10 00 00 00 82 10 00 00 43 10 8b 80 00 00 01 01
On Samstag 28 M?rz 2009 21:18:19 Yinghai Lu wrote:
> Prakash Punnoor wrote:
> > On Samstag 28 M?rz 2009 13:34:44 Prakash Punnoor wrote:
> >> On Freitag 27 M?rz 2009 00:10:01 Jesse Barnes wrote:
> >>> On Fri, 20 Mar 2009 19:29:41 -0700
> >>>
> >>> Yinghai Lu <[email protected]> wrote:
> >>>> Impact: fix bug
> >>>>
> >>>> Prakash reported that his c51-mcp51 system ondie sound card doesn't
> >>>> work MSI but if he hack out the HT-MSI on mcp51, the MSI will work
> >>>> well with sound card.
> >>>>
> >>>> this patch rework the nv_msi_ht_cap_quirk()
> >>>> and will only try to avoid to enable ht_msi on device following that
> >>>> root dev, and don't touch that root dev
> >>>>
> >>>> v3: will enable c51...
> >>>> v4: will enable c51 kind of without leaf too.
> >>>> v5: update to mainline
> >>>>
> >>>> Reported-by: Prakash Punnoor <[email protected]>
> >>>> Signed-off-by: Yinghai Lu <[email protected]>
> >>>
> >>> Applied, thanks. Prakash if you get a chance can you try testing my
> >>> linux-next branch (or just linux-next in general tomorrow) to make sure
> >>> this is still ok for you?
> >>>
> >>> Thanks,
> >>
> >> Finally I am able to test the linux-next branch of pci tree after Jesse
> >> gave some help with git.(Is it correct that the kernel calls itself
> >> 2.6.28-rc8? I looked into quirks.c and it seems to be correctly
> >> patched.) Unfortunately it doesn't seem to work for me (and I am
> >> wondering why as the old v4 version seemed to work ontop of one of the
> >> 2.6.29-rc versions):
> >>
> >> dmesg|grep HT
> >> pci 0000:00:00.0: Found disabled HT MSI Mapping
> >> pci 0000:00:03.0: Enabling HT MSI Mapping
> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
> >> pci 0000:00:0e.0: Enabling HT MSI Mapping
> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
> >> pci 0000:00:0f.0: Enabling HT MSI Mapping
> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
> >> pci 0000:00:10.0: Enabling HT MSI Mapping
> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
> >> pci 0000:00:10.1: Enabling HT MSI Mapping
> >>
> >> Device 09.0 doesn't get enabled (good) but 00.0 also not (bad). Then my
> >> Intel HDA cannot use MSI.
> >
> > I sprinkeld a few debugging messages around in the code and looking at
> > that I don't see how the code can enable NMSI for device 00.0, but not
> > for 09.0:
> >
> > Both will exit here:
> >
> > if (host_bridge == dev && host_bridge_with_leaf(host_bridge))
> >
> > in nv_ht_enable_msi_mapping, so it seems host_bridge_with_leaf returns
> > true for both. I think because my hw configuration changed a bit
> > (inserted one PCIe card) comparing to last time I tested old v4 version,
> > this doesn't work anymore - so the leaf check alone is not realiable, I
> > guess. For me adding something like this, makes it work: (I hope the
> > description makes sense, as I am just refering to the function names and
> > trying to guess its meanings.)
> >
> > Patch is against linux-next branch of pci tree.
> >
> > [patch] pci: enable MSI on host bridge without checking for leaves
> >
> > On C51 the host bridge needs to be enabled, but the MCP51 host bridge
> > not. So don't check for leaves on the main host bridge.
> >
> > Signed-off-by: Prakash Punnoor <[email protected]>
> >
> > --- drivers/pci/quirks.c.old 2009-03-28 14:06:07.249250095 +0100
> > +++ drivers/pci/quirks.c 2009-03-28 14:22:35.027510230 +0100
> > @@ -2292,8 +2292,10 @@ static void __devinit __nv_msi_ht_cap_qu
> > if (pos != 0) {
> > /* Host bridge is to HT */
> > if (found == 1) {
> > - /* it is not enabled, try to enable it */
> > - if (all)
> > + /* it is not enabled, try to enable it;
> > + * don't check for leaves on host bridge
> > + */
> > + if (all || host_bridge->devfn == dev->devfn)
> > ht_enable_msi_mapping(dev);
> > else
> > nv_ht_enable_msi_mapping(dev);
>
> seems it is not right, it may enable your 09.0 again.
No if you look into the whole function, you'll see that host_bridge is device
0:0. ( host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); )
On Samstag 28 M?rz 2009 21:52:45 Yinghai Lu wrote:
> On Sat, Mar 28, 2009 at 6:31 AM, Prakash Punnoor <[email protected]> wrote:
> > On Samstag 28 M?rz 2009 13:34:44 Prakash Punnoor wrote:
> >> On Freitag 27 M?rz 2009 00:10:01 Jesse Barnes wrote:
> >> > On Fri, 20 Mar 2009 19:29:41 -0700
> >> >
> >> > Yinghai Lu <[email protected]> wrote:
> >> > > Impact: fix bug
> >> > >
> >> > > Prakash reported that his c51-mcp51 system ondie sound card doesn't
> >> > > work MSI but if he hack out the HT-MSI on mcp51, the MSI will work
> >> > > well with sound card.
> >> > >
> >> > > this patch rework the nv_msi_ht_cap_quirk()
> >> > > and will only try to avoid to enable ht_msi on device following that
> >> > > root dev, and don't touch that root dev
> >> > >
> >> > > v3: will enable c51...
> >> > > v4: will enable c51 kind of without leaf too.
> >> > > v5: update to mainline
> >> > >
> >> > > Reported-by: Prakash Punnoor <[email protected]>
> >> > > Signed-off-by: Yinghai Lu <[email protected]>
> >> >
> >> > Applied, thanks. Prakash if you get a chance can you try testing my
> >> > linux-next branch (or just linux-next in general tomorrow) to make
> >> > sure this is still ok for you?
> >> >
> >> > Thanks,
> >>
> >> Finally I am able to test the linux-next branch of pci tree after Jesse
> >> gave some help with git.(Is it correct that the kernel calls itself
> >> 2.6.28-rc8? I looked into quirks.c and it seems to be correctly
> >> patched.) Unfortunately it doesn't seem to work for me (and I am
> >> wondering why as the old v4 version seemed to work ontop of one of the
> >> 2.6.29-rc versions):
> >>
> >> dmesg|grep HT
> >> pci 0000:00:00.0: Found disabled HT MSI Mapping
> >> pci 0000:00:03.0: Enabling HT MSI Mapping
> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
> >> pci 0000:00:0e.0: Enabling HT MSI Mapping
> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
> >> pci 0000:00:0f.0: Enabling HT MSI Mapping
> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
> >> pci 0000:00:10.0: Enabling HT MSI Mapping
> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
> >> pci 0000:00:10.1: Enabling HT MSI Mapping
> >>
> >> Device 09.0 doesn't get enabled (good) but 00.0 also not (bad). Then my
> >> Intel HDA cannot use MSI.
> >
> > I sprinkeld a few debugging messages around in the code and looking at
> > that I don't see how the code can enable NMSI for device 00.0, but not
> > for 09.0:
> >
> > Both will exit here:
> >
> > if (host_bridge == dev && host_bridge_with_leaf(host_bridge))
>
> where is
> 0000:00:03.0: Enabling HT MSI Mapping
> from?
As I said this time there is a PCIe device more in my system (a realtek NIC):
I guess because of that this one appeared - or I have some different drivers
loaded?
00:03.0 PCI bridge: nVidia Corporation C51 PCI Express Bridge (rev a1) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 0000a000-0000afff
Memory behind bridge: fdc00000-fdcfffff
Prefetchable memory behind bridge: 00000000fdd00000-00000000fddfffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Subsystem: nVidia Corporation Device 0000
Capabilities: [48] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Mask- 64bit+ Count=1/2 Enable+
Address: 00000000fee0300c Data: 4149
Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed-
Mapping Address Base: 00000000fee00000
Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us
ExtTag- RBE- FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us
ClockPM- Surprise- LLActRep+ BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise-
Slot # 0, PowerLimit 0.000000; Interlock- NoCompl-
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Off, PwrInd On, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet+ LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
Capabilities: [100] Virtual Channel <?>
Kernel driver in use: pcieport-driver
00: de 10 fd 02 07 04 10 00 a1 00 04 06 08 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 a1 a1 00 20
20: c0 fd c0 fd d1 fd d1 fd 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00
40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00
50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 49 41 00 00
60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 41 01 c0 04 00 00 10 28 00 00 11 3c 11 01
90: 40 00 11 30 00 00 00 00 c0 01 48 01 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
The realtek nic:
01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01)
Subsystem: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 25
Region 0: I/O ports at ac00 [size=256]
Region 2: Memory at fdcff000 (64-bit, non-prefetchable) [size=4K]
Expansion ROM at fdcc0000 [disabled] [size=128K]
Capabilities: [40] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] Vital Product Data
Unknown small resource type 05
Unknown large resource type 6c
No end tag found
Capabilities: [50] MSI: Mask- 64bit+ Count=1/2 Enable+
Address: 00000000fee0300c Data: 4161
Capabilities: [60] Express (v1) Endpoint, MSI 00
DevCap: MaxPayload 1024 bytes, PhantFunc 0, Latency L0s <1us, L1 unlimited
ExtTag+ AttnBtn+ AttnInd+ PwrInd+ RBE- FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 4096 bytes
DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited
ClockPM- Surprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
Capabilities: [84] Vendor Specific Information <?>
Capabilities: [100] Advanced Error Reporting
UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn-
Capabilities: [12c] Virtual Channel <?>
Capabilities: [148] Device Serial Number 68-81-ec-10-00-00-12-45
Capabilities: [154] Power Budgeting <?>
Kernel driver in use: r8169
00: ec 10 68 81 07 04 10 00 01 00 00 02 10 00 00 00
10: 01 ac 00 00 00 00 00 00 04 f0 cf fd 00 00 00 00
20: 00 00 00 00 00 00 00 00 02 01 00 00 ec 10 68 81
30: 00 00 cc fd 40 00 00 00 00 00 00 00 05 01 00 00
40: 01 48 c2 f7 00 00 00 00 03 50 00 00 05 df c2 f7
50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 61 41 00 00
60: 10 84 01 00 23 7f 00 00 10 58 1a 00 41 f4 03 00
70: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 09 00 4c 01 01 1c 02 00 fb ff ff 11
90: 08 30 00 00 a2 10 0a 00 67 50 08 00 c3 01 00 00
a0: 02 28 ff 01 00 00 00 00 00 08 00 00 03 00 03 00
b0: 00 00 00 00 ff 3f ff 3f ff ff 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
On Sat, Mar 28, 2009 at 3:16 PM, Prakash Punnoor <[email protected]> wrote:
> On Samstag 28 M?rz 2009 21:52:45 Yinghai Lu wrote:
>> On Sat, Mar 28, 2009 at 6:31 AM, Prakash Punnoor <[email protected]> wrote:
>> > On Samstag 28 M?rz 2009 13:34:44 Prakash Punnoor wrote:
>> >> On Freitag 27 M?rz 2009 00:10:01 Jesse Barnes wrote:
>> >> > On Fri, 20 Mar 2009 19:29:41 -0700
>> >> >
>> >> > Yinghai Lu <[email protected]> wrote:
>> >> > > Impact: fix bug
>> >> > >
>> >> > > Prakash reported that his c51-mcp51 system ondie sound card doesn't
>> >> > > work MSI but if he hack out the HT-MSI on mcp51, the MSI will work
>> >> > > well with sound card.
>> >> > >
>> >> > > this patch rework the nv_msi_ht_cap_quirk()
>> >> > > and will only try to avoid to enable ht_msi on device following that
>> >> > > root dev, and don't touch that root dev
>> >> > >
>> >> > > v3: will enable c51...
>> >> > > v4: will enable c51 kind of without leaf too.
>> >> > > v5: update to mainline
>> >> > >
>> >> > > Reported-by: Prakash Punnoor <[email protected]>
>> >> > > Signed-off-by: Yinghai Lu <[email protected]>
>> >> >
>> >> > Applied, thanks. ?Prakash if you get a chance can you try testing my
>> >> > linux-next branch (or just linux-next in general tomorrow) to make
>> >> > sure this is still ok for you?
>> >> >
>> >> > Thanks,
>> >>
>> >> Finally I am able to test the linux-next branch of pci tree after Jesse
>> >> gave some help with git.(Is it correct that the kernel calls itself
>> >> 2.6.28-rc8? I looked into quirks.c and it seems to be correctly
>> >> patched.) Unfortunately it doesn't seem to work for me (and I am
>> >> wondering why as the old v4 version seemed to work ontop of one of the
>> >> 2.6.29-rc versions):
>> >>
>> >> dmesg|grep HT
>> >> pci 0000:00:00.0: Found disabled HT MSI Mapping
>> >> pci 0000:00:03.0: Enabling HT MSI Mapping
>> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> >> pci 0000:00:0e.0: Enabling HT MSI Mapping
>> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> >> pci 0000:00:0f.0: Enabling HT MSI Mapping
>> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> >> pci 0000:00:10.0: Enabling HT MSI Mapping
>> >> pci 0000:00:09.0: Found disabled HT MSI Mapping
>> >> pci 0000:00:10.1: Enabling HT MSI Mapping
>> >>
>> >> Device 09.0 doesn't get enabled (good) but 00.0 also not (bad). Then my
>> >> Intel HDA cannot use MSI.
>> >
>> > I sprinkeld a few debugging messages around in the code and looking at
>> > that I don't see how the code can enable NMSI for device 00.0, but not
>> > for 09.0:
>> >
>> > Both will exit here:
>> >
>> > if (host_bridge == dev && host_bridge_with_leaf(host_bridge))
>>
>> where is
>> 0000:00:03.0: Enabling HT MSI Mapping
>> from?
>
> As I said this time there is a PCIe device more in my system (a realtek NIC):
> I guess because of that this one appeared - or I have some different drivers
> loaded?
>
> 00:03.0 PCI bridge: nVidia Corporation C51 PCI Express Bridge (rev a1) (prog-if 00 [Normal decode])
> ? ? ? ?Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
> ? ? ? ?Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
> ? ? ? ?Latency: 0, Cache Line Size: 32 bytes
> ? ? ? ?Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> ? ? ? ?I/O behind bridge: 0000a000-0000afff
> ? ? ? ?Memory behind bridge: fdc00000-fdcfffff
> ? ? ? ?Prefetchable memory behind bridge: 00000000fdd00000-00000000fddfffff
> ? ? ? ?Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
> ? ? ? ?BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
> ? ? ? ? ? ? ? ?PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
> ? ? ? ?Capabilities: [40] Subsystem: nVidia Corporation Device 0000
> ? ? ? ?Capabilities: [48] Power Management version 2
> ? ? ? ? ? ? ? ?Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
> ? ? ? ? ? ? ? ?Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> ? ? ? ?Capabilities: [50] MSI: Mask- 64bit+ Count=1/2 Enable+
> ? ? ? ? ? ? ? ?Address: 00000000fee0300c ?Data: 4149
> ? ? ? ?Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed-
> ? ? ? ? ? ? ? ?Mapping Address Base: 00000000fee00000
> ? ? ? ?Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00
> ? ? ? ? ? ? ? ?DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us
> ? ? ? ? ? ? ? ? ? ? ? ?ExtTag- RBE- FLReset-
> ? ? ? ? ? ? ? ?DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
> ? ? ? ? ? ? ? ? ? ? ? ?RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
> ? ? ? ? ? ? ? ? ? ? ? ?MaxPayload 128 bytes, MaxReadReq 512 bytes
> ? ? ? ? ? ? ? ?DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
> ? ? ? ? ? ? ? ?LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us
> ? ? ? ? ? ? ? ? ? ? ? ?ClockPM- Surprise- LLActRep+ BwNot-
> ? ? ? ? ? ? ? ?LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
> ? ? ? ? ? ? ? ? ? ? ? ?ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
> ? ? ? ? ? ? ? ?LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
> ? ? ? ? ? ? ? ?SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise-
> ? ? ? ? ? ? ? ? ? ? ? ?Slot # ?0, PowerLimit 0.000000; Interlock- NoCompl-
> ? ? ? ? ? ? ? ?SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
> ? ? ? ? ? ? ? ? ? ? ? ?Control: AttnInd Off, PwrInd On, Power- Interlock-
> ? ? ? ? ? ? ? ?SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
> ? ? ? ? ? ? ? ? ? ? ? ?Changed: MRL- PresDet+ LinkState+
> ? ? ? ? ? ? ? ?RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
> ? ? ? ? ? ? ? ?RootCap: CRSVisible-
> ? ? ? ? ? ? ? ?RootSta: PME ReqID 0000, PMEStatus- PMEPending-
> ? ? ? ?Capabilities: [100] Virtual Channel <?>
> ? ? ? ?Kernel driver in use: pcieport-driver
> 00: de 10 fd 02 07 04 10 00 a1 00 04 06 08 00 01 00
> 10: 00 00 00 00 00 00 00 00 00 01 01 00 a1 a1 00 20
> 20: c0 fd c0 fd d1 fd d1 fd 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00
> 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00
> 50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 49 41 00 00
> 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 10 00 41 01 c0 04 00 00 10 28 00 00 11 3c 11 01
> 90: 40 00 11 30 00 00 00 00 c0 01 48 01 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> The realtek nic:
> 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 01)
> ? ? ? ?Subsystem: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller
> ? ? ? ?Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
> ? ? ? ?Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
> ? ? ? ?Latency: 0, Cache Line Size: 64 bytes
> ? ? ? ?Interrupt: pin A routed to IRQ 25
> ? ? ? ?Region 0: I/O ports at ac00 [size=256]
> ? ? ? ?Region 2: Memory at fdcff000 (64-bit, non-prefetchable) [size=4K]
> ? ? ? ?Expansion ROM at fdcc0000 [disabled] [size=128K]
> ? ? ? ?Capabilities: [40] Power Management version 2
> ? ? ? ? ? ? ? ?Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
> ? ? ? ? ? ? ? ?Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> ? ? ? ?Capabilities: [48] Vital Product Data
> ? ? ? ? ? ? ? ?Unknown small resource type 05
> ? ? ? ? ? ? ? ?Unknown large resource type 6c
> ? ? ? ? ? ? ? ?No end tag found
> ? ? ? ?Capabilities: [50] MSI: Mask- 64bit+ Count=1/2 Enable+
> ? ? ? ? ? ? ? ?Address: 00000000fee0300c ?Data: 4161
> ? ? ? ?Capabilities: [60] Express (v1) Endpoint, MSI 00
> ? ? ? ? ? ? ? ?DevCap: MaxPayload 1024 bytes, PhantFunc 0, Latency L0s <1us, L1 unlimited
> ? ? ? ? ? ? ? ? ? ? ? ?ExtTag+ AttnBtn+ AttnInd+ PwrInd+ RBE- FLReset-
> ? ? ? ? ? ? ? ?DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
> ? ? ? ? ? ? ? ? ? ? ? ?RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
> ? ? ? ? ? ? ? ? ? ? ? ?MaxPayload 128 bytes, MaxReadReq 4096 bytes
> ? ? ? ? ? ? ? ?DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr+ TransPend-
> ? ? ? ? ? ? ? ?LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited
> ? ? ? ? ? ? ? ? ? ? ? ?ClockPM- Surprise- LLActRep- BwNot-
> ? ? ? ? ? ? ? ?LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
> ? ? ? ? ? ? ? ? ? ? ? ?ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
> ? ? ? ? ? ? ? ?LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
> ? ? ? ?Capabilities: [84] Vendor Specific Information <?>
> ? ? ? ?Capabilities: [100] Advanced Error Reporting
> ? ? ? ? ? ? ? ?UESta: ?DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
> ? ? ? ? ? ? ? ?UEMsk: ?DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
> ? ? ? ? ? ? ? ?UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
> ? ? ? ? ? ? ? ?CESta: ?RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
> ? ? ? ? ? ? ? ?CEMsk: ?RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
> ? ? ? ? ? ? ? ?AERCap: First Error Pointer: 14, GenCap- CGenEn- ChkCap- ChkEn-
> ? ? ? ?Capabilities: [12c] Virtual Channel <?>
> ? ? ? ?Capabilities: [148] Device Serial Number 68-81-ec-10-00-00-12-45
> ? ? ? ?Capabilities: [154] Power Budgeting <?>
> ? ? ? ?Kernel driver in use: r8169
> 00: ec 10 68 81 07 04 10 00 01 00 00 02 10 00 00 00
> 10: 01 ac 00 00 00 00 00 00 04 f0 cf fd 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 02 01 00 00 ec 10 68 81
> 30: 00 00 cc fd 40 00 00 00 00 00 00 00 05 01 00 00
> 40: 01 48 c2 f7 00 00 00 00 03 50 00 00 05 df c2 f7
> 50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 61 41 00 00
> 60: 10 84 01 00 23 7f 00 00 10 58 1a 00 41 f4 03 00
> 70: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 09 00 4c 01 01 1c 02 00 fb ff ff 11
> 90: 08 30 00 00 a2 10 0a 00 67 50 08 00 c3 01 00 00
> a0: 02 28 ff 01 00 00 00 00 00 08 00 00 03 00 03 00
> b0: 00 00 00 00 ff 3f ff 3f ff ff 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
ok, when you plug in the card, BIOS will enable the pcie bridge...
need other way to figure out it is HT tunnel or HT end devices.
YH
please try follwing patch over pci/linux-next
Thanks
YH
[PATCH] pci: don't enable too much HT MSI mapping -v6
Impact: fix bug
Prakash reported that his c51-mcp51 system ondie sound card doesn't work MSI
but if he hack out the HT-MSI on mcp51, the MSI will work well with sound card.
this patch rework the nv_msi_ht_cap_quirk()
and will only try to avoid to enable ht_msi on device following that root dev,
and don't touch that root dev
v6: only do that trick with end_device on the chain.
Reported-by: Prakash Punnoor <[email protected]>
Signed-off-by: Yinghai Lu <[email protected]>
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index faf02dd..52714f2 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2206,6 +2206,33 @@ static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
return found;
}
+#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
+#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
+
+static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
+{
+ int pos, ctrl_off;
+ int end = 0;
+ u16 flags, ctrl;
+
+ pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
+
+ if (!pos)
+ goto out;
+
+ pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
+
+ ctrl_off = ((flags >> 10) & 1) ?
+ PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
+ pci_read_config_word(dev, pos + ctrl_off, &ctrl);
+
+ if (ctrl & (1 << 6))
+ end = 1;
+
+out:
+ return end;
+}
+
static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
{
struct pci_dev *host_bridge;
@@ -2230,8 +2257,9 @@ static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
if (!found)
return;
- /* don't enable host_bridge with leaf directly here */
- if (host_bridge == dev && host_bridge_with_leaf(host_bridge))
+ /* don't enable end_device/host_bridge with leaf directly here */
+ if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
+ host_bridge_with_leaf(host_bridge))
goto out;
/* root did that ! */
On Sonntag 29 M?rz 2009 03:33:03 Yinghai Lu wrote:
> please try follwing patch over pci/linux-next
>
> Thanks
>
> YH
>
> [PATCH] pci: don't enable too much HT MSI mapping -v6
Works fine now, thanks!
pci 0000:00:00.0: Found disabled HT MSI Mapping
pci 0000:00:00.0: Enabling HT MSI Mapping
pci 0000:00:00.0: Found enabled HT MSI Mapping
pci 0000:00:05.0: Boot video device
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:0e.0: Enabling HT MSI Mapping
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:0f.0: Enabling HT MSI Mapping
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:10.0: Enabling HT MSI Mapping
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:10.1: Enabling HT MSI Mapping
So drop my patch and merge v6 of Yinghai Lu's one.
Cheers,
Prakash
On Sun, Mar 29, 2009 at 2:15 AM, Prakash Punnoor <[email protected]> wrote:
> On Sonntag 29 M?rz 2009 03:33:03 Yinghai Lu wrote:
>> please try follwing patch over pci/linux-next
>>
>> Thanks
>>
>> YH
>>
>> [PATCH] pci: don't enable too much HT MSI mapping -v6
>
> Works fine now, thanks!
>
> pci 0000:00:00.0: Found disabled HT MSI Mapping
> pci 0000:00:00.0: Enabling HT MSI Mapping
> pci 0000:00:00.0: Found enabled HT MSI Mapping
> pci 0000:00:05.0: Boot video device
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:0e.0: Enabling HT MSI Mapping
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:0f.0: Enabling HT MSI Mapping
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:10.0: Enabling HT MSI Mapping
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:10.1: Enabling HT MSI Mapping
>
can you put you pcie network card in the pcie slot belong to c51?
we should find 00:03.0 the pcie bridge...
Thanks
YH
On Sonntag 29 M?rz 2009 11:32:56 Yinghai Lu wrote:
> On Sun, Mar 29, 2009 at 2:15 AM, Prakash Punnoor <[email protected]> wrote:
> > On Sonntag 29 M?rz 2009 03:33:03 Yinghai Lu wrote:
> >> please try follwing patch over pci/linux-next
> >>
> >> Thanks
> >>
> >> YH
> >>
> >> [PATCH] pci: don't enable too much HT MSI mapping -v6
> >
> > Works fine now, thanks!
> >
> > pci 0000:00:00.0: Found disabled HT MSI Mapping
> > pci 0000:00:00.0: Enabling HT MSI Mapping
> > pci 0000:00:00.0: Found enabled HT MSI Mapping
> > pci 0000:00:05.0: Boot video device
> > pci 0000:00:09.0: Found disabled HT MSI Mapping
> > pci 0000:00:0e.0: Enabling HT MSI Mapping
> > pci 0000:00:09.0: Found disabled HT MSI Mapping
> > pci 0000:00:0f.0: Enabling HT MSI Mapping
> > pci 0000:00:09.0: Found disabled HT MSI Mapping
> > pci 0000:00:10.0: Enabling HT MSI Mapping
> > pci 0000:00:09.0: Found disabled HT MSI Mapping
> > pci 0000:00:10.1: Enabling HT MSI Mapping
>
> can you put you pcie network card in the pcie slot belong to c51?
> we should find 00:03.0 the pcie bridge...
>
Above is when inserted in PCIe 1x slot, now in my PCIe 16x slot
(I don't have other options):
pci 0000:00:00.0: Found disabled HT MSI Mapping
pci 0000:00:00.0: Enabling HT MSI Mapping
pci 0000:00:00.0: Found enabled HT MSI Mapping
pci 0000:00:05.0: Boot video device
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:0e.0: Enabling HT MSI Mapping
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:0f.0: Enabling HT MSI Mapping
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:10.0: Enabling HT MSI Mapping
pci 0000:00:09.0: Found disabled HT MSI Mapping
pci 0000:00:10.1: Enabling HT MSI Mapping
00:04.0 PCI bridge: nVidia Corporation C51 PCI Express Bridge (rev a1) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 32 bytes
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 0000a000-0000afff
Memory behind bridge: fdc00000-fdcfffff
Prefetchable memory behind bridge: 00000000fdd00000-00000000fddfffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Subsystem: nVidia Corporation Device 0000
Capabilities: [48] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [50] MSI: Mask- 64bit+ Count=1/2 Enable+
Address: 00000000fee0300c Data: 4149
Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed-
Mapping Address Base: 00000000fee00000
Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us
ExtTag- RBE- FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <512ns, L1 <4us
ClockPM- Surprise- LLActRep+ BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise-
Slot # 0, PowerLimit 0.000000; Interlock- NoCompl-
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Off, PwrInd On, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet+ LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
Capabilities: [100] Virtual Channel <?>
Kernel driver in use: pcieport-driver
00: de 10 fb 02 07 04 10 00 a1 00 04 06 08 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 a1 a1 00 20
20: c0 fd c0 fd d1 fd d1 fd 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00
40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00
50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 49 41 00 00
60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 41 01 c0 04 00 00 10 28 00 00 01 3d 11 00
90: 40 00 11 30 00 00 00 00 c0 01 48 01 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Prakash Punnoor wrote:
> On Sonntag 29 M?rz 2009 11:32:56 Yinghai Lu wrote:
>> On Sun, Mar 29, 2009 at 2:15 AM, Prakash Punnoor <[email protected]> wrote:
>>> On Sonntag 29 M?rz 2009 03:33:03 Yinghai Lu wrote:
>>>> please try follwing patch over pci/linux-next
>>>>
>>>> Thanks
>>>>
>>>> YH
>>>>
>>>> [PATCH] pci: don't enable too much HT MSI mapping -v6
>>> Works fine now, thanks!
>>>
>>> pci 0000:00:00.0: Found disabled HT MSI Mapping
>>> pci 0000:00:00.0: Enabling HT MSI Mapping
>>> pci 0000:00:00.0: Found enabled HT MSI Mapping
>>> pci 0000:00:05.0: Boot video device
>>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>>> pci 0000:00:0e.0: Enabling HT MSI Mapping
>>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>>> pci 0000:00:0f.0: Enabling HT MSI Mapping
>>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>>> pci 0000:00:10.0: Enabling HT MSI Mapping
>>> pci 0000:00:09.0: Found disabled HT MSI Mapping
>>> pci 0000:00:10.1: Enabling HT MSI Mapping
>> can you put you pcie network card in the pcie slot belong to c51?
>> we should find 00:03.0 the pcie bridge...
>>
>
>
> Above is when inserted in PCIe 1x slot, now in my PCIe 16x slot
> (I don't have other options):
>
> pci 0000:00:00.0: Found disabled HT MSI Mapping
> pci 0000:00:00.0: Enabling HT MSI Mapping
> pci 0000:00:00.0: Found enabled HT MSI Mapping
> pci 0000:00:05.0: Boot video device
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:0e.0: Enabling HT MSI Mapping
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:0f.0: Enabling HT MSI Mapping
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:10.0: Enabling HT MSI Mapping
> pci 0000:00:09.0: Found disabled HT MSI Mapping
> pci 0000:00:10.1: Enabling HT MSI Mapping
>
>
>
> 00:04.0 PCI bridge: nVidia Corporation C51 PCI Express Bridge (rev a1) (prog-if 00 [Normal decode])
> Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
> Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
> Latency: 0, Cache Line Size: 32 bytes
> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
> I/O behind bridge: 0000a000-0000afff
> Memory behind bridge: fdc00000-fdcfffff
> Prefetchable memory behind bridge: 00000000fdd00000-00000000fddfffff
> Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
> BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
> PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
> Capabilities: [40] Subsystem: nVidia Corporation Device 0000
> Capabilities: [48] Power Management version 2
> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
> Status: D0 PME-Enable- DSel=0 DScale=0 PME-
> Capabilities: [50] MSI: Mask- 64bit+ Count=1/2 Enable+
> Address: 00000000fee0300c Data: 4149
> Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed-
> Mapping Address Base: 00000000fee00000
> Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00
> DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us
> ExtTag- RBE- FLReset-
> DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
> RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
> MaxPayload 128 bytes, MaxReadReq 512 bytes
> DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
> LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <512ns, L1 <4us
> ClockPM- Surprise- LLActRep+ BwNot-
> LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
> ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
> LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
> SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise-
> Slot # 0, PowerLimit 0.000000; Interlock- NoCompl-
> SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
> Control: AttnInd Off, PwrInd On, Power- Interlock-
> SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
> Changed: MRL- PresDet+ LinkState+
> RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
> RootCap: CRSVisible-
> RootSta: PME ReqID 0000, PMEStatus- PMEPending-
> Capabilities: [100] Virtual Channel <?>
> Kernel driver in use: pcieport-driver
> 00: de 10 fb 02 07 04 10 00 a1 00 04 06 08 00 01 00
> 10: 00 00 00 00 00 00 00 00 00 01 01 00 a1 a1 00 20
> 20: c0 fd c0 fd d1 fd d1 fd 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 04 00
> 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00
> 50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 49 41 00 00
> 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 10 00 41 01 c0 04 00 00 10 28 00 00 01 3d 11 00
> 90: 40 00 11 30 00 00 00 00 c0 01 48 01 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
>
ok, looks good.
Jesse, please apply the -v6, in addition to -v5.
YH
Impact: fix bug
Prakash reported that his c51-mcp51 system ondie sound card doesn't work MSI
but if he hack out the HT-MSI on mcp51, the MSI will work well with sound card.
this patch rework the nv_msi_ht_cap_quirk()
and will only try to avoid to enable ht_msi on device following that root dev,
and don't touch that root dev
v6: only do that trick with end_device on the chain.
Reported-by: Prakash Punnoor <[email protected]>
Tested-by: Prakash Punnoor <[email protected]>
Signed-off-by: Yinghai Lu <[email protected]>
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index faf02dd..52714f2 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2206,6 +2206,33 @@ static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
return found;
}
+#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
+#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
+
+static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
+{
+ int pos, ctrl_off;
+ int end = 0;
+ u16 flags, ctrl;
+
+ pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
+
+ if (!pos)
+ goto out;
+
+ pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
+
+ ctrl_off = ((flags >> 10) & 1) ?
+ PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
+ pci_read_config_word(dev, pos + ctrl_off, &ctrl);
+
+ if (ctrl & (1 << 6))
+ end = 1;
+
+out:
+ return end;
+}
+
static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
{
struct pci_dev *host_bridge;
@@ -2230,8 +2257,9 @@ static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
if (!found)
return;
- /* don't enable host_bridge with leaf directly here */
- if (host_bridge == dev && host_bridge_with_leaf(host_bridge))
+ /* don't enable end_device/host_bridge with leaf directly here */
+ if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
+ host_bridge_with_leaf(host_bridge))
goto out;
/* root did that ! */
On Sun, 29 Mar 2009 12:30:05 -0700
Yinghai Lu <[email protected]> wrote:
> Impact: fix bug
>
> Prakash reported that his c51-mcp51 system ondie sound card doesn't
> work MSI but if he hack out the HT-MSI on mcp51, the MSI will work
> well with sound card.
>
> this patch rework the nv_msi_ht_cap_quirk()
> and will only try to avoid to enable ht_msi on device following that
> root dev, and don't touch that root dev
>
> v6: only do that trick with end_device on the chain.
>
> Reported-by: Prakash Punnoor <[email protected]>
> Tested-by: Prakash Punnoor <[email protected]>
> Signed-off-by: Yinghai Lu <[email protected]>
Applied, thanks for testing & fixing the fix!
Thanks,
--
Jesse Barnes, Intel Open Source Technology Center