From: Wolfgang Muees <[email protected]>
o Document the various pitfalls of SD cards in SPI mode.
Signed-off-by: Wolfgang Muees <[email protected]>
---
diff -uprN 2_6_29_rc7_patch7_unaligned_responses/drivers/mmc/host/mmc_spi.c 2_6_29_rc7_patch8_documentation/drivers/mmc/host/mmc_spi.c
--- 2_6_29_rc7_patch7_unaligned_responses/drivers/mmc/host/mmc_spi.c 2009-03-11 13:51:25.000000000 +0100
+++ 2_6_29_rc7_patch8_documentation/drivers/mmc/host/mmc_spi.c 2009-03-12 10:54:24.000000000 +0100
@@ -68,6 +68,20 @@
* during that time ... at least on unshared bus segments.
*/
+/* PITFALLS:
+ *
+ * - SD card benchmarking is done in 4 bit SD mode. Nobody care about
+ * speed in SPI mode. So expect less throughput and longer timeouts
+ * as in SD mode. (See core.c:mmc_set_data_timeout()).
+ * - SPI imposes a byte-aligned protocol. Expect that SD cards violate
+ * this requirement for ALL responses:
+ * - response after command
+ * - data token up to CRC for read blocks
+ * - token response after a write block
+ * - Expect that the delay (in bits) will vary according to the
+ * buffer fill grade in the SD card controller.
+ * - Expect that CRC16 is only working for full 512 byte data blocks.
+ */
/*
* Local protocol constants, internal to data block protocols.
@@ -695,8 +709,8 @@ mmc_spi_writeblock(struct mmc_spi_host *
* writes succeeded; see the standard.
*
* In practice, there are (even modern SDHC-)Cards which need
- * some bits to send the response, so we have to cope with this
- * situation and check the response bit-by-bit. Arggh!!!
+ * some clock bits to send the response, so we have to cope with
+ * this situation and check the response bit-by-bit. Arggh!!!
*/
pattern = scratch->status[0] << 24;
pattern |= scratch->status[1] << 16;
---
regards
i. A. Wolfgang M?es
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On Thu, 12 Mar 2009 11:06:37 +0100
Wolfgang Mües <[email protected]> wrote:
> From: Wolfgang Muees <[email protected]>
>
> o Document the various pitfalls of SD cards in SPI mode.
>
> Signed-off-by: Wolfgang Muees <[email protected]>
>
> ---
> diff -uprN 2_6_29_rc7_patch7_unaligned_responses/drivers/mmc/host/mmc_spi.c 2_6_29_rc7_patch8_documentation/drivers/mmc/host/mmc_spi.c
> --- 2_6_29_rc7_patch7_unaligned_responses/drivers/mmc/host/mmc_spi.c 2009-03-11 13:51:25.000000000 +0100
> +++ 2_6_29_rc7_patch8_documentation/drivers/mmc/host/mmc_spi.c 2009-03-12 10:54:24.000000000 +0100
> @@ -68,6 +68,20 @@
> * during that time ... at least on unshared bus segments.
> */
>
> +/* PITFALLS:
> + *
> + * - SD card benchmarking is done in 4 bit SD mode. Nobody care about
> + * speed in SPI mode. So expect less throughput and longer timeouts
> + * as in SD mode. (See core.c:mmc_set_data_timeout()).
> + * - SPI imposes a byte-aligned protocol. Expect that SD cards violate
> + * this requirement for ALL responses:
> + * - response after command
> + * - data token up to CRC for read blocks
> + * - token response after a write block
Perhaps you should elaborate on why this is (not everyone knows that
the native protocol isn't byte aligned).
> + * - Expect that the delay (in bits) will vary according to the
> + * buffer fill grade in the SD card controller.
> + * - Expect that CRC16 is only working for full 512 byte data blocks.
This is a bit premature as so far it's only the CSD and CID that have
been found to violate the CRC requirement. And that's somewhat expected
as those are probably precomputed and stored on the card (and someone
forgot to update them).
Rgds
--
-- Pierre Ossman
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