From: Dexuan Cui <[email protected]>
As per PCI Bus Power Management Interface Specification Revision 1.2
this is bit 3, not bit 2, of the Power Management Control/Status
register.
Signed-off-by: Dexuan Cui <[email protected]>
Signed-off-by: Jan Beulich <[email protected]>
Cc: stable <[email protected]>
---
include/linux/pci_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- linux-2.6.29-rc8/include/linux/pci_regs.h 2009-03-17 17:14:16.000000000 +0100
+++ 2.6.29-rc8-pci-pm-ctrl-no-soft-reset/include/linux/pci_regs.h 2009-03-04 11:25:28.000000000 +0100
@@ -235,7 +235,7 @@
#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
#define PCI_PM_CTRL 4 /* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
-#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */
+#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
On Tue, Mar 17, 2009 at 04:17:48PM +0000, Jan Beulich wrote:
> From: Dexuan Cui <[email protected]>
>
> As per PCI Bus Power Management Interface Specification Revision 1.2
> this is bit 3, not bit 2, of the Power Management Control/Status
> register.
The same patch was already posted by Yu Zhao on February 25th and I
reviewed it for Jesse. I don't see it in any of the trees yet though ...
(arguably, I should have picked it up for the fixes tree that I did
while Jesse was away).
--
Matthew Wilcox Intel Open Source Technology Centre
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours. We can't possibly take such
a retrograde step."
On Tue, 17 Mar 2009 11:38:45 -0600
Matthew Wilcox <[email protected]> wrote:
> On Tue, Mar 17, 2009 at 04:17:48PM +0000, Jan Beulich wrote:
> > From: Dexuan Cui <[email protected]>
> >
> > As per PCI Bus Power Management Interface Specification Revision 1.2
> > this is bit 3, not bit 2, of the Power Management Control/Status
> > register.
>
> The same patch was already posted by Yu Zhao on February 25th and I
> reviewed it for Jesse. I don't see it in any of the trees yet
> though ... (arguably, I should have picked it up for the fixes tree
> that I did while Jesse was away).
Yeah I've got it in my queue but haven't pushed it yet. Thanks.
--
Jesse Barnes, Intel Open Source Technology Center
On Wed, Mar 18, 2009 at 01:38:45AM +0800, Matthew Wilcox wrote:
> On Tue, Mar 17, 2009 at 04:17:48PM +0000, Jan Beulich wrote:
> > From: Dexuan Cui <[email protected]>
> >
> > As per PCI Bus Power Management Interface Specification Revision 1.2
> > this is bit 3, not bit 2, of the Power Management Control/Status
> > register.
>
> The same patch was already posted by Yu Zhao on February 25th and I
> reviewed it for Jesse. I don't see it in any of the trees yet though ...
> (arguably, I should have picked it up for the fixes tree that I did
> while Jesse was away).
Sorry, I didn't bother you to pick it up for the rc because the wrong mask
doesn't cause any known problem so far (fortunately the wrong bit used as
No_Soft_Reset is hardwired to 0, which means PM restores the config space
for all the devices).