2009-11-10 18:49:44

by Dave Jones

Subject: x86: add new cache descriptors

The latest rev of Intel doc AP-485 details new cache descriptors that we don't yet support.
12MB, 18MB and 24MB 24-way assoc L3 caches.

Signed-off-by: Dave Jones <[email protected]>

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 804c40e..228fc67 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -102,6 +102,9 @@ static const struct _cache_table __cpuinitconst cache_table[] =
{ 0xe2, LVL_3, 2048 }, /* 16-way set assoc, 64 byte line size */
{ 0xe3, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
{ 0xe4, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
+ { 0xea, LVL_3, 12288 }, /* 24-way set assoc, 64 byte line size */
+ { 0xeb, LVL_3, 18432 }, /* 24-way set assoc, 64 byte line size */
+ { 0xec, LVL_3, 24576 }, /* 24-way set assoc, 64 byte line size */
{ 0x00, 0, 0}
};

2009-11-10 19:00:11

by Dave Jones

Subject: Re: x86: add new cache descriptors

On Tue, Nov 10, 2009 at 01:49:24PM -0500, Dave Jones wrote:

> diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
> index 804c40e..228fc67 100644
> --- a/arch/x86/kernel/cpu/intel_cacheinfo.c
> +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
> @@ -102,6 +102,9 @@ static const struct _cache_table __cpuinitconst cache_table[] =
> { 0xe2, LVL_3, 2048 }, /* 16-way set assoc, 64 byte line size */
> { 0xe3, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
> { 0xe4, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
> + { 0xea, LVL_3, 12288 }, /* 24-way set assoc, 64 byte line size */
> + { 0xeb, LVL_3, 18432 }, /* 24-way set assoc, 64 byte line size */
> + { 0xec, LVL_3, 24576 }, /* 24-way set assoc, 64 byte line size */
> { 0x00, 0, 0}

btw, something I'm thinking of doing as a followup is making these use the
defines like we have in drivers/char/agp/agp.h

#define KB(x) ((x) * 1024)
#define MB(x) (KB (KB (x)))
#define GB(x) (MB (KB (x)))

There's a few similar definitions throughout the tree. Any opinions on whether
I should add these to kernel.h, or create a new header for them ?

Dave

2009-11-10 19:09:57

by Dave Jones

Subject: [tip:x86/urgent] x86: Add new Intel CPU cache size descriptors

Commit-ID: 85160b92fbd35321104819283c91bfed2b553e3c
Gitweb: http://git.kernel.org/tip/85160b92fbd35321104819283c91bfed2b553e3c
Author: Dave Jones <[email protected]>
AuthorDate: Tue, 10 Nov 2009 13:49:24 -0500
Committer: Ingo Molnar <[email protected]>
CommitDate: Tue, 10 Nov 2009 20:06:16 +0100

x86: Add new Intel CPU cache size descriptors

The latest rev of Intel doc AP-485 details new cache descriptors
that we don't yet support. 12MB, 18MB and 24MB 24-way assoc L3
caches.

Signed-off-by: Dave Jones <[email protected]>
LKML-Reference: <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 804c40e..1410392 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -102,6 +102,9 @@ static const struct _cache_table __cpuinitconst cache_table[] =
{ 0xe2, LVL_3, 2048 }, /* 16-way set assoc, 64 byte line size */
{ 0xe3, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
{ 0xe4, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
+ { 0xea, LVL_3, 12288 }, /* 24-way set assoc, 64 byte line size */
+ { 0xeb, LVL_3, 18432 }, /* 24-way set assoc, 64 byte line size */
+ { 0xec, LVL_3, 24576 }, /* 24-way set assoc, 64 byte line size */
{ 0x00, 0, 0}
};