2009-11-10 20:01:54

by Dave Jones

Subject: Fix typo in intel cache size

I double-checked the datasheet. This should be 2MB.

Signed-off-by: Dave Jones <[email protected]>

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 804c40e..6123138 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -94,7 +94,7 @@ static const struct _cache_table __cpuinitconst cache_table[] =
{ 0xd1, LVL_3, 1024 }, /* 4-way set assoc, 64 byte line size */
{ 0xd2, LVL_3, 2048 }, /* 4-way set assoc, 64 byte line size */
{ 0xd6, LVL_3, 1024 }, /* 8-way set assoc, 64 byte line size */
- { 0xd7, LVL_3, 2038 }, /* 8-way set assoc, 64 byte line size */
+ { 0xd7, LVL_3, 2048 }, /* 8-way set assoc, 64 byte line size */
{ 0xd8, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */
{ 0xdc, LVL_3, 2048 }, /* 12-way set assoc, 64 byte line size */
{ 0xdd, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */

2009-11-10 20:53:51

by Ingo Molnar

Subject: Re: Fix typo in intel cache size

* Dave Jones <[email protected]> wrote:

> I double-checked the datasheet. This should be 2MB.
>
> Signed-off-by: Dave Jones <[email protected]>
>
> diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
> index 804c40e..6123138 100644
> --- a/arch/x86/kernel/cpu/intel_cacheinfo.c
> +++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
> @@ -94,7 +94,7 @@ static const struct _cache_table __cpuinitconst cache_table[] =
> { 0xd1, LVL_3, 1024 }, /* 4-way set assoc, 64 byte line size */
> { 0xd2, LVL_3, 2048 }, /* 4-way set assoc, 64 byte line size */
> { 0xd6, LVL_3, 1024 }, /* 8-way set assoc, 64 byte line size */
> - { 0xd7, LVL_3, 2038 }, /* 8-way set assoc, 64 byte line size */
> + { 0xd7, LVL_3, 2048 }, /* 8-way set assoc, 64 byte line size */

ah, thanks - applied.

I also marked both fixes from you for -stable backport - these are
pretty risk-free fixes and cpuinfo looks ugly on new CPUs without a
proper cache size entry.

Thanks,

Ingo

2009-11-10 20:55:26

by Dave Jones

Subject: [tip:x86/urgent] x86: Fix typo in Intel CPU cache size descriptor

Commit-ID: e02e0e1a130b9ca37c5186d38ad4b3aaf58bb149
Gitweb: http://git.kernel.org/tip/e02e0e1a130b9ca37c5186d38ad4b3aaf58bb149
Author: Dave Jones <[email protected]>
AuthorDate: Tue, 10 Nov 2009 15:01:20 -0500
Committer: Ingo Molnar <[email protected]>
CommitDate: Tue, 10 Nov 2009 21:52:32 +0100

x86: Fix typo in Intel CPU cache size descriptor

I double-checked the datasheet. One of the existing
descriptors has a typo: it should be 2MB not 2038 KB.

Signed-off-by: Dave Jones <[email protected]>
Cc: <[email protected]> # .3x.x: 85160b9: x86: Add new Intel CPU cache size descriptors
Cc: <[email protected]> # .3x.x
LKML-Reference: <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 1410392..8178d03 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -94,7 +94,7 @@ static const struct _cache_table __cpuinitconst cache_table[] =
{ 0xd1, LVL_3, 1024 }, /* 4-way set assoc, 64 byte line size */
{ 0xd2, LVL_3, 2048 }, /* 4-way set assoc, 64 byte line size */
{ 0xd6, LVL_3, 1024 }, /* 8-way set assoc, 64 byte line size */
- { 0xd7, LVL_3, 2038 }, /* 8-way set assoc, 64 byte line size */
+ { 0xd7, LVL_3, 2048 }, /* 8-way set assoc, 64 byte line size */
{ 0xd8, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */
{ 0xdc, LVL_3, 2048 }, /* 12-way set assoc, 64 byte line size */
{ 0xdd, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */