The max junction temperature of Atom N450/D410/D510 CPUs is 100 degrees Celsius.
Since these CPUs are always coupled with Intel NM10 chipset in one package, the
best way to verify whether an Atom CPU is N450/D410/D510 is to check the host
bridge device.
Signed-off-by: Yong Wang <[email protected]>
Acked-by: Huaxu Wan <[email protected]>
---
drivers/hwmon/coretemp.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index caef39c..65a33ec 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -33,6 +33,7 @@
#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/cpu.h>
+#include <linux/pci.h>
#include <asm/msr.h>
#include <asm/processor.h>
@@ -161,6 +162,7 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
int usemsr_ee = 1;
int err;
u32 eax, edx;
+ struct pci_dev *host_bridge;
/* Early chips have no MSR for TjMax */
@@ -168,11 +170,21 @@ static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *
usemsr_ee = 0;
}
- /* Atoms seems to have TjMax at 90C */
+ /* Atoms CPUs */
if (c->x86_model == 0x1c) {
usemsr_ee = 0;
- tjmax = 90000;
+
+ host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
+
+ if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
+ && (host_bridge->device == 0xa000 /* NM10 based nettop */
+ || host_bridge->device == 0xa010)) /* NM10 based netbook */
+ tjmax = 100000;
+ else
+ tjmax = 90000;
+
+ pci_dev_put(host_bridge);
}
if ((c->x86_model > 0xe) && (usemsr_ee)) {
Hi Yong,
On Thu, 24 Dec 2009 15:31:02 +0800, Yong Wang wrote:
> The max junction temperature of Atom N450/D410/D510 CPUs is 100 degrees Celsius.
> Since these CPUs are always coupled with Intel NM10 chipset in one package, the
> best way to verify whether an Atom CPU is N450/D410/D510 is to check the host
> bridge device.
>
> Signed-off-by: Yong Wang <[email protected]>
> Acked-by: Huaxu Wan <[email protected]>
Applied, thanks. I've also added a Kconfig dependency on CONFIG_PCI.
--
Jean Delvare
On Wed, 6 Jan 2010 16:08:17 +0100, Jean Delvare wrote:
> Hi Yong,
>
> On Thu, 24 Dec 2009 15:31:02 +0800, Yong Wang wrote:
> > The max junction temperature of Atom N450/D410/D510 CPUs is 100 degrees Celsius.
> > Since these CPUs are always coupled with Intel NM10 chipset in one package, the
> > best way to verify whether an Atom CPU is N450/D410/D510 is to check the host
> > bridge device.
> >
> > Signed-off-by: Yong Wang <[email protected]>
> > Acked-by: Huaxu Wan <[email protected]>
>
> Applied, thanks. I've also added a Kconfig dependency on CONFIG_PCI.
Hmm. Thinking about it some more... What about nVidia-based systems?
Can't we have systems with an Atom N450/D410/D510 and a non-Intel
chipset?
--
Jean Delvare
On Sun, Jan 10, 2010 at 08:06:21PM +0100, Jean Delvare wrote:
>
> Hmm. Thinking about it some more... What about nVidia-based systems?
> Can't we have systems with an Atom N450/D410/D510 and a non-Intel
> chipset?
>
No matter what chipset or gfx you use with the new Atom chip, the
integrated memory controller (IMC) will always be used. This patch
checks the presence of that IMC. Hope this clarifies.
Thanks
-Yong
On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
>
> > No matter what chipset or gfx you use with the new Atom chip, the
> > integrated memory controller (IMC) will always be used. This patch
> > checks the presence of that IMC. Hope this clarifies.
> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
What prevents another vendor from selling a compatible south bridge
then?
I start believing that we'd rather identify these Atom models using
CPUID rather than a PCI device.
--
Jean Delvare
On 01/17/2010 09:15 AM, Jean Delvare wrote:
> On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
>>
>>> No matter what chipset or gfx you use with the new Atom chip, the
>>> integrated memory controller (IMC) will always be used. This patch
>>> checks the presence of that IMC. Hope this clarifies.
>> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
>
> What prevents another vendor from selling a compatible south bridge
> then?
Nothing (other than licensing for the DMI bus, see NVIDIA and the
problems this creates for their ION chipset). I'm assuming this patch is
checking for the host bridge device though, that is integrated into the
CPU and would always be present.
>
> I start believing that we'd rather identify these Atom models using
> CPUID rather than a PCI device.
>
On Sun, 17 Jan 2010 13:29:06 -0600, Robert Hancock wrote:
> On 01/17/2010 09:15 AM, Jean Delvare wrote:
> > On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
> >>
> >>> No matter what chipset or gfx you use with the new Atom chip, the
> >>> integrated memory controller (IMC) will always be used. This patch
> >>> checks the presence of that IMC. Hope this clarifies.
> >> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
> >
> > What prevents another vendor from selling a compatible south bridge
> > then?
>
> Nothing (other than licensing for the DMI bus, see NVIDIA and the
> problems this creates for their ION chipset). I'm assuming this patch is
> checking for the host bridge device though, that is integrated into the
> CPU and would always be present.
That's where I am confused. The patch checks for the presence of the
Intel NM10, which, reading its description looks much like a south
bridge and not a memory controller (north bridge). So I think the patch
is wrong (or at least incomplete).
Anyway, how difficult would it be to set TjMax based on the CPUID? I
presume that the Intel Atom 400 and 500 series have their own CPUID
value, haven't they? This would seem even easier that checking for a
PCI device.
--
Jean Delvare
On Sun, Jan 17, 2010 at 09:05:36PM +0100, Jean Delvare wrote:
> On Sun, 17 Jan 2010 13:29:06 -0600, Robert Hancock wrote:
> > On 01/17/2010 09:15 AM, Jean Delvare wrote:
> > > On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
> > >>
> > >>> No matter what chipset or gfx you use with the new Atom chip, the
> > >>> integrated memory controller (IMC) will always be used. This patch
> > >>> checks the presence of that IMC. Hope this clarifies.
> > >> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
This is correct.
> > >
> > > What prevents another vendor from selling a compatible south bridge
> > > then?
> >
> > Nothing (other than licensing for the DMI bus, see NVIDIA and the
> > problems this creates for their ION chipset). I'm assuming this patch is
> > checking for the host bridge device though, that is integrated into the
> > CPU and would always be present.
>
> That's where I am confused. The patch checks for the presence of the
> Intel NM10, which, reading its description looks much like a south
> bridge and not a memory controller (north bridge). So I think the patch
> is wrong (or at least incomplete).
>
Sorry, I made a mistake in the patch description. The new Atom CPU is
coupled with integrated gfx and memory controller in one package. NM10
chipset is another chip. This patch does check the presence of the
integrated memory controller, i.e. 00:00.0 Host bridge device, which
will always be present no matter whether NM10 chipset is used or not.
> Anyway, how difficult would it be to set TjMax based on the CPUID? I
> presume that the Intel Atom 400 and 500 series have their own CPUID
> value, haven't they? This would seem even easier that checking for a
> PCI device.
>
CPUID value (family and model number) remains the same for all Atom CPUs
thus far. That is why we check the new Atom CPU this way.
Thanks
-Yong
On 21:05 Sun 17 Jan, Jean Delvare wrote:
> On Sun, 17 Jan 2010 13:29:06 -0600, Robert Hancock wrote:
> > On 01/17/2010 09:15 AM, Jean Delvare wrote:
> > > On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
> > >>
> > >>> No matter what chipset or gfx you use with the new Atom chip, the
> > >>> integrated memory controller (IMC) will always be used. This patch
> > >>> checks the presence of that IMC. Hope this clarifies.
> > >> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
> > >
> > > What prevents another vendor from selling a compatible south bridge
> > > then?
> >
> > Nothing (other than licensing for the DMI bus, see NVIDIA and the
> > problems this creates for their ION chipset). I'm assuming this patch is
> > checking for the host bridge device though, that is integrated into the
> > CPU and would always be present.
>
> That's where I am confused. The patch checks for the presence of the
> Intel NM10, which, reading its description looks much like a south
> bridge and not a memory controller (north bridge). So I think the patch
> is wrong (or at least incomplete).
>
> Anyway, how difficult would it be to set TjMax based on the CPUID? I
> presume that the Intel Atom 400 and 500 series have their own CPUID
> value, haven't they? This would seem even easier that checking for a
> PCI device.
Actually, all the Atom processors share the same CPUID(0x1C) and the
worse is not all of them has the same TjMax. That's a big problem.
Thanks
Huaxu
On Mon, 18 Jan 2010 15:21:38 +0800, Huaxu Wan wrote:
> On 21:05 Sun 17 Jan, Jean Delvare wrote:
> > Anyway, how difficult would it be to set TjMax based on the CPUID? I
> > presume that the Intel Atom 400 and 500 series have their own CPUID
> > value, haven't they? This would seem even easier that checking for a
> > PCI device.
>
> Actually, all the Atom processors share the same CPUID(0x1C) and the
> worse is not all of them has the same TjMax. That's a big problem.
0x1C is the product value. The stepping value could be different. There
could also be other identification methods based on cpuid() or rdmsr()
commands. This is done quite frequently to identify specific CPU models.
--
Jean Delvare
On Mon, 18 Jan 2010 14:58:21 +0800, Yong Wang wrote:
> On Sun, Jan 17, 2010 at 09:05:36PM +0100, Jean Delvare wrote:
> > That's where I am confused. The patch checks for the presence of the
> > Intel NM10, which, reading its description looks much like a south
> > bridge and not a memory controller (north bridge). So I think the patch
> > is wrong (or at least incomplete).
>
> Sorry, I made a mistake in the patch description. The new Atom CPU is
> coupled with integrated gfx and memory controller in one package. NM10
> chipset is another chip. This patch does check the presence of the
> integrated memory controller, i.e. 00:00.0 Host bridge device, which
> will always be present no matter whether NM10 chipset is used or not.
OK. Then indeed the patch description was rather bad. Even the comments
in the code are misleading, they mention the NM10 when they don't
really have to.
But at least if the code itself is OK... that's not that bad.
> > Anyway, how difficult would it be to set TjMax based on the CPUID? I
> > presume that the Intel Atom 400 and 500 series have their own CPUID
> > value, haven't they? This would seem even easier that checking for a
> > PCI device.
>
> CPUID value (family and model number) remains the same for all Atom CPUs
> thus far. That is why we check the new Atom CPU this way.
What about the stepping value? Don't these CPU models have their own?
Thanks,
--
Jean Delvare
On Mon, Jan 18, 2010 at 09:14:51AM +0100, Jean Delvare wrote:
> On Mon, 18 Jan 2010 14:58:21 +0800, Yong Wang wrote:
> > On Sun, Jan 17, 2010 at 09:05:36PM +0100, Jean Delvare wrote:
> > > That's where I am confused. The patch checks for the presence of the
> > > Intel NM10, which, reading its description looks much like a south
> > > bridge and not a memory controller (north bridge). So I think the patch
> > > is wrong (or at least incomplete).
> >
> > Sorry, I made a mistake in the patch description. The new Atom CPU is
> > coupled with integrated gfx and memory controller in one package. NM10
> > chipset is another chip. This patch does check the presence of the
> > integrated memory controller, i.e. 00:00.0 Host bridge device, which
> > will always be present no matter whether NM10 chipset is used or not.
>
> OK. Then indeed the patch description was rather bad. Even the comments
> in the code are misleading, they mention the NM10 when they don't
> really have to.
>
> But at least if the code itself is OK... that's not that bad.
>
> > > Anyway, how difficult would it be to set TjMax based on the CPUID? I
> > > presume that the Intel Atom 400 and 500 series have their own CPUID
> > > value, haven't they? This would seem even easier that checking for a
> > > PCI device.
> >
> > CPUID value (family and model number) remains the same for all Atom CPUs
> > thus far. That is why we check the new Atom CPU this way.
>
> What about the stepping value? Don't these CPU models have their own?
>
The stepping value is not architectually defined. Therefore, it is not
the recommended way to detect CPU make and models.
Thanks
-Yong
> No matter what chipset or gfx you use with the new Atom chip, the
> integrated memory controller (IMC) will always be used. This patch
> checks the presence of that IMC. Hope this clarifies.
To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
Yuhong Bao
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