When using iommu_domain_alloc with the Intel iommu, the domain address width
is always initialized to 48 bits (agaw 2). This domain->agaw value is then
used by pfn_to_dma_pte to (always) build a 4 level page table. However, not
all systems support iommu width of 48 or 4 level page tables. In particular,
the Core i5-660 and i5-670 support an address width of 36 bits (not 39!), an
agaw of only 1, and only 3 level page tables.
This version of the patch simply lops off extra levels of the page tables if
the agaw value of the iommu is less than what is currently allocated for the
domain (in intel_iommu_attach_device). If there were already allocated
addresses above what the new iommu can handle, EFAULT is returned.
Signed-off-by: Tom Lyon <[email protected]>
---
V1 and V2 of this patch were patch of a larger patch, this is now independent.
--- linux-2.6.33/drivers/pci/intel-iommu.c 2010-02-24 10:52:17.000000000 -0800
+++ mylinux-2.6.33/drivers/pci/intel-iommu.c 2010-04-13 16:51:55.000000000 -0700
@@ -3436,22 +3436,6 @@
/* domain id for virtual machine, it won't be set in context */
static unsigned long vm_domid;
-static int vm_domain_min_agaw(struct dmar_domain *domain)
-{
- int i;
- int min_agaw = domain->agaw;
-
- i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
- for (; i < g_num_of_iommus; ) {
- if (min_agaw > g_iommus[i]->agaw)
- min_agaw = g_iommus[i]->agaw;
-
- i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
- }
-
- return min_agaw;
-}
-
static struct dmar_domain *iommu_alloc_vm_domain(void)
{
struct dmar_domain *domain;
@@ -3582,7 +3566,6 @@
struct pci_dev *pdev = to_pci_dev(dev);
struct intel_iommu *iommu;
int addr_width;
- u64 end;
/* normally pdev is not mapped */
if (unlikely(domain_context_mapped(pdev))) {
@@ -3605,14 +3588,30 @@
/* check if this iommu agaw is sufficient for max mapped address */
addr_width = agaw_to_width(iommu->agaw);
- end = DOMAIN_MAX_ADDR(addr_width);
- end = end & VTD_PAGE_MASK;
- if (end < dmar_domain->max_addr) {
- printk(KERN_ERR "%s: iommu agaw (%d) is not "
+ if (addr_width > cap_mgaw(iommu->cap))
+ addr_width = cap_mgaw(iommu->cap);
+
+ if (dmar_domain->max_addr > (1LL << addr_width)) {
+ printk(KERN_ERR "%s: iommu width (%d) is not "
"sufficient for the mapped address (%llx)\n",
- __func__, iommu->agaw, dmar_domain->max_addr);
+ __func__, addr_width, dmar_domain->max_addr);
return -EFAULT;
}
+ dmar_domain->gaw = addr_width;
+
+ /*
+ * Knock out extra levels of page tables if necessary
+ */
+ while (iommu->agaw < dmar_domain->agaw) {
+ struct dma_pte *pte;
+
+ pte = dmar_domain->pgd;
+ if (dma_pte_present(pte)) {
+ free_pgtable_page(dmar_domain->pgd);
+ dmar_domain->pgd = (struct dma_pte *)dma_pte_addr(pte);
+ }
+ dmar_domain->agaw--;
+ }
return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
}
On Mon, 19 Apr 2010 14:44:16 -0700
"Tom Lyon" <[email protected]> wrote:
>
> When using iommu_domain_alloc with the Intel iommu, the domain address width
> is always initialized to 48 bits (agaw 2). __This domain->agaw value is then
> used by pfn_to_dma_pte to (always) build a 4 level page table. __However, not
> all systems support iommu width of 48 or 4 level page tables. __In particular,
> the Core i5-660 and i5-670 support an address width of 36 bits (not 39!), an
> agaw of only 1, and only 3 level page tables.
>
> This version of the patch simply lops off extra levels of the page tables if
> the agaw value of the iommu is less than what is currently allocated for the
> domain (in intel_iommu_attach_device). If there were already allocated
> addresses above what the new iommu can handle, EFAULT is returned.
> Signed-off-by: Tom Lyon <[email protected]>
This smells like a 2.6.34 patch. Do you agree?
I agree, but I defer to Mr. Woodhouse.
On Monday 19 April 2010 03:43:39 pm Andrew Morton wrote:
> On Mon, 19 Apr 2010 14:44:16 -0700
> "Tom Lyon" <[email protected]> wrote:
>
> >
> > When using iommu_domain_alloc with the Intel iommu, the domain address width
> > is always initialized to 48 bits (agaw 2). __This domain->agaw value is then
> > used by pfn_to_dma_pte to (always) build a 4 level page table. __However, not
> > all systems support iommu width of 48 or 4 level page tables. __In particular,
> > the Core i5-660 and i5-670 support an address width of 36 bits (not 39!), an
> > agaw of only 1, and only 3 level page tables.
> >
> > This version of the patch simply lops off extra levels of the page tables if
> > the agaw value of the iommu is less than what is currently allocated for the
> > domain (in intel_iommu_attach_device). If there were already allocated
> > addresses above what the new iommu can handle, EFAULT is returned.
> > Signed-off-by: Tom Lyon <[email protected]>
>
> This smells like a 2.6.34 patch. Do you agree?
>
* Andrew Morton ([email protected]) wrote:
> On Mon, 19 Apr 2010 14:44:16 -0700
> "Tom Lyon" <[email protected]> wrote:
> >
> > When using iommu_domain_alloc with the Intel iommu, the domain address width
> > is always initialized to 48 bits (agaw 2). __This domain->agaw value is then
> > used by pfn_to_dma_pte to (always) build a 4 level page table. __However, not
> > all systems support iommu width of 48 or 4 level page tables. __In particular,
> > the Core i5-660 and i5-670 support an address width of 36 bits (not 39!), an
> > agaw of only 1, and only 3 level page tables.
> >
> > This version of the patch simply lops off extra levels of the page tables if
> > the agaw value of the iommu is less than what is currently allocated for the
> > domain (in intel_iommu_attach_device). If there were already allocated
> > addresses above what the new iommu can handle, EFAULT is returned.
> > Signed-off-by: Tom Lyon <[email protected]>
>
> This smells like a 2.6.34 patch. Do you agree?
I didn't think this effected in-tree code. Tom hit this while developing
a new user of the iommu interface, whereas the current user (KVM) doesn't
trigger this.
thanks,
-chris