by Thomas Petazzoni

Hi Linus,

On Mon, Jul 29, 2013 at 06:20:13PM +0200, Linus Walleij wrote:
> On Wed, Jul 24, 2013 at 12:25 AM, Maxime Ripard
> <[email protected]> wrote:
>
> > The Allwinner A31 SoC uses the same IP than the one found in the
> > A10/A13, with only different pins. Add the pins and the associated
> > functions found in the A31.
> >
> > Signed-off-by: Maxime Ripard <[email protected]>
>
> Acked-by: Linus Walleij <[email protected]>
>
> Will you carry this through ARM SoC or do you want me to merge
> this into the pinctrl tree? It seems pretty independent.

I'd prefer if you could merge it through the pinctrl tree.

Thanks!
Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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2013-07-30 12:44:57

by Maxime Ripard

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Subject: Re: [PATCH 04/10] ARM: sun6i: Add restart code for the A31

Hi Mark,

On Mon, Jul 29, 2013 at 03:04:31PM +0100, Mark Rutland wrote:
> On Tue, Jul 23, 2013 at 11:25:06PM +0100, Maxime Ripard wrote:
> > The Allwinner A31 has a sligthly different watchdog that requires a
> > different restart code.
> >
> > Signed-off-by: Maxime Ripard <[email protected]>
> > ---
> > arch/arm/mach-sunxi/sunxi.c | 37 +++++++++++++++++++++++++++++++++++++
> > 1 file changed, 37 insertions(+)
> >
> > diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> > index 11326d9..c18ef3a 100644
> > --- a/arch/arm/mach-sunxi/sunxi.c
> > +++ b/arch/arm/mach-sunxi/sunxi.c
> > @@ -32,6 +32,15 @@
> > #define SUN4I_WATCHDOG_MODE_ENABLE (1 << 0)
> > #define SUN4I_WATCHDOG_MODE_RESET_ENABLE (1 << 1)
> >
> > +#define SUN6I_WATCHDOG1_IRQ_REG 0x00
> > +#define SUN6I_WATCHDOG1_CTRL_REG 0x10
> > +#define SUN6I_WATCHDOG1_CTRL_RESTART (1 << 0)
> > +#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
> > +#define SUN6I_WATCHDOG1_CONFIG_RESTART (1 << 0)
> > +#define SUN6I_WATCHDOG1_CONFIG_IRQ (1 << 1)
> > +#define SUN6I_WATCHDOG1_MODE_REG 0x18
> > +#define SUN6I_WATCHDOG1_MODE_ENABLE (1 << 0)
> > +
> > static void __iomem *wdt_base;
> >
> > static void sun4i_restart(enum reboot_mode mode, const char *cmd)
> > @@ -56,8 +65,36 @@ static void sun4i_restart(enum reboot_mode mode, const char *cmd)
> > }
> > }
> >
> > +static void sun6i_restart(char mode, const char *cmd)
> > +{
> > + if (!wdt_base)
> > + return;
> > +
> > + /* Disable interrupts */
> > + writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);
> > +
> > + /* We want to disable the IRQ and just reset the whole system */
> > + writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
> > + wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);
> > +
> > + /* Enable timer. The default and lowest interval value is 0.5s */
> > + writel(SUN6I_WATCHDOG1_MODE_ENABLE,
> > + wdt_base + SUN6I_WATCHDOG1_MODE_REG);
> > +
> > + /* Restart the watchdog. */
> > + writel(SUN6I_WATCHDOG1_CTRL_RESTART,
> > + wdt_base + SUN6I_WATCHDOG1_CTRL_REG);
> > +
> > + while (1) {
> > + mdelay(5);
> > + writel(SUN6I_WATCHDOG1_MODE_ENABLE,
> > + wdt_base + SUN6I_WATCHDOG1_MODE_REG);
> > + }
> > +}
> > +
> > static struct of_device_id sunxi_restart_ids[] = {
> > { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
> > + { .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart },
>
> Is there a corresponding binding document addition?
>
> sun4i-wdt.txt could be turned into a more general sunxi-wdt.txt.

Ah, right, thanks!

I'll fix it in the v2.

Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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2013-07-30 13:18:32

by Maxime Ripard

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Subject: Re: [PATCH 05/10] ARM: sunxi: Add Allwinner A31 DTSI

Hi Marc,

On Tue, Jul 30, 2013 at 09:59:02AM +0100, Marc Zyngier wrote:
> Hi Maxime,
>
> On 23/07/13 23:25, Maxime Ripard wrote:
> > Signed-off-by: Maxime Ripard <[email protected]>
> > ---
> > arch/arm/boot/dts/Makefile | 3 +-
> > arch/arm/boot/dts/sun6i-a31.dtsi | 155 +++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 157 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/boot/dts/sun6i-a31.dtsi
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 641b3c9..1482533 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -210,7 +210,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
> > sun4i-a10-mini-xplus.dtb \
> > sun4i-a10-hackberry.dtb \
> > sun5i-a10s-olinuxino-micro.dtb \
> > - sun5i-a13-olinuxino.dtb
> > + sun5i-a13-olinuxino.dtb \
> > + sun6i-a31-colombus.dtb
> > dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
> > tegra20-iris-512.dtb \
> > tegra20-medcom-wide.dtb \
> > diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> > new file mode 100644
> > index 0000000..c6c19a9
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> > @@ -0,0 +1,155 @@
> > +/*
> > + * Copyright 2013 Maxime Ripard
> > + *
> > + * Maxime Ripard <[email protected]>
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +/include/ "skeleton.dtsi"
> > +
>
> [...]
>
> > + gic: interrupt-controller@01c81000 {
> > + compatible = "arm,cortex-a7-gic";
> > + reg = <0x01c81000 0x1000>, <0x01c82000 0x100>;
>
> Th Cortex A7 TRM indicates that its GIC has the virtualization
> extensions. You should reflect this in the binding (wider GICC range,
> GICH and GICV ranges, maintenance interrupt).
>
> See
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464d/BGBJFJJA.html
> for details.

Thanks!

I'll add those to the v2.

Maxime

--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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