by Sebastian Hesselbarth

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Subject: [PATCH v2 8/8] ARM: add initial support for Marvell Berlin SoCs

This adds initial support for the Marvell Berlin (88DE3xxx) SoC family
and basic machine setup for Armada 1500 (88DE3100) SoCs.

Signed-off-by: Sebastian Hesselbarth <[email protected]>
Reviewed-by: Jason Cooper <[email protected]>
Reviewed-by: Thomas Petazzoni <[email protected]>
Reviewed-by: Arnd Bergmann <[email protected]>
---
Changelog:
v1->v2:
- replace 88DE3xxx numbering with SoC variant name
(Requested by Jisheng Zhang)
- remove LOCAL_TIMERS dependency (Suggested by Dinh Nguyen)
RFCv2->v1:
- remove custom .init_time, adds dependency for arch-wide of_clk_init call
RFCv1->RFCv2:
- nuke .map_io (Reported by Arnd Bergmann)
- add copyright reference
- switch to mach-berlin instead of mach-mvebu

Cc: Jason Cooper <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Russell King <[email protected]>
Cc: Jisheng Zhang <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
arch/arm/Kconfig | 2 ++
arch/arm/Makefile | 1 +
arch/arm/mach-berlin/Kconfig | 23 +++++++++++++++++++++++
arch/arm/mach-berlin/Makefile | 1 +
arch/arm/mach-berlin/berlin.c | 39 +++++++++++++++++++++++++++++++++++++++
5 files changed, 66 insertions(+)
create mode 100644 arch/arm/mach-berlin/Kconfig
create mode 100644 arch/arm/mach-berlin/Makefile
create mode 100644 arch/arm/mach-berlin/berlin.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1ad6fb6..5692426 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -932,6 +932,8 @@ source "arch/arm/mach-bcm/Kconfig"

source "arch/arm/mach-bcm2835/Kconfig"

+source "arch/arm/mach-berlin/Kconfig"
+
source "arch/arm/mach-clps711x/Kconfig"

source "arch/arm/mach-cns3xxx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a37a50f..3ba332b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -147,6 +147,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM) += bcm
machine-$(CONFIG_ARCH_BCM2835) += bcm2835
+machine-$(CONFIG_ARCH_BERLIN) += berlin
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) += davinci
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
new file mode 100644
index 0000000..bdd5383
--- /dev/null
+++ b/arch/arm/mach-berlin/Kconfig
@@ -0,0 +1,23 @@
+config ARCH_BERLIN
+ bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_IRQ_CHIP
+ select COMMON_CLK
+ select DW_APB_ICTL
+ select DW_APB_TIMER_OF
+
+if ARCH_BERLIN
+
+menu "Marvell Berlin SoC variants"
+
+config MACH_BERLIN_BG2
+ bool "Marvell Armada 1500 (BG2)"
+ select ARM_GIC
+ select CACHE_L2X0
+ select CPU_PJ4B
+ select HAVE_ARM_TWD if SMP
+ select HAVE_SMP
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-berlin/Makefile b/arch/arm/mach-berlin/Makefile
new file mode 100644
index 0000000..ab69fe9
--- /dev/null
+++ b/arch/arm/mach-berlin/Makefile
@@ -0,0 +1 @@
+obj-y += berlin.o
diff --git a/arch/arm/mach-berlin/berlin.c b/arch/arm/mach-berlin/berlin.c
new file mode 100644
index 0000000..16c2942
--- /dev/null
+++ b/arch/arm/mach-berlin/berlin.c
@@ -0,0 +1,39 @@
+/*
+ * Device Tree support for Marvell Berlin SoCs.
+ *
+ * Sebastian Hesselbarth <[email protected]>
+ *
+ * based on GPL'ed 2.6 kernel sources
+ * (c) Marvell International Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+
+static void __init berlin_init_machine(void)
+{
+ /*
+ * with DT probing for L2CCs, berlin_init_machine can be removed.
+ * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
+ */
+ l2x0_of_init(0x70c00000, 0xfeffffff);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const berlin_dt_compat[] = {
+ "marvell,berlin",
+ NULL,
+};
+
+DT_MACHINE_START(BERLIN_DT, "Marvell Berlin")
+ .dt_compat = berlin_dt_compat,
+ .init_machine = berlin_init_machine,
+MACHINE_END
--
1.7.10.4

2013-10-25 21:31:06

by Sebastian Hesselbarth

[permalink] [raw]

Subject: Re: [PATCH v2 1/8] irqchip: add DesignWare APB ICTL interrupt controller

On 10/17/2013 07:37 AM, Sebastian Hesselbarth wrote:
> This adds an irqchip driver and corresponding devicetree binding for the
> secondary interrupt controllers based on Synopsys DesignWare IP dw_apb_ictl.
>
> Signed-off-by: Sebastian Hesselbarth <[email protected]>
> Reviewed-by: Mark Rutland <[email protected]>
> Reviewed-by: Jisheng Zhang <[email protected]>

Thomas (tglx),

can you please look at this and review it? IIRC, Olof already closed
the arm-soc merge window for v3.13, so there is plenty of time to get
this straight. Nevertheless, it would be great to have it in early in
v3.13.

Also, I prefer to have Mark look at the bindings again and maybe
update his remarks with the latest conclusions of KS.

Regards,
Sebastian

> ---
> Changelog:
> v1->v2:
> - reword binding docu for reg property and add FIQ decoding note
> (Suggested by Mark Rutland)
> - add cleanup on error path (Reported by Jisheng Zhang)
> RFCv1->RFCv2:
> - added copyright reference
>
> Cc: Jason Cooper <[email protected]>
> Cc: Thomas Petazzoni <[email protected]>
> Cc: Arnd Bergmann <[email protected]>
> Cc: Thomas Gleixner <[email protected]>
> Cc: Mark Rutland <[email protected]>
> Cc: Jisheng Zhang <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> .../interrupt-controller/snps,dw-apb-ictl.txt | 32 +++++
> drivers/irqchip/Kconfig | 4 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-dw-apb-ictl.c | 150 ++++++++++++++++++++
> 4 files changed, 187 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> create mode 100644 drivers/irqchip/irq-dw-apb-ictl.c
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> new file mode 100644
> index 0000000..4929117
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt
> @@ -0,0 +1,32 @@
> +Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
> +
> +Synopsys DesignWare provides interrupt controller IP for APB known as
> +dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
> +APB bus, e.g. Marvell Armada 1500.
> +
> +Required properties:
> +- compatible: shall be "snps,dw-apb-ictl"
> +- reg: physical base address of the controller and length of memory mapped
> + region starting with ENABLE_LOW register
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
> +- interrupts: interrupt reference to primary interrupt controller
> +- interrupt-parent: (optional) reference specific primary interrupt controller
> +
> +The interrupt sources map to the corresponding bits in the interrupt
> +registers, i.e.
> +- 0 maps to bit 0 of low interrupts,
> +- 1 maps to bit 1 of low interrupts,
> +- 32 maps to bit 0 of high interrupts,
> +- 33 maps to bit 1 of high interrupts,
> +- (optional) fast interrupts start at 64.
> +
> +Example:
> + aic: interrupt-controller@3000 {
> + compatible = "snps,dw-apb-ictl";
> + reg = <0x3000 0xc00>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + };
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 3792a1a..940638d 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -30,6 +30,10 @@ config ARM_VIC_NR
> The maximum number of VICs available in the system, for
> power management.
>
> +config DW_APB_ICTL
> + bool
> + select IRQ_DOMAIN
> +
> config IMGPDC_IRQ
> bool
> select GENERIC_IRQ_CHIP
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index c60b901..6427323 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
> obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
> obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
> obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
> +obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
> obj-$(CONFIG_METAG) += irq-metag-ext.o
> obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
> obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o
> diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c
> new file mode 100644
> index 0000000..31e231e
> --- /dev/null
> +++ b/drivers/irqchip/irq-dw-apb-ictl.c
> @@ -0,0 +1,150 @@
> +/*
> + * Synopsys DW APB ICTL irqchip driver.
> + *
> + * Sebastian Hesselbarth <[email protected]>
> + *
> + * based on GPL'ed 2.6 kernel sources
> + * (c) Marvell International Ltd.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip/chained_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#include "irqchip.h"
> +
> +#define APB_INT_ENABLE_L 0x00
> +#define APB_INT_ENABLE_H 0x04
> +#define APB_INT_MASK_L 0x08
> +#define APB_INT_MASK_H 0x0c
> +#define APB_INT_FINALSTATUS_L 0x30
> +#define APB_INT_FINALSTATUS_H 0x34
> +
> +static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
> +{
> + struct irq_chip *chip = irq_get_chip(irq);
> + struct irq_chip_generic *gc = irq_get_handler_data(irq);
> + struct irq_domain *d = gc->private;
> + u32 stat;
> + int n;
> +
> + chained_irq_enter(chip, desc);
> +
> + for (n = 0; n < gc->num_ct; n++) {
> + stat = readl_relaxed(gc->reg_base +
> + APB_INT_FINALSTATUS_L + 4 * n);
> + while (stat) {
> + u32 hwirq = ffs(stat) - 1;
> + generic_handle_irq(irq_find_mapping(d,
> + gc->irq_base + hwirq + 32 * n));
> + stat &= ~(1 << hwirq);
> + }
> + }
> +
> + chained_irq_exit(chip, desc);
> +}
> +
> +static int __init dw_apb_ictl_init(struct device_node *np,
> + struct device_node *parent)
> +{
> + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
> + struct resource r;
> + struct irq_domain *domain;
> + struct irq_chip_generic *gc;
> + void __iomem *iobase;
> + int ret, nrirqs, irq;
> + u32 reg;
> +
> + /* Map the parent interrupt for the chained handler */
> + irq = irq_of_parse_and_map(np, 0);
> + if (irq <= 0) {
> + pr_err("%s: unable to parse irq\n", np->full_name);
> + return -EINVAL;
> + }
> +
> + ret = of_address_to_resource(np, 0, &r);
> + if (ret) {
> + pr_err("%s: unable to get resource\n", np->full_name);
> + return ret;
> + }
> +
> + if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
> + pr_err("%s: unable to request mem region\n", np->full_name);
> + return -ENOMEM;
> + }
> +
> + iobase = ioremap(r.start, resource_size(&r));
> + if (!iobase) {
> + pr_err("%s: unable to map resource\n", np->full_name);
> + ret = -ENOMEM;
> + goto err_release;
> + }
> +
> + /*
> + * DW IP can be configured to allow 2-64 irqs. We can determine
> + * the number of irqs supported by writing into enable register
> + * and look for bits not set, as corresponding flip-flops will
> + * have been removed by sythesis tool.
> + */
> +
> + /* mask and enable all interrupts */
> + writel(~0, iobase + APB_INT_MASK_L);
> + writel(~0, iobase + APB_INT_MASK_H);
> + writel(~0, iobase + APB_INT_ENABLE_L);
> + writel(~0, iobase + APB_INT_ENABLE_H);
> +
> + reg = readl(iobase + APB_INT_ENABLE_H);
> + if (reg)
> + nrirqs = 32 + fls(reg);
> + else
> + nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
> +
> + domain = irq_domain_add_linear(np, nrirqs,
> + &irq_generic_chip_ops, NULL);
> + if (!domain) {
> + pr_err("%s: unable to add irq domain\n", np->full_name);
> + ret = -ENOMEM;
> + goto err_unmap;
> + }
> +
> + ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,
> + np->name, handle_level_irq, clr, 0,
> + IRQ_GC_INIT_MASK_CACHE);
> + if (ret) {
> + pr_err("%s: unable to alloc irq domain gc\n", np->full_name);
> + goto err_unmap;
> + }
> +
> + gc = irq_get_domain_generic_chip(domain, 0);
> + gc->private = domain;
> + gc->reg_base = iobase;
> +
> + gc->chip_types[0].regs.mask = APB_INT_MASK_L;
> + gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
> + gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
> +
> + if (nrirqs > 32) {
> + gc->chip_types[1].regs.mask = APB_INT_MASK_H;
> + gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
> + gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
> + }
> +
> + irq_set_handler_data(irq, gc);
> + irq_set_chained_handler(irq, dw_apb_ictl_handler);
> +
> + return 0;
> +
> +err_unmap:
> + iounmap(iobase);
> +err_release:
> + release_mem_region(r.start, resource_size(&r));
> + return ret;
> +}
> +IRQCHIP_DECLARE(dw_apb_ictl,
> + "snps,dw-apb-ictl", dw_apb_ictl_init);
>