First three patches are improvement and fixes for SPEAr13xx support.
Patches 4-6 add miphy40lp skelten driver and support for spear1310/40 miphy
wrapper. Patch 7 add support for SPEAr13xx PCIe.
These pathes are tested with linux-3.14-rc1 with following patch on the top of
it:
Author: Balaji T K <[email protected]>
Date: Mon Jan 20 16:41:27 2014 +0200
ata: ahci_platform: Manage SATA PHY
Tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Modifications for SATA are tested with SPEAr1340-evb board
Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3
Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall()
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g.
pcie designware driver improvements,fixes for IO translation bug, PCIe dw
driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA
platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.
PCIe driver support for SPEAr1310/40 platform board is added.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Mohit Kumar (2):
SPEAr13xx: defconfig: Update
MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
Pratyush Anand (6):
clk: SPEAr13xx: Fix pcie clock name
SPEAr13xx: Fix static mapping table
phy: st-miphy-40lp: Add skeleton driver
SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
pcie: SPEAr13xx: Add designware pcie support
.../devicetree/bindings/arm/spear-misc.txt | 4 +
.../devicetree/bindings/pci/spear13xx-pcie.txt | 7 +
.../devicetree/bindings/phy/st-miphy40lp.txt | 12 +
MAINTAINERS | 6 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 96 +++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 32 +-
arch/arm/boot/dts/spear13xx.dtsi | 10 +-
arch/arm/configs/spear13xx_defconfig | 15 +
arch/arm/mach-spear/Kconfig | 3 +
arch/arm/mach-spear/include/mach/spear.h | 4 +-
arch/arm/mach-spear/spear1340.c | 127 +----
arch/arm/mach-spear/spear13xx.c | 2 +-
drivers/clk/spear/spear1310_clock.c | 6 +-
drivers/clk/spear/spear1340_clock.c | 2 +-
drivers/pci/host/Kconfig | 5 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pcie-spear13xx.c | 414 ++++++++++++++++
drivers/phy/Kconfig | 6 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-miphy40lp.c | 544 +++++++++++++++++++++
22 files changed, 1166 insertions(+), 139 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
create mode 100644 drivers/pci/host/pcie-spear13xx.c
create mode 100644 drivers/phy/phy-miphy40lp.c
--
1.8.1.2
ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
skeleton support for the same.
Currently phy ops are returning -EINVAL. They can be elaborated
depending on the SOC being supported in future.
Signed-off-by: Pratyush Anand <[email protected]>
Tested-by: Mohit Kumar <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++
drivers/phy/Kconfig | 6 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++
4 files changed, 193 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
create mode 100644 drivers/phy/phy-miphy40lp.c
diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
new file mode 100644
index 0000000..d0c7096
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
@@ -0,0 +1,12 @@
+Required properties:
+- compatible : should be "st,miphy40lp-phy"
+ Other supported soc specific compatible:
+ "st,spear1310-miphy"
+ "st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- phy-id: Instance id of the phy.
+- #phy-cells : from the generic PHY bindings, must be 1.
+ - 1st cell: phandle to the phy node.
+ - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
+ and 2 for Super Speed USB.
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afa2354..2f58993 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
help
Enable this to support the Broadcom Kona USB 2.0 PHY.
+config PHY_ST_MIPHY40LP
+ tristate "ST MIPHY 40LP driver"
+ help
+ Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
+ select GENERIC_PHY
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..c061091 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
new file mode 100644
index 0000000..d478c14
--- /dev/null
+++ b/drivers/phy/phy-miphy40lp.c
@@ -0,0 +1,174 @@
+/*
+ * ST MiPHY-40LP PHY driver
+ *
+ * Copyright (C) 2014 ST Microelectronics
+ * Pratyush Anand <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+enum phy_mode {
+ SATA,
+ PCIE,
+ SS_USB,
+};
+
+struct st_miphy40lp_priv {
+ /* regmap for any soc specific misc registers */
+ struct regmap *misc;
+ /* phy struct pointer */
+ struct phy *phy;
+ /* device node pointer */
+ struct device_node *np;
+ /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
+ enum phy_mode mode;
+ /* instance id of this phy */
+ u32 id;
+};
+
+static int miphy40lp_init(struct phy *phy)
+{
+ return -EINVAL;
+}
+
+static int miphy40lp_exit(struct phy *phy)
+{
+ return -EINVAL;
+}
+
+static int miphy40lp_power_off(struct phy *phy)
+{
+ return -EINVAL;
+}
+
+static int miphy40lp_power_on(struct phy *phy)
+{
+ return -EINVAL;
+}
+
+static const struct of_device_id st_miphy40lp_of_match[] = {
+ { .compatible = "st,miphy40lp-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
+
+static struct phy_ops st_miphy40lp_ops = {
+ .init = miphy40lp_init,
+ .exit = miphy40lp_exit,
+ .power_off = miphy40lp_power_off,
+ .power_on = miphy40lp_power_on,
+ .owner = THIS_MODULE,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int miphy40lp_suspend(struct device *dev)
+{
+ return -EINVAL;
+}
+
+static int miphy40lp_resume(struct device *dev)
+{
+ return -EINVAL;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
+ miphy40lp_resume);
+
+static struct phy *st_miphy40lp_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+ if (args->args_count < 1) {
+ dev_err(dev, "DT did not pass correct no of args\n");
+ return NULL;
+ }
+
+ phypriv->mode = args->args[0];
+
+ return phypriv->phy;
+}
+
+static int __init st_miphy40lp_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct st_miphy40lp_priv *phypriv;
+ struct phy_provider *phy_provider;
+
+ phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
+ if (!phypriv) {
+ dev_err(dev, "can't alloc miphy40lp private date memory\n");
+ return -ENOMEM;
+ }
+
+ phypriv->np = dev->of_node;
+
+ phypriv->misc =
+ syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
+ if (IS_ERR(phypriv->misc)) {
+ dev_err(dev, "failed to find misc regmap\n");
+ return PTR_ERR(phypriv->misc);
+ }
+
+ if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
+ dev_err(dev, "failed to find phy id\n");
+ return -EINVAL;
+ }
+
+ phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(dev, "failed to register phy provider\n");
+ return PTR_ERR(phy_provider);
+ }
+
+ phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
+ if (IS_ERR(phypriv->phy)) {
+ dev_err(dev, "failed to create SATA PCIe PHY\n");
+ return PTR_ERR(phypriv->phy);
+ }
+
+ dev_set_drvdata(dev, phypriv);
+ phy_set_drvdata(phypriv->phy, phypriv);
+
+ return 0;
+}
+
+static int __exit st_miphy40lp_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static struct platform_driver st_miphy40lp_driver = {
+ .remove = __exit_p(st_miphy40lp_remove),
+ .driver = {
+ .name = "miphy40lp-phy",
+ .owner = THIS_MODULE,
+ .pm = &miphy40lp_pm_ops,
+ .of_match_table = of_match_ptr(st_miphy40lp_of_match),
+ },
+};
+
+static int __init st_miphy40lp_init(void)
+{
+
+ return platform_driver_probe(&st_miphy40lp_driver,
+ st_miphy40lp_probe);
+}
+module_init(st_miphy40lp_init);
+
+MODULE_DESCRIPTION("ST MIPHY-40LP driver");
+MODULE_AUTHOR("Pratyush Anand <[email protected]>");
+MODULE_LICENSE("GPL v2");
--
1.8.1.2
SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds
support for the same.
Signed-off-by: Pratyush Anand <[email protected]>
Tested-by: Mohit Kumar <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/phy/phy-miphy40lp.c | 178 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 178 insertions(+)
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index cc7f45d..61e94be 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -9,6 +9,7 @@
* published by the Free Software Foundation.
*
* 04/02/2014: Adding support of SATA mode for SPEAr1340.
+ * 04/02/2014: Adding support of PCIe mode for SPEAr1340 and SPEAr1310
*/
#include <linux/delay.h>
@@ -73,6 +74,80 @@
#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+/* SPEAr1310 Registers */
+#define SPEAR1310_PCIE_SATA_CFG 0x3A4
+ #define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29)
+ #define SPEAR1310_PCIE_SATA2_SEL_SATA (1 << 31)
+ #define SPEAR1310_PCIE_SATA1_SEL_SATA (1 << 30)
+ #define SPEAR1310_PCIE_SATA0_SEL_SATA (1 << 29)
+ #define SPEAR1310_SATA2_CFG_TX_CLK_EN (1 << 27)
+ #define SPEAR1310_SATA2_CFG_RX_CLK_EN (1 << 26)
+ #define SPEAR1310_SATA2_CFG_POWERUP_RESET (1 << 25)
+ #define SPEAR1310_SATA2_CFG_PM_CLK_EN (1 << 24)
+ #define SPEAR1310_SATA1_CFG_TX_CLK_EN (1 << 23)
+ #define SPEAR1310_SATA1_CFG_RX_CLK_EN (1 << 22)
+ #define SPEAR1310_SATA1_CFG_POWERUP_RESET (1 << 21)
+ #define SPEAR1310_SATA1_CFG_PM_CLK_EN (1 << 20)
+ #define SPEAR1310_SATA0_CFG_TX_CLK_EN (1 << 19)
+ #define SPEAR1310_SATA0_CFG_RX_CLK_EN (1 << 18)
+ #define SPEAR1310_SATA0_CFG_POWERUP_RESET (1 << 17)
+ #define SPEAR1310_SATA0_CFG_PM_CLK_EN (1 << 16)
+ #define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT (1 << 11)
+ #define SPEAR1310_PCIE2_CFG_POWERUP_RESET (1 << 10)
+ #define SPEAR1310_PCIE2_CFG_CORE_CLK_EN (1 << 9)
+ #define SPEAR1310_PCIE2_CFG_AUX_CLK_EN (1 << 8)
+ #define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT (1 << 7)
+ #define SPEAR1310_PCIE1_CFG_POWERUP_RESET (1 << 6)
+ #define SPEAR1310_PCIE1_CFG_CORE_CLK_EN (1 << 5)
+ #define SPEAR1310_PCIE1_CFG_AUX_CLK_EN (1 << 4)
+ #define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT (1 << 3)
+ #define SPEAR1310_PCIE0_CFG_POWERUP_RESET (1 << 2)
+ #define SPEAR1310_PCIE0_CFG_CORE_CLK_EN (1 << 1)
+ #define SPEAR1310_PCIE0_CFG_AUX_CLK_EN (1 << 0)
+
+ #define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | (1 << (x + 29)))
+ #define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+ (1 << (x + 29)))
+ #define SPEAR1310_PCIE_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+ SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+ SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+ #define SPEAR1310_SATA_CFG_VAL(x) \
+ (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+ SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+ SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+ SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8
+ #define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT (1 << 31)
+ #define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 (1 << 28)
+ #define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x) (x << 16)
+ #define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT (1 << 15)
+ #define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 (1 << 12)
+ #define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+ #define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+ SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+ SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3AC
enum phy_mode {
SATA,
@@ -181,6 +256,104 @@ static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
return -EINVAL;
}
+static int spear1340_pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_PCIE_CFG_VAL);
+
+ return 0;
+}
+
+static int spear1340_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+ return 0;
+}
+
+static int spear1310_pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ u32 mask, val;
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE);
+
+ switch (phypriv->id) {
+ case 0:
+ mask = SPEAR1310_PCIE_CFG_MASK(0);
+ val = SPEAR1310_PCIE_CFG_VAL(0);
+ break;
+ case 1:
+ mask = SPEAR1310_PCIE_CFG_MASK(1);
+ val = SPEAR1310_PCIE_CFG_VAL(1);
+ break;
+ case 2:
+ mask = SPEAR1310_PCIE_CFG_MASK(2);
+ val = SPEAR1310_PCIE_CFG_VAL(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG, mask, val);
+
+ return 0;
+}
+
+static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ u32 mask;
+
+ switch (phypriv->id) {
+ case 0:
+ mask = SPEAR1310_PCIE_CFG_MASK(0);
+ break;
+ case 1:
+ mask = SPEAR1310_PCIE_CFG_MASK(1);
+ break;
+ case 2:
+ mask = SPEAR1310_PCIE_CFG_MASK(2);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
+ SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
+
+ regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
+ SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
+
+ return 0;
+}
+
+static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_pcie_miphy_init(phypriv);
+ else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
+ return spear1310_pcie_miphy_init(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_pcie_miphy_exit(phypriv);
+ else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
+ return spear1310_pcie_miphy_exit(phypriv);
+ else
+ return -EINVAL;
+}
+
static int miphy40lp_init(struct phy *phy)
{
struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
@@ -188,6 +361,8 @@ static int miphy40lp_init(struct phy *phy)
switch (phypriv->mode) {
case SATA:
return sata_miphy_init(phypriv);
+ case PCIE:
+ return pcie_miphy_init(phypriv);
default:
return -EINVAL;
}
@@ -200,6 +375,8 @@ static int miphy40lp_exit(struct phy *phy)
switch (phypriv->mode) {
case SATA:
return sata_miphy_exit(phypriv);
+ case PCIE:
+ return pcie_miphy_exit(phypriv);
default:
return -EINVAL;
}
@@ -232,6 +409,7 @@ static int miphy40lp_power_on(struct phy *phy)
static const struct of_device_id st_miphy40lp_of_match[] = {
{ .compatible = "st,miphy40lp-phy" },
{ .compatible = "st,spear1340-miphy" },
+ { .compatible = "st,spear1310-miphy" },
{ },
};
MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
--
1.8.1.2
ahci driver needs some platform specific functions which are called at
init, exit, suspend and resume conditions. Till now these functions were
present in a platform driver with a fixme notes.
Similar functions modifying same set of registers will also be needed in
case of PCIe phy init/exit.
So move all these SATA platform code to phy-miphy40lp driver.
Signed-off-by: Pratyush Anand <[email protected]>
Tested-by: Mohit Kumar <[email protected]>
Cc: Viresh Kumar <[email protected]>
Cc: Tejun Heo <[email protected]>
Cc: Arnd Bergmann <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../devicetree/bindings/arm/spear-misc.txt | 4 +
arch/arm/boot/dts/spear1310-evb.dts | 4 +
arch/arm/boot/dts/spear1310.dtsi | 39 +++-
arch/arm/boot/dts/spear1340-evb.dts | 4 +
arch/arm/boot/dts/spear1340.dtsi | 13 +-
arch/arm/boot/dts/spear13xx.dtsi | 5 +
arch/arm/mach-spear/Kconfig | 2 +
arch/arm/mach-spear/spear1340.c | 127 +------------
drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
9 files changed, 266 insertions(+), 136 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
diff --git a/Documentation/devicetree/bindings/arm/spear-misc.txt b/Documentation/devicetree/bindings/arm/spear-misc.txt
new file mode 100644
index 0000000..aacd36a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear-misc.txt
@@ -0,0 +1,4 @@
+* SPEAr Misc configuration
+** misc node required properties:
+- compatible Should be "st,spear1340-misc", "syscon".
+- reg: Address range of misc space
diff --git a/arch/arm/boot/dts/spear1310-evb.dts b/arch/arm/boot/dts/spear1310-evb.dts
index b56a801..d42c84b 100644
--- a/arch/arm/boot/dts/spear1310-evb.dts
+++ b/arch/arm/boot/dts/spear1310-evb.dts
@@ -106,6 +106,10 @@
status = "okay";
};
+ miphy@eb800000 {
+ status = "okay";
+ };
+
cf@b2800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 122ae94..64e7dd5 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -29,24 +29,57 @@
#gpio-cells = <2>;
};
- ahci@b1000000 {
+ miphy0: miphy@eb800000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ phy-id = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ miphy1: miphy@eb804000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb804000 0x4000>;
+ misc = <&misc>;
+ phy-id = <1>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ miphy2: miphy@eb808000 {
+ compatible = "st,miphy", "st,spear1310-miphy";
+ reg = <0xeb808000 0x4000>;
+ misc = <&misc>;
+ phy-id = <2>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ ahci0: ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 68 0x4>;
+ phys = <&miphy0 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
- ahci@b1800000 {
+ ahci1: ahci@b1800000 {
compatible = "snps,spear-ahci";
reg = <0xb1800000 0x10000>;
interrupts = <0 69 0x4>;
+ phys = <&miphy1 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
- ahci@b4000000 {
+ ahci2: ahci@b4000000 {
compatible = "snps,spear-ahci";
reg = <0xb4000000 0x10000>;
interrupts = <0 70 0x4>;
+ phys = <&miphy2 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear1340-evb.dts b/arch/arm/boot/dts/spear1340-evb.dts
index d6c30ae..b23e05e 100644
--- a/arch/arm/boot/dts/spear1340-evb.dts
+++ b/arch/arm/boot/dts/spear1340-evb.dts
@@ -122,6 +122,10 @@
status = "okay";
};
+ miphy@eb800000 {
+ status = "okay";
+ };
+
dma@ea800000 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 54d128d..7e3a04b 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -31,10 +31,21 @@
status = "disabled";
};
- ahci@b1000000 {
+ miphy0: miphy@eb800000 {
+ compatible = "st,miphy", "st,spear1340-miphy";
+ reg = <0xeb800000 0x4000>;
+ misc = <&misc>;
+ phy-id = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ ahci0: ahci@b1000000 {
compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>;
interrupts = <0 72 0x4>;
+ phys = <&miphy0 0>;
+ phy-names = "sata-phy";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3a72508 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -220,6 +220,11 @@
0xd8000000 0xd8000000 0x01000000
0xe0000000 0xe0000000 0x10000000>;
+ misc: syscon@e0700000 {
+ compatible = "st,spear1340-misc", "syscon";
+ reg = <0xe0700000 0x1000>;
+ };
+
gpio0: gpio@e0600000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xe0600000 0x1000>;
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e6..7e7f1b0 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select USE_OF
+ select MFD_SYSCON
+ select PHY_ST_MIPHY40LP
help
Supports for ARM's SPEAR13XX family
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..8e27093 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -11,138 +11,13 @@
* warranty of any kind, whether express or implied.
*/
-#define pr_fmt(fmt) "SPEAr1340: " fmt
-
-#include <linux/ahci_platform.h>
-#include <linux/amba/serial.h>
-#include <linux/delay.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "generic.h"
-#include <mach/spear.h>
-
-/* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG (VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG (VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR (VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST (VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST (VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST (VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG (VA_MISC_BASE + 0x424)
- /* PCIE CFG MASks */
- #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
- #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
- #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
- #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
- #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
- #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
- #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
- #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
- #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
- #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
- #define SPEAR1340_SATA_PCIE_CFG_MASK 0xF1F
- #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
- SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
- SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
- SPEAR1340_PCIE_CFG_POWERUP_RESET | \
- SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
- #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
- SPEAR1340_SATA_CFG_PM_CLK_EN | \
- SPEAR1340_SATA_CFG_POWERUP_RESET | \
- SPEAR1340_SATA_CFG_RX_CLK_EN | \
- SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG (VA_MISC_BASE + 0x428)
- #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
- #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
- #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
- #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_CLK_REF_DIV2 | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
- (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
- #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
- (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
- SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
-/* SATA device registration */
-static int sata_miphy_init(struct device *dev, void __iomem *addr)
-{
- writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
- writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
- SPEAR1340_PCIE_MIPHY_CFG);
- /* Switch on sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
- /* Disable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
-
- return 0;
-}
-
-void sata_miphy_exit(struct device *dev)
-{
- writel(0, SPEAR1340_PCIE_SATA_CFG);
- writel(0, SPEAR1340_PCIE_MIPHY_CFG);
-
- /* Enable PCIE SATA Controller reset */
- writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
- SPEAR1340_PERIP1_SW_RST);
- msleep(20);
- /* Switch off sata power domain */
- writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
- msleep(20);
-}
-
-int sata_suspend(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_FREEZE)
- return 0;
-
- sata_miphy_exit(dev);
-
- return 0;
-}
-
-int sata_resume(struct device *dev)
-{
- if (dev->power.power_state.event == PM_EVENT_THAW)
- return 0;
-
- return sata_miphy_init(dev, NULL);
-}
-
-static struct ahci_platform_data sata_pdata = {
- .init = sata_miphy_init,
- .exit = sata_miphy_exit,
- .suspend = sata_suspend,
- .resume = sata_resume,
-};
-
-/* Add SPEAr1340 auxdata to pass platform data */
-static struct of_dev_auxdata spear1340_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("snps,spear-ahci", SPEAR1340_SATA_BASE, NULL,
- &sata_pdata),
- {}
-};
static void __init spear1340_dt_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table,
- spear1340_auxdata_lookup, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const spear1340_dt_board_compat[] = {
diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
index d478c14..cc7f45d 100644
--- a/drivers/phy/phy-miphy40lp.c
+++ b/drivers/phy/phy-miphy40lp.c
@@ -8,6 +8,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
+ * 04/02/2014: Adding support of SATA mode for SPEAr1340.
*/
#include <linux/delay.h>
@@ -19,6 +20,60 @@
#include <linux/phy/phy.h>
#include <linux/regmap.h>
+/* SPEAr1340 Registers */
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG 0x100
+ #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
+#define SPEAR1340_PCM_WKUP_CFG 0x104
+#define SPEAR1340_SWITCH_CTR 0x108
+
+#define SPEAR1340_PERIP1_SW_RST 0x318
+ #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
+#define SPEAR1340_PERIP2_SW_RST 0x31C
+#define SPEAR1340_PERIP3_SW_RST 0x320
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG 0x424
+ /* PCIE CFG MASks */
+ #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
+ #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
+ #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
+ #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
+ #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
+ #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
+ #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
+ #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
+ #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
+ #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
+ #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
+ #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
+ SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+ SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+ SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+ SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+ #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
+ SPEAR1340_SATA_CFG_PM_CLK_EN | \
+ SPEAR1340_SATA_CFG_POWERUP_RESET | \
+ SPEAR1340_SATA_CFG_RX_CLK_EN | \
+ SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG 0x428
+ #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
+ #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
+ #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
+ #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+ (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+ #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+ SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
enum phy_mode {
SATA,
PCIE,
@@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
u32 id;
};
+static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK,
+ SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+ /* Switch on sata power domain */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN);
+ msleep(20);
+ /* Disable PCIE SATA Controller reset */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RST_SATA, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
+ SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+ SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+
+ /* Enable PCIE SATA Controller reset */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
+ SPEAR1340_PERIP1_SW_RST_SATA,
+ SPEAR1340_PERIP1_SW_RST_SATA);
+ msleep(20);
+ /* Switch off sata power domain */
+ regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
+ SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
+ msleep(20);
+
+ return 0;
+}
+
+static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_sata_miphy_init(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_sata_miphy_exit(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return 0;
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return 0;
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_sata_miphy_exit(phypriv);
+ else
+ return -EINVAL;
+}
+
+static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
+{
+ if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
+ return spear1340_sata_miphy_init(phypriv);
+ else
+ return -EINVAL;
+}
+
static int miphy40lp_init(struct phy *phy)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_init(phypriv);
+ default:
+ return -EINVAL;
+ }
}
static int miphy40lp_exit(struct phy *phy)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_exit(phypriv);
+ default:
+ return -EINVAL;
+ }
}
static int miphy40lp_power_off(struct phy *phy)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_power_off(phypriv);
+ default:
+ return -EINVAL;
+ }
}
static int miphy40lp_power_on(struct phy *phy)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_power_on(phypriv);
+ default:
+ return -EINVAL;
+ }
}
static const struct of_device_id st_miphy40lp_of_match[] = {
{ .compatible = "st,miphy40lp-phy" },
+ { .compatible = "st,spear1340-miphy" },
{ },
};
MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
@@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
#ifdef CONFIG_PM_SLEEP
static int miphy40lp_suspend(struct device *dev)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+ if (dev->power.power_state.event == PM_EVENT_FREEZE)
+ return 0;
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_suspend(phypriv);
+ default:
+ return -EINVAL;
+ }
}
static int miphy40lp_resume(struct device *dev)
{
- return -EINVAL;
+ struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
+
+ if (dev->power.power_state.event == PM_EVENT_THAW)
+ return 0;
+
+ switch (phypriv->mode) {
+ case SATA:
+ return sata_miphy_resume(phypriv);
+ default:
+ return -EINVAL;
+ }
}
#endif
--
1.8.1.2
Hi,
On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> skeleton support for the same.
>
> Currently phy ops are returning -EINVAL. They can be elaborated
> depending on the SOC being supported in future.
>
> Signed-off-by: Pratyush Anand <[email protected]>
> Tested-by: Mohit Kumar <[email protected]>
> Cc: Arnd Bergmann <[email protected]>
> Cc: Kishon Vijay Abraham I <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> .../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++
> drivers/phy/Kconfig | 6 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++
> 4 files changed, 193 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> create mode 100644 drivers/phy/phy-miphy40lp.c
>
> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> new file mode 100644
> index 0000000..d0c7096
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> @@ -0,0 +1,12 @@
> +Required properties:
> +- compatible : should be "st,miphy40lp-phy"
> + Other supported soc specific compatible:
> + "st,spear1310-miphy"
> + "st,spear1340-miphy"
> +- reg : offset and length of the PHY register set.
> +- misc: phandle for the syscon node to access misc registers
> +- phy-id: Instance id of the phy.
> +- #phy-cells : from the generic PHY bindings, must be 1.
> + - 1st cell: phandle to the phy node.
> + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> + and 2 for Super Speed USB.
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index afa2354..2f58993 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
> help
> Enable this to support the Broadcom Kona USB 2.0 PHY.
>
> +config PHY_ST_MIPHY40LP
> + tristate "ST MIPHY 40LP driver"
> + help
> + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> + select GENERIC_PHY
> +
> endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index b57c253..c061091 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
> obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
> +obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> new file mode 100644
> index 0000000..d478c14
> --- /dev/null
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -0,0 +1,174 @@
> +/*
> + * ST MiPHY-40LP PHY driver
> + *
> + * Copyright (C) 2014 ST Microelectronics
> + * Pratyush Anand <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +enum phy_mode {
> + SATA,
> + PCIE,
> + SS_USB,
> +};
> +
> +struct st_miphy40lp_priv {
> + /* regmap for any soc specific misc registers */
> + struct regmap *misc;
> + /* phy struct pointer */
> + struct phy *phy;
> + /* device node pointer */
> + struct device_node *np;
> + /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> + enum phy_mode mode;
> + /* instance id of this phy */
> + u32 id;
> +};
> +
> +static int miphy40lp_init(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_exit(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_power_off(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_power_on(struct phy *phy)
> +{
> + return -EINVAL;
> +}
> +
> +static const struct of_device_id st_miphy40lp_of_match[] = {
> + { .compatible = "st,miphy40lp-phy" },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> +
> +static struct phy_ops st_miphy40lp_ops = {
> + .init = miphy40lp_init,
> + .exit = miphy40lp_exit,
> + .power_off = miphy40lp_power_off,
> + .power_on = miphy40lp_power_on,
> + .owner = THIS_MODULE,
Would prefer to either align all the fields or align none. Here only owner is
aligned.
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int miphy40lp_suspend(struct device *dev)
> +{
> + return -EINVAL;
> +}
> +
> +static int miphy40lp_resume(struct device *dev)
> +{
> + return -EINVAL;
> +}
> +#endif
> +
> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> + miphy40lp_resume);
> +
> +static struct phy *st_miphy40lp_xlate(struct device *dev,
> + struct of_phandle_args *args)
> +{
> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> + if (args->args_count < 1) {
> + dev_err(dev, "DT did not pass correct no of args\n");
> + return NULL;
> + }
> +
> + phypriv->mode = args->args[0];
> +
> + return phypriv->phy;
> +}
> +
> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct st_miphy40lp_priv *phypriv;
> + struct phy_provider *phy_provider;
> +
> + phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> + if (!phypriv) {
> + dev_err(dev, "can't alloc miphy40lp private date memory\n");
> + return -ENOMEM;
> + }
> +
> + phypriv->np = dev->of_node;
> +
> + phypriv->misc =
> + syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> + if (IS_ERR(phypriv->misc)) {
> + dev_err(dev, "failed to find misc regmap\n");
> + return PTR_ERR(phypriv->misc);
> + }
> +
> + if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> + dev_err(dev, "failed to find phy id\n");
> + return -EINVAL;
> + }
Do we really need this phy id? How is it being used?
> +
> + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> + if (IS_ERR(phy_provider)) {
> + dev_err(dev, "failed to register phy provider\n");
> + return PTR_ERR(phy_provider);
> + }
phy_provider_register should be the last step in registering the PHY. Or your
PHY call backs can be called before you create the PHY. Btw in your case you
should call dev_set_drvdata before doing phy_provider_register.
> +
> + phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> + if (IS_ERR(phypriv->phy)) {
> + dev_err(dev, "failed to create SATA PCIe PHY\n");
> + return PTR_ERR(phypriv->phy);
> + }
> +
> + dev_set_drvdata(dev, phypriv);
> + phy_set_drvdata(phypriv->phy, phypriv);
> +
> + return 0;
> +}
> +
> +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> +{
> + return 0;
> +}
I think you can remove this empty 'remove' callback.
Thanks
Kishon
Hi Kishon,
On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
> > skeleton support for the same.
> >
> > Currently phy ops are returning -EINVAL. They can be elaborated
> > depending on the SOC being supported in future.
> >
> > Signed-off-by: Pratyush Anand <[email protected]>
> > Tested-by: Mohit Kumar <[email protected]>
> > Cc: Arnd Bergmann <[email protected]>
> > Cc: Kishon Vijay Abraham I <[email protected]>
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > ---
> > .../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++
> > drivers/phy/Kconfig | 6 +
> > drivers/phy/Makefile | 1 +
> > drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++
> > 4 files changed, 193 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > create mode 100644 drivers/phy/phy-miphy40lp.c
> >
> > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > new file mode 100644
> > index 0000000..d0c7096
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > @@ -0,0 +1,12 @@
> > +Required properties:
> > +- compatible : should be "st,miphy40lp-phy"
> > + Other supported soc specific compatible:
> > + "st,spear1310-miphy"
> > + "st,spear1340-miphy"
> > +- reg : offset and length of the PHY register set.
> > +- misc: phandle for the syscon node to access misc registers
> > +- phy-id: Instance id of the phy.
> > +- #phy-cells : from the generic PHY bindings, must be 1.
> > + - 1st cell: phandle to the phy node.
> > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > + and 2 for Super Speed USB.
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index afa2354..2f58993 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
> > help
> > Enable this to support the Broadcom Kona USB 2.0 PHY.
> >
> > +config PHY_ST_MIPHY40LP
> > + tristate "ST MIPHY 40LP driver"
> > + help
> > + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
> > + select GENERIC_PHY
> > +
> > endmenu
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index b57c253..c061091 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
> > obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
> > obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
> > obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
> > +obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > new file mode 100644
> > index 0000000..d478c14
> > --- /dev/null
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -0,0 +1,174 @@
> > +/*
> > + * ST MiPHY-40LP PHY driver
> > + *
> > + * Copyright (C) 2014 ST Microelectronics
> > + * Pratyush Anand <[email protected]>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/regmap.h>
> > +
> > +enum phy_mode {
> > + SATA,
> > + PCIE,
> > + SS_USB,
> > +};
> > +
> > +struct st_miphy40lp_priv {
> > + /* regmap for any soc specific misc registers */
> > + struct regmap *misc;
> > + /* phy struct pointer */
> > + struct phy *phy;
> > + /* device node pointer */
> > + struct device_node *np;
> > + /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
> > + enum phy_mode mode;
> > + /* instance id of this phy */
> > + u32 id;
> > +};
> > +
> > +static int miphy40lp_init(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_exit(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_off(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_power_on(struct phy *phy)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static const struct of_device_id st_miphy40lp_of_match[] = {
> > + { .compatible = "st,miphy40lp-phy" },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > +
> > +static struct phy_ops st_miphy40lp_ops = {
> > + .init = miphy40lp_init,
> > + .exit = miphy40lp_exit,
> > + .power_off = miphy40lp_power_off,
> > + .power_on = miphy40lp_power_on,
> > + .owner = THIS_MODULE,
>
> Would prefer to either align all the fields or align none. Here only owner is
> aligned.
ok.
> > +};
> > +
> > +#ifdef CONFIG_PM_SLEEP
> > +static int miphy40lp_suspend(struct device *dev)
> > +{
> > + return -EINVAL;
> > +}
> > +
> > +static int miphy40lp_resume(struct device *dev)
> > +{
> > + return -EINVAL;
> > +}
> > +#endif
> > +
> > +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
> > + miphy40lp_resume);
> > +
> > +static struct phy *st_miphy40lp_xlate(struct device *dev,
> > + struct of_phandle_args *args)
> > +{
> > + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > + if (args->args_count < 1) {
> > + dev_err(dev, "DT did not pass correct no of args\n");
> > + return NULL;
> > + }
> > +
> > + phypriv->mode = args->args[0];
> > +
> > + return phypriv->phy;
> > +}
> > +
> > +static int __init st_miphy40lp_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct st_miphy40lp_priv *phypriv;
> > + struct phy_provider *phy_provider;
> > +
> > + phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
> > + if (!phypriv) {
> > + dev_err(dev, "can't alloc miphy40lp private date memory\n");
> > + return -ENOMEM;
> > + }
> > +
> > + phypriv->np = dev->of_node;
> > +
> > + phypriv->misc =
> > + syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
> > + if (IS_ERR(phypriv->misc)) {
> > + dev_err(dev, "failed to find misc regmap\n");
> > + return PTR_ERR(phypriv->misc);
> > + }
> > +
> > + if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
> > + dev_err(dev, "failed to find phy id\n");
> > + return -EINVAL;
> > + }
> Do we really need this phy id? How is it being used?
Yes , it is being used by patch 6/8.
>
> > +
> > + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> > + if (IS_ERR(phy_provider)) {
> > + dev_err(dev, "failed to register phy provider\n");
> > + return PTR_ERR(phy_provider);
> > + }
>
> phy_provider_register should be the last step in registering the PHY. Or your
> PHY call backs can be called before you create the PHY. Btw in your case you
But every one else like phy-exynos-mipi-video or phy-omap-usb2 or any
other did it same way. First phy_provider_register and then
phy_create.
> should call dev_set_drvdata before doing phy_provider_register.
yes, I need to correct it.
> > +
> > + phypriv->phy = devm_phy_create(dev, &st_miphy40lp_ops, NULL);
> > + if (IS_ERR(phypriv->phy)) {
> > + dev_err(dev, "failed to create SATA PCIe PHY\n");
> > + return PTR_ERR(phypriv->phy);
> > + }
> > +
> > + dev_set_drvdata(dev, phypriv);
> > + phy_set_drvdata(phypriv->phy, phypriv);
> > +
> > + return 0;
> > +}
> > +
> > +static int __exit st_miphy40lp_remove(struct platform_device *pdev)
> > +{
> > + return 0;
> > +}
>
> I think you can remove this empty 'remove' callback.
Yaa.. Can be removed.
Rgds
Pratyush
>
> Thanks
> Kishon
Hi,
On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> Hi Kishon,
>
> On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
>>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
>>> skeleton support for the same.
>>>
>>> Currently phy ops are returning -EINVAL. They can be elaborated
>>> depending on the SOC being supported in future.
>>>
>>> Signed-off-by: Pratyush Anand <[email protected]>
>>> Tested-by: Mohit Kumar <[email protected]>
>>> Cc: Arnd Bergmann <[email protected]>
>>> Cc: Kishon Vijay Abraham I <[email protected]>
>>> Cc: [email protected]
>>> Cc: [email protected]
>>> Cc: [email protected]
>>> Cc: [email protected]
>>> ---
>>> .../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++
>>> drivers/phy/Kconfig | 6 +
>>> drivers/phy/Makefile | 1 +
>>> drivers/phy/phy-miphy40lp.c | 174 +++++++++++++++++++++
>>> 4 files changed, 193 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> create mode 100644 drivers/phy/phy-miphy40lp.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> new file mode 100644
>>> index 0000000..d0c7096
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
>>> @@ -0,0 +1,12 @@
>>> +Required properties:
>>> +- compatible : should be "st,miphy40lp-phy"
>>> + Other supported soc specific compatible:
>>> + "st,spear1310-miphy"
>>> + "st,spear1340-miphy"
>>> +- reg : offset and length of the PHY register set.
>>> +- misc: phandle for the syscon node to access misc registers
>>> +- phy-id: Instance id of the phy.
>>> +- #phy-cells : from the generic PHY bindings, must be 1.
>>> + - 1st cell: phandle to the phy node.
>>> + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
>>> + and 2 for Super Speed USB.
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index afa2354..2f58993 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY
>>> help
>>> Enable this to support the Broadcom Kona USB 2.0 PHY.
>>>
>>> +config PHY_ST_MIPHY40LP
>>> + tristate "ST MIPHY 40LP driver"
>>> + help
>>> + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB.
>>> + select GENERIC_PHY
>>> +
>>> endmenu
>>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>>> index b57c253..c061091 100644
>>> --- a/drivers/phy/Makefile
>>> +++ b/drivers/phy/Makefile
>>> @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
>>> obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
>>> obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
>>> obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
>>> +obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
>>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
>>> new file mode 100644
>>> index 0000000..d478c14
>>> --- /dev/null
>>> +++ b/drivers/phy/phy-miphy40lp.c
>>> @@ -0,0 +1,174 @@
>>> +/*
>>> + * ST MiPHY-40LP PHY driver
>>> + *
>>> + * Copyright (C) 2014 ST Microelectronics
>>> + * Pratyush Anand <[email protected]>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + */
>>> +
>>> +#include <linux/delay.h>
>>> +#include <linux/dma-mapping.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/mfd/syscon.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/phy/phy.h>
>>> +#include <linux/regmap.h>
>>> +
>>> +enum phy_mode {
>>> + SATA,
>>> + PCIE,
>>> + SS_USB,
>>> +};
>>> +
>>> +struct st_miphy40lp_priv {
>>> + /* regmap for any soc specific misc registers */
>>> + struct regmap *misc;
>>> + /* phy struct pointer */
>>> + struct phy *phy;
>>> + /* device node pointer */
>>> + struct device_node *np;
>>> + /* phy mode: 0 for SATA 1 for PCIe and 2 for SS-USB */
>>> + enum phy_mode mode;
>>> + /* instance id of this phy */
>>> + u32 id;
>>> +};
>>> +
>>> +static int miphy40lp_init(struct phy *phy)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_exit(struct phy *phy)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_power_off(struct phy *phy)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_power_on(struct phy *phy)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static const struct of_device_id st_miphy40lp_of_match[] = {
>>> + { .compatible = "st,miphy40lp-phy" },
>>> + { },
>>> +};
>>> +MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
>>> +
>>> +static struct phy_ops st_miphy40lp_ops = {
>>> + .init = miphy40lp_init,
>>> + .exit = miphy40lp_exit,
>>> + .power_off = miphy40lp_power_off,
>>> + .power_on = miphy40lp_power_on,
>>> + .owner = THIS_MODULE,
>>
>> Would prefer to either align all the fields or align none. Here only owner is
>> aligned.
>
> ok.
>
>>> +};
>>> +
>>> +#ifdef CONFIG_PM_SLEEP
>>> +static int miphy40lp_suspend(struct device *dev)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +
>>> +static int miphy40lp_resume(struct device *dev)
>>> +{
>>> + return -EINVAL;
>>> +}
>>> +#endif
>>> +
>>> +static SIMPLE_DEV_PM_OPS(miphy40lp_pm_ops, miphy40lp_suspend,
>>> + miphy40lp_resume);
>>> +
>>> +static struct phy *st_miphy40lp_xlate(struct device *dev,
>>> + struct of_phandle_args *args)
>>> +{
>>> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
>>> +
>>> + if (args->args_count < 1) {
>>> + dev_err(dev, "DT did not pass correct no of args\n");
>>> + return NULL;
>>> + }
>>> +
>>> + phypriv->mode = args->args[0];
>>> +
>>> + return phypriv->phy;
>>> +}
>>> +
>>> +static int __init st_miphy40lp_probe(struct platform_device *pdev)
>>> +{
>>> + struct device *dev = &pdev->dev;
>>> + struct st_miphy40lp_priv *phypriv;
>>> + struct phy_provider *phy_provider;
>>> +
>>> + phypriv = devm_kzalloc(dev, sizeof(*phypriv), GFP_KERNEL);
>>> + if (!phypriv) {
>>> + dev_err(dev, "can't alloc miphy40lp private date memory\n");
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + phypriv->np = dev->of_node;
>>> +
>>> + phypriv->misc =
>>> + syscon_regmap_lookup_by_phandle(dev->of_node, "misc");
>>> + if (IS_ERR(phypriv->misc)) {
>>> + dev_err(dev, "failed to find misc regmap\n");
>>> + return PTR_ERR(phypriv->misc);
>>> + }
>>> +
>>> + if (of_property_read_u32(dev->of_node, "phy-id", &phypriv->id)) {
>>> + dev_err(dev, "failed to find phy id\n");
>>> + return -EINVAL;
>>> + }
>> Do we really need this phy id? How is it being used?
>
> Yes , it is being used by patch 6/8.
Alright.
>
>>
>>> +
>>> + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
>>> + if (IS_ERR(phy_provider)) {
>>> + dev_err(dev, "failed to register phy provider\n");
>>> + return PTR_ERR(phy_provider);
>>> + }
>>
>> phy_provider_register should be the last step in registering the PHY. Or your
>> PHY call backs can be called before you create the PHY. Btw in your case you
>
> But every one else like phy-exynos-mipi-video or phy-omap-usb2 or any
> other did it same way. First phy_provider_register and then
> phy_create.
That's a bug which we figured out very late. Will get it fixed in this -rc cycle.
Thanks
Kishon
Hi,
On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> ahci driver needs some platform specific functions which are called at
> init, exit, suspend and resume conditions. Till now these functions were
> present in a platform driver with a fixme notes.
>
> Similar functions modifying same set of registers will also be needed in
> case of PCIe phy init/exit.
>
> So move all these SATA platform code to phy-miphy40lp driver.
>
> Signed-off-by: Pratyush Anand <[email protected]>
> Tested-by: Mohit Kumar <[email protected]>
> Cc: Viresh Kumar <[email protected]>
> Cc: Tejun Heo <[email protected]>
> Cc: Arnd Bergmann <[email protected]>
> Cc: Kishon Vijay Abraham I <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> .../devicetree/bindings/arm/spear-misc.txt | 4 +
> arch/arm/boot/dts/spear1310-evb.dts | 4 +
> arch/arm/boot/dts/spear1310.dtsi | 39 +++-
> arch/arm/boot/dts/spear1340-evb.dts | 4 +
> arch/arm/boot/dts/spear1340.dtsi | 13 +-
> arch/arm/boot/dts/spear13xx.dtsi | 5 +
> arch/arm/mach-spear/Kconfig | 2 +
> arch/arm/mach-spear/spear1340.c | 127 +------------
> drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
It would be better if you can split this patch. Keep arch/ in separate patch
and drivers/ in separate patch.
> 9 files changed, 266 insertions(+), 136 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>
.
.
<snip>
.
.
> static const char * const spear1340_dt_board_compat[] = {
> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> index d478c14..cc7f45d 100644
> --- a/drivers/phy/phy-miphy40lp.c
> +++ b/drivers/phy/phy-miphy40lp.c
> @@ -8,6 +8,7 @@
> * it under the terms of the GNU General Public License version 2 as
> * published by the Free Software Foundation.
> *
> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> */
>
> #include <linux/delay.h>
> @@ -19,6 +20,60 @@
> #include <linux/phy/phy.h>
> #include <linux/regmap.h>
>
> +/* SPEAr1340 Registers */
> +/* Power Management Registers */
> +#define SPEAR1340_PCM_CFG 0x100
> + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
> +#define SPEAR1340_PCM_WKUP_CFG 0x104
> +#define SPEAR1340_SWITCH_CTR 0x108
> +
> +#define SPEAR1340_PERIP1_SW_RST 0x318
> + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
> +#define SPEAR1340_PERIP2_SW_RST 0x31C
> +#define SPEAR1340_PERIP3_SW_RST 0x320
> +
> +/* PCIE - SATA configuration registers */
> +#define SPEAR1340_PCIE_SATA_CFG 0x424
> + /* PCIE CFG MASks */
> + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
use BIT() wherever possible.
> + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
> + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
> + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
> + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
> + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
> + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
> + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
> + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
> + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
> + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
> + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
> + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
> + SPEAR1340_SATA_CFG_PM_CLK_EN | \
> + SPEAR1340_SATA_CFG_POWERUP_RESET | \
> + SPEAR1340_SATA_CFG_RX_CLK_EN | \
> + SPEAR1340_SATA_CFG_TX_CLK_EN)
> +
> +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
> + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
> + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
> + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
> + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> +
> enum phy_mode {
> SATA,
> PCIE,
> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> u32 id;
> };
>
> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
The function name format here differs from what you have already added. It will
be good to have consistent name in the file.
> +{
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> + /* Switch on sata power domain */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> + msleep(20);
> + /* Disable PCIE SATA Controller reset */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RST_SATA, 0);
> + msleep(20);
> +
> + return 0;
> +}
> +
> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> +
> + /* Enable PCIE SATA Controller reset */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> + SPEAR1340_PERIP1_SW_RST_SATA,
> + SPEAR1340_PERIP1_SW_RST_SATA);
> + msleep(20);
> + /* Switch off sata power domain */
> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> + SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> + msleep(20);
> +
> + return 0;
> +}
> +
> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
This compatible value is a bit confusing since it doesn't have 'sata' in it.
spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
> + return spear1340_sata_miphy_init(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_sata_miphy_exit(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return 0;
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return 0;
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_sata_miphy_exit(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_sata_miphy_init(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> static int miphy40lp_init(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_init(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_exit(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_exit(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_power_off(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_power_off(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_power_on(struct phy *phy)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_power_on(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static const struct of_device_id st_miphy40lp_of_match[] = {
> { .compatible = "st,miphy40lp-phy" },
> + { .compatible = "st,spear1340-miphy" },
> { },
> };
> MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
> #ifdef CONFIG_PM_SLEEP
> static int miphy40lp_suspend(struct device *dev)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> + if (dev->power.power_state.event == PM_EVENT_FREEZE)
> + return 0;
I'm not sure if you should be accessing it from the drivers. Will be good to
check with PM guys.
> +
> + switch (phypriv->mode) {
> + case SATA:
> + return sata_miphy_suspend(phypriv);
> + default:
> + return -EINVAL;
> + }
> }
>
> static int miphy40lp_resume(struct device *dev)
> {
> - return -EINVAL;
> + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> +
> + if (dev->power.power_state.event == PM_EVENT_THAW)
> + return 0;
Same here.
Thanks
Kishon
On Thu, Feb 06, 2014 at 02:23:20PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 11:44 AM, Pratyush Anand wrote:
> > Hi Kishon,
> >
> > On Thu, Feb 06, 2014 at 02:01:45PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds
[...]
> >>> +
> >>> + phy_provider = devm_of_phy_provider_register(dev, st_miphy40lp_xlate);
> >>> + if (IS_ERR(phy_provider)) {
> >>> + dev_err(dev, "failed to register phy provider\n");
> >>> + return PTR_ERR(phy_provider);
> >>> + }
> >>
> >> phy_provider_register should be the last step in registering the PHY. Or your
> >> PHY call backs can be called before you create the PHY. Btw in your case you
> >
> > But every one else like phy-exynos-mipi-video or phy-omap-usb2 or any
> > other did it same way. First phy_provider_register and then
> > phy_create.
>
> That's a bug which we figured out very late. Will get it fixed in this -rc cycle.
Ok..I ll correct in mine too. :)
Rgds
Pratyush
>
> Thanks
> Kishon
On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> > ahci driver needs some platform specific functions which are called at
> > init, exit, suspend and resume conditions. Till now these functions were
> > present in a platform driver with a fixme notes.
> >
> > Similar functions modifying same set of registers will also be needed in
> > case of PCIe phy init/exit.
> >
> > So move all these SATA platform code to phy-miphy40lp driver.
> >
> > Signed-off-by: Pratyush Anand <[email protected]>
> > Tested-by: Mohit Kumar <[email protected]>
> > Cc: Viresh Kumar <[email protected]>
> > Cc: Tejun Heo <[email protected]>
> > Cc: Arnd Bergmann <[email protected]>
> > Cc: Kishon Vijay Abraham I <[email protected]>
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > Cc: [email protected]
> > ---
> > .../devicetree/bindings/arm/spear-misc.txt | 4 +
> > arch/arm/boot/dts/spear1310-evb.dts | 4 +
> > arch/arm/boot/dts/spear1310.dtsi | 39 +++-
> > arch/arm/boot/dts/spear1340-evb.dts | 4 +
> > arch/arm/boot/dts/spear1340.dtsi | 13 +-
> > arch/arm/boot/dts/spear13xx.dtsi | 5 +
> > arch/arm/mach-spear/Kconfig | 2 +
> > arch/arm/mach-spear/spear1340.c | 127 +------------
> > drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
>
> It would be better if you can split this patch. Keep arch/ in separate patch
> and drivers/ in separate patch.
Code is actually moving from arch to driver. Therefore I kept it in
same patch.
> > 9 files changed, 266 insertions(+), 136 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> >
> .
> .
> <snip>
> .
> .
> > static const char * const spear1340_dt_board_compat[] = {
> > diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> > index d478c14..cc7f45d 100644
> > --- a/drivers/phy/phy-miphy40lp.c
> > +++ b/drivers/phy/phy-miphy40lp.c
> > @@ -8,6 +8,7 @@
> > * it under the terms of the GNU General Public License version 2 as
> > * published by the Free Software Foundation.
> > *
> > + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> > */
> >
> > #include <linux/delay.h>
> > @@ -19,6 +20,60 @@
> > #include <linux/phy/phy.h>
> > #include <linux/regmap.h>
> >
> > +/* SPEAr1340 Registers */
> > +/* Power Management Registers */
> > +#define SPEAR1340_PCM_CFG 0x100
> > + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
> > +#define SPEAR1340_PCM_WKUP_CFG 0x104
> > +#define SPEAR1340_SWITCH_CTR 0x108
> > +
> > +#define SPEAR1340_PERIP1_SW_RST 0x318
> > + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
> > +#define SPEAR1340_PERIP2_SW_RST 0x31C
> > +#define SPEAR1340_PERIP3_SW_RST 0x320
> > +
> > +/* PCIE - SATA configuration registers */
> > +#define SPEAR1340_PCIE_SATA_CFG 0x424
> > + /* PCIE CFG MASks */
> > + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
>
> use BIT() wherever possible.
OK.
> > + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
> > + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
> > + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
> > + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
> > + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
> > + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
> > + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
> > + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
> > + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
> > + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
> > + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
> > + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> > + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> > + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> > + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> > + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
> > + SPEAR1340_SATA_CFG_PM_CLK_EN | \
> > + SPEAR1340_SATA_CFG_POWERUP_RESET | \
> > + SPEAR1340_SATA_CFG_RX_CLK_EN | \
> > + SPEAR1340_SATA_CFG_TX_CLK_EN)
> > +
> > +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
> > + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
> > + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
> > + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
> > + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
> > + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
> > + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
> > + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> > + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> > + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> > + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> > + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> > + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> > + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> > + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> > +
> > enum phy_mode {
> > SATA,
> > PCIE,
> > @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> > u32 id;
> > };
> >
> > +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>
> The function name format here differs from what you have already added. It will
> be good to have consistent name in the file.
You mean to pass "struct phy *phy" in all the internal functions too?
> > +{
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > + SPEAR1340_PCIE_MIPHY_CFG_MASK,
> > + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
> > + /* Switch on sata power domain */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN);
> > + msleep(20);
> > + /* Disable PCIE SATA Controller reset */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > + SPEAR1340_PERIP1_SW_RST_SATA, 0);
> > + msleep(20);
> > +
> > + return 0;
> > +}
> > +
> > +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
> > + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
> > + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
> > +
> > + /* Enable PCIE SATA Controller reset */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
> > + SPEAR1340_PERIP1_SW_RST_SATA,
> > + SPEAR1340_PERIP1_SW_RST_SATA);
> > + msleep(20);
> > + /* Switch off sata power domain */
> > + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
> > + SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
> > + msleep(20);
> > +
> > + return 0;
> > +}
> > +
> > +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
>
> This compatible value is a bit confusing since it doesn't have 'sata' in it.
> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
same spear1340 miphy is used for sata as well as for pcie. sata or
pcie mode is selected using mode args passed in phys.
> > + return spear1340_sata_miphy_init(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_sata_miphy_exit(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_off(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return 0;
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_power_on(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return 0;
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_suspend(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_sata_miphy_exit(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int sata_miphy_resume(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_sata_miphy_init(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > static int miphy40lp_init(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_init(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_exit(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_exit(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_power_off(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_power_off(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_power_on(struct phy *phy)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = phy_get_drvdata(phy);
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_power_on(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static const struct of_device_id st_miphy40lp_of_match[] = {
> > { .compatible = "st,miphy40lp-phy" },
> > + { .compatible = "st,spear1340-miphy" },
> > { },
> > };
> > MODULE_DEVICE_TABLE(of, st_miphy40lp_of_match);
> > @@ -75,12 +247,32 @@ static struct phy_ops st_miphy40lp_ops = {
> > #ifdef CONFIG_PM_SLEEP
> > static int miphy40lp_suspend(struct device *dev)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > + if (dev->power.power_state.event == PM_EVENT_FREEZE)
> > + return 0;
>
> I'm not sure if you should be accessing it from the drivers. Will be good to
> check with PM guys.
+ linux-pm mailing list.
Rgds
Pratyush
> > +
> > + switch (phypriv->mode) {
> > + case SATA:
> > + return sata_miphy_suspend(phypriv);
> > + default:
> > + return -EINVAL;
> > + }
> > }
> >
> > static int miphy40lp_resume(struct device *dev)
> > {
> > - return -EINVAL;
> > + struct st_miphy40lp_priv *phypriv = dev_get_drvdata(dev);
> > +
> > + if (dev->power.power_state.event == PM_EVENT_THAW)
> > + return 0;
>
> Same here.
>
> Thanks
> Kishon
Hi,
On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
>>> ahci driver needs some platform specific functions which are called at
>>> init, exit, suspend and resume conditions. Till now these functions were
>>> present in a platform driver with a fixme notes.
>>>
>>> Similar functions modifying same set of registers will also be needed in
>>> case of PCIe phy init/exit.
>>>
>>> So move all these SATA platform code to phy-miphy40lp driver.
>>>
>>> Signed-off-by: Pratyush Anand <[email protected]>
>>> Tested-by: Mohit Kumar <[email protected]>
>>> Cc: Viresh Kumar <[email protected]>
>>> Cc: Tejun Heo <[email protected]>
>>> Cc: Arnd Bergmann <[email protected]>
>>> Cc: Kishon Vijay Abraham I <[email protected]>
>>> Cc: [email protected]
>>> Cc: [email protected]
>>> Cc: [email protected]
>>> Cc: [email protected]
>>> Cc: [email protected]
>>> ---
>>> .../devicetree/bindings/arm/spear-misc.txt | 4 +
>>> arch/arm/boot/dts/spear1310-evb.dts | 4 +
>>> arch/arm/boot/dts/spear1310.dtsi | 39 +++-
>>> arch/arm/boot/dts/spear1340-evb.dts | 4 +
>>> arch/arm/boot/dts/spear1340.dtsi | 13 +-
>>> arch/arm/boot/dts/spear13xx.dtsi | 5 +
>>> arch/arm/mach-spear/Kconfig | 2 +
>>> arch/arm/mach-spear/spear1340.c | 127 +------------
>>> drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
>>
>> It would be better if you can split this patch. Keep arch/ in separate patch
>> and drivers/ in separate patch.
>
> Code is actually moving from arch to driver. Therefore I kept it in
> same patch.
>
>>> 9 files changed, 266 insertions(+), 136 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
>>>
>> .
>> .
>> <snip>
>> .
>> .
>>> static const char * const spear1340_dt_board_compat[] = {
>>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
>>> index d478c14..cc7f45d 100644
>>> --- a/drivers/phy/phy-miphy40lp.c
>>> +++ b/drivers/phy/phy-miphy40lp.c
>>> @@ -8,6 +8,7 @@
>>> * it under the terms of the GNU General Public License version 2 as
>>> * published by the Free Software Foundation.
>>> *
>>> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
>>> */
>>>
>>> #include <linux/delay.h>
>>> @@ -19,6 +20,60 @@
>>> #include <linux/phy/phy.h>
>>> #include <linux/regmap.h>
>>>
>>> +/* SPEAr1340 Registers */
>>> +/* Power Management Registers */
>>> +#define SPEAR1340_PCM_CFG 0x100
>>> + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
>>> +#define SPEAR1340_PCM_WKUP_CFG 0x104
>>> +#define SPEAR1340_SWITCH_CTR 0x108
>>> +
>>> +#define SPEAR1340_PERIP1_SW_RST 0x318
>>> + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
>>> +#define SPEAR1340_PERIP2_SW_RST 0x31C
>>> +#define SPEAR1340_PERIP3_SW_RST 0x320
>>> +
>>> +/* PCIE - SATA configuration registers */
>>> +#define SPEAR1340_PCIE_SATA_CFG 0x424
>>> + /* PCIE CFG MASks */
>>> + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
>>
>> use BIT() wherever possible.
>
> OK.
>
>>> + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
>>> + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
>>> + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
>>> + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
>>> + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
>>> + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
>>> + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
>>> + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
>>> + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
>>> + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
>>> + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
>>> + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
>>> + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
>>> + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
>>> + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
>>> + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
>>> + SPEAR1340_SATA_CFG_PM_CLK_EN | \
>>> + SPEAR1340_SATA_CFG_POWERUP_RESET | \
>>> + SPEAR1340_SATA_CFG_RX_CLK_EN | \
>>> + SPEAR1340_SATA_CFG_TX_CLK_EN)
>>> +
>>> +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
>>> + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
>>> + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
>>> + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
>>> + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
>>> + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
>>> + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
>>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
>>> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>>> + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
>>> + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
>>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
>>> + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
>>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
>>> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>>> + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
>>> +
>>> enum phy_mode {
>>> SATA,
>>> PCIE,
>>> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
>>> u32 id;
>>> };
>>>
>>> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>>
>> The function name format here differs from what you have already added. It will
>> be good to have consistent name in the file.
>
> You mean to pass "struct phy *phy" in all the internal functions too?
No. I meant let all the function names begin with miphy40lp_.
>
>>> +{
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> + SPEAR1340_PCIE_SATA_CFG_MASK, SPEAR1340_SATA_CFG_VAL);
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> + SPEAR1340_PCIE_MIPHY_CFG_MASK,
>>> + SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
>>> + /* Switch on sata power domain */
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
>>> + SPEAR1340_PCM_CFG_SATA_POWER_EN,
>>> + SPEAR1340_PCM_CFG_SATA_POWER_EN);
>>> + msleep(20);
>>> + /* Disable PCIE SATA Controller reset */
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
>>> + SPEAR1340_PERIP1_SW_RST_SATA, 0);
>>> + msleep(20);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int spear1340_sata_miphy_exit(struct st_miphy40lp_priv *phypriv)
>>> +{
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_SATA_CFG,
>>> + SPEAR1340_PCIE_SATA_CFG_MASK, 0);
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCIE_MIPHY_CFG,
>>> + SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
>>> +
>>> + /* Enable PCIE SATA Controller reset */
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PERIP1_SW_RST,
>>> + SPEAR1340_PERIP1_SW_RST_SATA,
>>> + SPEAR1340_PERIP1_SW_RST_SATA);
>>> + msleep(20);
>>> + /* Switch off sata power domain */
>>> + regmap_update_bits(phypriv->misc, SPEAR1340_PCM_CFG,
>>> + SPEAR1340_PCM_CFG_SATA_POWER_EN, 0);
>>> + msleep(20);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int sata_miphy_init(struct st_miphy40lp_priv *phypriv)
>>> +{
>>> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
>>
>> This compatible value is a bit confusing since it doesn't have 'sata' in it.
>> spear1340 can have usb phy or pcie phy too no? How do we differentiate it then?
>
> same spear1340 miphy is used for sata as well as for pcie. sata or
> pcie mode is selected using mode args passed in phys.
Alright. Got it while reading the next patch ;-)
Thanks
Kishon
On Thu, Feb 06, 2014 at 04:01:25PM +0800, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Thursday 06 February 2014 12:30 PM, Pratyush Anand wrote:
> > On Thu, Feb 06, 2014 at 02:32:42PM +0800, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Thursday 06 February 2014 10:14 AM, Pratyush Anand wrote:
> >>> ahci driver needs some platform specific functions which are called at
> >>> init, exit, suspend and resume conditions. Till now these functions were
> >>> present in a platform driver with a fixme notes.
> >>>
> >>> Similar functions modifying same set of registers will also be needed in
> >>> case of PCIe phy init/exit.
> >>>
> >>> So move all these SATA platform code to phy-miphy40lp driver.
> >>>
> >>> Signed-off-by: Pratyush Anand <[email protected]>
> >>> Tested-by: Mohit Kumar <[email protected]>
> >>> Cc: Viresh Kumar <[email protected]>
> >>> Cc: Tejun Heo <[email protected]>
> >>> Cc: Arnd Bergmann <[email protected]>
> >>> Cc: Kishon Vijay Abraham I <[email protected]>
> >>> Cc: [email protected]
> >>> Cc: [email protected]
> >>> Cc: [email protected]
> >>> Cc: [email protected]
> >>> Cc: [email protected]
> >>> ---
> >>> .../devicetree/bindings/arm/spear-misc.txt | 4 +
> >>> arch/arm/boot/dts/spear1310-evb.dts | 4 +
> >>> arch/arm/boot/dts/spear1310.dtsi | 39 +++-
> >>> arch/arm/boot/dts/spear1340-evb.dts | 4 +
> >>> arch/arm/boot/dts/spear1340.dtsi | 13 +-
> >>> arch/arm/boot/dts/spear13xx.dtsi | 5 +
> >>> arch/arm/mach-spear/Kconfig | 2 +
> >>> arch/arm/mach-spear/spear1340.c | 127 +------------
> >>> drivers/phy/phy-miphy40lp.c | 204 ++++++++++++++++++++-
> >>
> >> It would be better if you can split this patch. Keep arch/ in separate patch
> >> and drivers/ in separate patch.
> >
> > Code is actually moving from arch to driver. Therefore I kept it in
> > same patch.
> >
> >>> 9 files changed, 266 insertions(+), 136 deletions(-)
> >>> create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> >>>
> >> .
> >> .
> >> <snip>
> >> .
> >> .
> >>> static const char * const spear1340_dt_board_compat[] = {
> >>> diff --git a/drivers/phy/phy-miphy40lp.c b/drivers/phy/phy-miphy40lp.c
> >>> index d478c14..cc7f45d 100644
> >>> --- a/drivers/phy/phy-miphy40lp.c
> >>> +++ b/drivers/phy/phy-miphy40lp.c
> >>> @@ -8,6 +8,7 @@
> >>> * it under the terms of the GNU General Public License version 2 as
> >>> * published by the Free Software Foundation.
> >>> *
> >>> + * 04/02/2014: Adding support of SATA mode for SPEAr1340.
> >>> */
> >>>
> >>> #include <linux/delay.h>
> >>> @@ -19,6 +20,60 @@
> >>> #include <linux/phy/phy.h>
> >>> #include <linux/regmap.h>
> >>>
> >>> +/* SPEAr1340 Registers */
> >>> +/* Power Management Registers */
> >>> +#define SPEAR1340_PCM_CFG 0x100
> >>> + #define SPEAR1340_PCM_CFG_SATA_POWER_EN 0x800
> >>> +#define SPEAR1340_PCM_WKUP_CFG 0x104
> >>> +#define SPEAR1340_SWITCH_CTR 0x108
> >>> +
> >>> +#define SPEAR1340_PERIP1_SW_RST 0x318
> >>> + #define SPEAR1340_PERIP1_SW_RST_SATA 0x1000
> >>> +#define SPEAR1340_PERIP2_SW_RST 0x31C
> >>> +#define SPEAR1340_PERIP3_SW_RST 0x320
> >>> +
> >>> +/* PCIE - SATA configuration registers */
> >>> +#define SPEAR1340_PCIE_SATA_CFG 0x424
> >>> + /* PCIE CFG MASks */
> >>> + #define SPEAR1340_PCIE_CFG_DEVICE_PRESENT (1 << 11)
> >>
> >> use BIT() wherever possible.
> >
> > OK.
> >
> >>> + #define SPEAR1340_PCIE_CFG_POWERUP_RESET (1 << 10)
> >>> + #define SPEAR1340_PCIE_CFG_CORE_CLK_EN (1 << 9)
> >>> + #define SPEAR1340_PCIE_CFG_AUX_CLK_EN (1 << 8)
> >>> + #define SPEAR1340_SATA_CFG_TX_CLK_EN (1 << 4)
> >>> + #define SPEAR1340_SATA_CFG_RX_CLK_EN (1 << 3)
> >>> + #define SPEAR1340_SATA_CFG_POWERUP_RESET (1 << 2)
> >>> + #define SPEAR1340_SATA_CFG_PM_CLK_EN (1 << 1)
> >>> + #define SPEAR1340_PCIE_SATA_SEL_PCIE (0)
> >>> + #define SPEAR1340_PCIE_SATA_SEL_SATA (1)
> >>> + #define SPEAR1340_PCIE_SATA_CFG_MASK 0xF1F
> >>> + #define SPEAR1340_PCIE_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_PCIE | \
> >>> + SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
> >>> + SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
> >>> + SPEAR1340_PCIE_CFG_POWERUP_RESET | \
> >>> + SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
> >>> + #define SPEAR1340_SATA_CFG_VAL (SPEAR1340_PCIE_SATA_SEL_SATA | \
> >>> + SPEAR1340_SATA_CFG_PM_CLK_EN | \
> >>> + SPEAR1340_SATA_CFG_POWERUP_RESET | \
> >>> + SPEAR1340_SATA_CFG_RX_CLK_EN | \
> >>> + SPEAR1340_SATA_CFG_TX_CLK_EN)
> >>> +
> >>> +#define SPEAR1340_PCIE_MIPHY_CFG 0x428
> >>> + #define SPEAR1340_MIPHY_OSC_BYPASS_EXT (1 << 31)
> >>> + #define SPEAR1340_MIPHY_CLK_REF_DIV2 (1 << 27)
> >>> + #define SPEAR1340_MIPHY_CLK_REF_DIV4 (2 << 27)
> >>> + #define SPEAR1340_MIPHY_CLK_REF_DIV8 (3 << 27)
> >>> + #define SPEAR1340_MIPHY_PLL_RATIO_TOP(x) (x << 0)
> >>> + #define SPEAR1340_PCIE_MIPHY_CFG_MASK 0xF80000FF
> >>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
> >>> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> >>> + SPEAR1340_MIPHY_CLK_REF_DIV2 | \
> >>> + SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
> >>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
> >>> + (SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
> >>> + #define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
> >>> + (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
> >>> + SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
> >>> +
> >>> enum phy_mode {
> >>> SATA,
> >>> PCIE,
> >>> @@ -38,28 +93,145 @@ struct st_miphy40lp_priv {
> >>> u32 id;
> >>> };
> >>>
> >>> +static int spear1340_sata_miphy_init(struct st_miphy40lp_priv *phypriv)
> >>
> >> The function name format here differs from what you have already added. It will
> >> be good to have consistent name in the file.
> >
> > You mean to pass "struct phy *phy" in all the internal functions too?
>
> No. I meant let all the function names begin with miphy40lp_.
okkk.. miphy40lp_spear1340_sata_init looks better :)
Rgds
Pratyush
On Thursday 06 February 2014, Pratyush Anand wrote:
> +static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> + u32 mask;
> +
> + switch (phypriv->id) {
> + case 0:
> + mask = SPEAR1310_PCIE_CFG_MASK(0);
> + break;
> + case 1:
> + mask = SPEAR1310_PCIE_CFG_MASK(1);
> + break;
> + case 2:
> + mask = SPEAR1310_PCIE_CFG_MASK(2);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
> + SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
> +
> + regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
> +
> + return 0;
> +}
hmm, you set the mask based on the id, but then use the macro below
and ignore the mask?
> +
> +static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_pcie_miphy_init(phypriv);
> + else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> + return spear1310_pcie_miphy_init(phypriv);
> + else
> + return -EINVAL;
> +}
> +
> +static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> +{
> + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> + return spear1340_pcie_miphy_exit(phypriv);
> + else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> + return spear1310_pcie_miphy_exit(phypriv);
> + else
> + return -EINVAL;
> +}
I think it's better to make this code table-driven. Rather than checking
'of_device_is_compatible()', it's much easier to add a .data field to
the of_device_id array that describes the PHY. You can use .data to
point to a structure containing per-device function pointers or
(better) values and offsets to be used.
Arnd
Hi Arnd,
Do you see any more improvement in this series.
Else we will send V5 (probably the final one) with modifications for
Kishon's comment.
Regards
Pratyush
On Thu, Feb 6, 2014 at 10:14 AM, Pratyush Anand <[email protected]> wrote:
> First three patches are improvement and fixes for SPEAr13xx support.
> Patches 4-6 add miphy40lp skelten driver and support for spear1310/40 miphy
> wrapper. Patch 7 add support for SPEAr13xx PCIe.
>
> These pathes are tested with linux-3.14-rc1 with following patch on the top of
> it:
> Author: Balaji T K <[email protected]>
> Date: Mon Jan 20 16:41:27 2014 +0200
>
> ata: ahci_platform: Manage SATA PHY
>
> Tested with SPEAr1310 evaluation board:
> - INTEL PRO 100/100 EP card
> - USB xhci gen2 card
> - Above cards connected through LeCROY PTC switch
>
> Modifications for SATA are tested with SPEAr1340-evb board
>
> Changes since v3:
> - Phy driver renamed to phy-miphy40lp
> - ahci phy hook patch used as suggested by Arnd
> - Incorporated other minor comments from v3
>
> Changes since v2:
> - Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to
> the phy framework
> - Modify ahci driver to include phy hooks
> - phy-core driver modifications for subsys_initcall()
>
> Changes since v1:
> - Few patches of the series are already accepted and applied to mainline e.g.
> pcie designware driver improvements,fixes for IO translation bug, PCIe dw
> driver maintainer. So dropped these from v2.
> - Incorporated comment to move the common/reset PCIe code to the seperate driver
> - PCIe and SATA share common PHY configuration registers, so move SATA
> platform code to the system config driver
> Fourth patch is improves pcie designware driver and fixes the IO
> translation bug. IO translation bug fix leads to the working of PCIe EP devices
> connected to RC through switch.
>
> PCIe driver support for SPEAr1310/40 platform board is added.
>
> These patches are tested with SPEAr1310 evaluation board:
> - INTEL PRO 100/100 EP card
> - USB xhci gen2 card
> - Above cards connected through LeCROY PTC switch
>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
>
> Mohit Kumar (2):
> SPEAr13xx: defconfig: Update
> MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
>
> Pratyush Anand (6):
> clk: SPEAr13xx: Fix pcie clock name
> SPEAr13xx: Fix static mapping table
> phy: st-miphy-40lp: Add skeleton driver
> SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
> phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
> pcie: SPEAr13xx: Add designware pcie support
>
> .../devicetree/bindings/arm/spear-misc.txt | 4 +
> .../devicetree/bindings/pci/spear13xx-pcie.txt | 7 +
> .../devicetree/bindings/phy/st-miphy40lp.txt | 12 +
> MAINTAINERS | 6 +
> arch/arm/boot/dts/spear1310-evb.dts | 4 +
> arch/arm/boot/dts/spear1310.dtsi | 96 +++-
> arch/arm/boot/dts/spear1340-evb.dts | 4 +
> arch/arm/boot/dts/spear1340.dtsi | 32 +-
> arch/arm/boot/dts/spear13xx.dtsi | 10 +-
> arch/arm/configs/spear13xx_defconfig | 15 +
> arch/arm/mach-spear/Kconfig | 3 +
> arch/arm/mach-spear/include/mach/spear.h | 4 +-
> arch/arm/mach-spear/spear1340.c | 127 +----
> arch/arm/mach-spear/spear13xx.c | 2 +-
> drivers/clk/spear/spear1310_clock.c | 6 +-
> drivers/clk/spear/spear1340_clock.c | 2 +-
> drivers/pci/host/Kconfig | 5 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pcie-spear13xx.c | 414 ++++++++++++++++
> drivers/phy/Kconfig | 6 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-miphy40lp.c | 544 +++++++++++++++++++++
> 22 files changed, 1166 insertions(+), 139 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
> create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
> create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> create mode 100644 drivers/pci/host/pcie-spear13xx.c
> create mode 100644 drivers/phy/phy-miphy40lp.c
>
> --
> 1.8.1.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Arnd,
On Thu, Feb 06, 2014 at 11:37:05PM +0800, Arnd Bergmann wrote:
> On Thursday 06 February 2014, Pratyush Anand wrote:
> > +static int spear1310_pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > + u32 mask;
> > +
> > + switch (phypriv->id) {
> > + case 0:
> > + mask = SPEAR1310_PCIE_CFG_MASK(0);
> > + break;
> > + case 1:
> > + mask = SPEAR1310_PCIE_CFG_MASK(1);
> > + break;
> > + case 2:
> > + mask = SPEAR1310_PCIE_CFG_MASK(2);
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_SATA_CFG,
> > + SPEAR1310_PCIE_CFG_MASK(phypriv->id), 0);
> > +
> > + regmap_update_bits(phypriv->misc, SPEAR1310_PCIE_MIPHY_CFG_1,
> > + SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK, 0);
> > +
> > + return 0;
> > +}
>
> hmm, you set the mask based on the id, but then use the macro below
> and ignore the mask?
Blunder, no need of switch case here :(
Will correct.
>
> > +
> > +static int pcie_miphy_init(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_pcie_miphy_init(phypriv);
> > + else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> > + return spear1310_pcie_miphy_init(phypriv);
> > + else
> > + return -EINVAL;
> > +}
> > +
> > +static int pcie_miphy_exit(struct st_miphy40lp_priv *phypriv)
> > +{
> > + if (of_device_is_compatible(phypriv->np, "st,spear1340-miphy"))
> > + return spear1340_pcie_miphy_exit(phypriv);
> > + else if (of_device_is_compatible(phypriv->np, "st,spear1310-miphy"))
> > + return spear1310_pcie_miphy_exit(phypriv);
> > + else
> > + return -EINVAL;
> > +}
>
> I think it's better to make this code table-driven. Rather than checking
> 'of_device_is_compatible()', it's much easier to add a .data field to
> the of_device_id array that describes the PHY. You can use .data to
> point to a structure containing per-device function pointers or
> (better) values and offsets to be used.
Sounds a better idea. will reduce code size a lot. Thanks.
Regards
Pratyush
>
> Arnd
Hi Arnd,
On Fri, Feb 07, 2014 at 11:54:30AM +0800, Pratyush ANAND wrote:
> Hi Arnd,
>
> On Thu, Feb 06, 2014 at 11:37:05PM +0800, Arnd Bergmann wrote:
> > On Thursday 06 February 2014, Pratyush Anand wrote:
> >
[...]
> > I think it's better to make this code table-driven. Rather than checking
> > 'of_device_is_compatible()', it's much easier to add a .data field to
> > the of_device_id array that describes the PHY. You can use .data to
> > point to a structure containing per-device function pointers or
> > (better) values and offsets to be used.
values and offset would be good as long as we do not need to write on
conditional read status. In our case its OK, as we do not need to
write conditionally. But, would it be a good idea to go that way?
Regards
Pratyush
>
> Sounds a better idea. will reduce code size a lot. Thanks.
>
> Regards
> Pratyush
>
> >
> > Arnd