by Daniel Thompson

[permalink] [raw]

Subject: Re: [PATCH v8 0/4] arm: KGDB NMI/FIQ support

On 16/07/14 18:15, Harro Haan wrote:
>> Anyhow I've put together a new version of my earlier patch that I think
>> will retrigger all interrupts except SGIs (I'll look at SGIs and
>> compatibility with non-Freescale parts only if this improved approach
>> works).
>>
>> Reported-by: Harro Haan <[email protected]>
>> Signed-off-by: Daniel Thompson <[email protected]>
>> ---
>> drivers/irqchip/irq-gic.c | 31 ++++++++++++++++++++++++++++++-
>> 1 file changed, 30 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
>> index 73ae896..88f92e6 100644
>> --- a/drivers/irqchip/irq-gic.c
>> +++ b/drivers/irqchip/irq-gic.c
>> @@ -303,6 +303,33 @@ static int gic_set_wake(struct irq_data *d,
>> unsigned int on)
>> #define gic_set_wake NULL
>> #endif
>>
>> +/* This is a software emulation of the Aliased Interrupt Acknowledge
>> Register
>> + * (GIC_AIAR) found in GICv2+.
>> + */
>> +static u32 gic_handle_spurious_group_0(struct gic_chip_data *gic, u32
>> irqstat)
>> +{
>> + u32 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
>> + void __iomem *dist_base = gic_data_dist_base(gic);
>> + u32 offset, mask;
>> +
>> + if (!gic_data_fiq_enable(gic) || irqnr >= 1021)
>> + return irqnr;
>> +
>> + offset = irqnr / 32 * 4;
>> + mask = 1 << (irqnr % 32);
>> + if (readl_relaxed(dist_base + GIC_DIST_IGROUP + offset) & mask)
>> + return irqnr;
>> +
>> + /* this interrupt must be taken as a FIQ so put it back into the
>> + * pending state and end our own servicing of it.
>> + */
>> + writel_relaxed(mask, dist_base + GIC_DIST_PENDING_SET + offset);
>> + readl_relaxed(dist_base + GIC_DIST_PENDING_SET + offset);
>> + writel_relaxed(irqstat, gic_data_cpu_base(gic) + GIC_CPU_EOI);
>> +
>> + return 1023;
>> +}
>> +
>> static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
>> {
>> u32 irqstat, irqnr;
>> @@ -310,8 +337,10 @@ static void __exception_irq_entry
>> gic_handle_irq(struct pt_regs *regs)
>> void __iomem *cpu_base = gic_data_cpu_base(gic);
>>
>> do {
>> + local_fiq_disable();
>> irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
>> - irqnr = irqstat & GICC_IAR_INT_ID_MASK;
>> + irqnr = gic_handle_spurious_group_0(gic, irqstat);
>> + local_fiq_enable();
>>
>> if (likely(irqnr > 15 && irqnr < 1021)) {
>> irqnr = irq_find_mapping(gic->domain, irqnr);
>> --
>> 1.9.3
>>
>>
>>
>
> I just tested the above code. This approach also works as expected for
> edge sensitive interrupts.

Awesome [and also a personal relief to get it right this time around ;-) ].

So we have two completely different confirmed-as-working workarounds!

2014-07-17 09:20:47

by Daniel Thompson

[permalink] [raw]

Subject: Re: [PATCH v8 0/4] arm: KGDB NMI/FIQ support

On 16/07/14 18:21, Harro Haan wrote:
> On 16 July 2014 14:54, Daniel Thompson <[email protected]> wrote:
>> On 15/07/14 19:45, Marek Vasut wrote:
>>>>> I can reduce the number of occurrences (not prevent it) by adding the
>>>>> following hack to irq-gic.c
>>>>> @@ -297,10 +309,12 @@ static asmlinkage void __exception_irq_entry
>>>>> gic_handle_irq(struct pt_regs *regs
>>>>>
>>>>> u32 irqstat, irqnr;
>>>>> struct gic_chip_data *gic = &gic_data[0];
>>>>> void __iomem *cpu_base = gic_data_cpu_base(gic);
>>>>>
>>>>> do {
>>>>>
>>>>> + while(readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_PENDING_SET)
>>>>> & (1 << 30))
>>>>> + printk(KERN_ERR "TEMP: gic_handle_irq: wait for FIQ exception\n");
>>>>>
>>>>> irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
>>>>> irqnr = irqstat & ~0x1c00;
>>>>
>>>> I've made a more complete attempt to fix this. Could you test the
>>>> following? (and be prepared to fuzz the line numbers)
>>>
>>> There's also another workaround, look at [1], but it's really a perverse hack
>>> thus far (blush). What I did there is I got hinted that an L1 page table can
>>> have this NS bit set. If this bit is set for a mapping, all accesses to memory
>>> area via that mapping will be non-secure. And then, in turn, by doing a non-
>>> secure read of the INTACK register, it will not ever happen that the FIQ number
>>> will pop up in the INTACK. I only do a non-secure read of the INTACK register,
>>> all other registers of the GICv1 are read via regular secure-mode accesses.
>>
>> I'll be looking into this approach.
>>
>> It is technically a better approach than mine since it prevents the IRQ
>> handler from ever reading a group 0 interrupt from INTACK.
>
> Agree, preventing the problem is better than fixing it afterwards.
>
>>
>> Unfortunately the tentacles of this workaround reach pretty deep in the
>> memory management code (rather than being concentrated in the GIC
>> driver) but the improved runtime behaviour might be worth it.
>
> I did some worst case measurements on the SabreSD while running:
> $ while true; do hackbench 20; done &
>
> Use banked non-secure GIC_CPU_INTACK register for regular interrupts
> (patches by Marek):
> The FIQ handler reads the TWD_TIMER_COUNTER 2570 ticks (which is x
> 1000 / 498 = 5161 nsec) after FIQ interrupt ID30 is generated.
> The average is around 497 ticks.
> The minimum is around 34 ticks.
>
> Use re-trigger approach by putting it back to pending state (latest
> patch by Daniel):
> The FIQ handler reads the TWD_TIMER_COUNTER 2678 ticks (which is x
> 1000 / 498 = 5378 nsec) after FIQ interrupt ID30 is generated.
> The average is around 563 ticks (note: almost everything is normal path)
> The minimum is around 34 ticks (note: this is the normal path, not the
> re-trigger path)
>
> So the results are quite similar.

This is great work.

Be aware that I'd also expect the the performance of my workaround would
drop a little bit when when support for SGIs is added (mostly due to due
to increased code size).