This patch add 1GB large page support information on
x86_64 architecture in Documentation/vm/hugetlbpage.txt.
Signed-off-by: Masanari Iida <[email protected]>
---
Documentation/vm/hugetlbpage.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/vm/hugetlbpage.txt b/Documentation/vm/hugetlbpage.txt
index bdd4bb9..0a2bf4f 100644
--- a/Documentation/vm/hugetlbpage.txt
+++ b/Documentation/vm/hugetlbpage.txt
@@ -2,7 +2,8 @@
The intent of this file is to give a brief summary of hugetlbpage support in
the Linux kernel. This support is built on top of multiple page size support
that is provided by most modern architectures. For example, i386
-architecture supports 4K and 4M (2M in PAE mode) page sizes, ia64
+architecture supports 4K and 4M (2M in PAE mode) page sizes, x86_64
+architecture supports 4K, 2M and 1G (SandyBridge or later) page sizes. ia64
architecture supports multiple page sizes 4K, 8K, 64K, 256K, 1M, 4M, 16M,
256M and ppc64 supports 4K and 16M. A TLB is a cache of virtual-to-physical
translations. Typically this is a very scarce resource on processor.
--
2.1.2.555.gfbecd99
On Sat, 1 Nov 2014 01:01:57 +0900
Masanari Iida <[email protected]> wrote:
> This patch add 1GB large page support information on
> x86_64 architecture in Documentation/vm/hugetlbpage.txt.
>
> Signed-off-by: Masanari Iida <[email protected]>
> ---
> Documentation/vm/hugetlbpage.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/vm/hugetlbpage.txt b/Documentation/vm/hugetlbpage.txt
> index bdd4bb9..0a2bf4f 100644
> --- a/Documentation/vm/hugetlbpage.txt
> +++ b/Documentation/vm/hugetlbpage.txt
> @@ -2,7 +2,8 @@
> The intent of this file is to give a brief summary of hugetlbpage support in
> the Linux kernel. This support is built on top of multiple page size support
> that is provided by most modern architectures. For example, i386
> -architecture supports 4K and 4M (2M in PAE mode) page sizes, ia64
> +architecture supports 4K and 4M (2M in PAE mode) page sizes, x86_64
> +architecture supports 4K, 2M and 1G (SandyBridge or later) page sizes. ia64
Good catch, but does it make sense to mention SandyBridge? Doesn't it makes
it Intel specific? What about mentioning the pdpe1gb flag instead?
> architecture supports multiple page sizes 4K, 8K, 64K, 256K, 1M, 4M, 16M,
> 256M and ppc64 supports 4K and 16M. A TLB is a cache of virtual-to-physical
> translations. Typically this is a very scarce resource on processor.
On 10/31/2014 09:01 AM, Masanari Iida wrote:
> --- a/Documentation/vm/hugetlbpage.txt
> +++ b/Documentation/vm/hugetlbpage.txt
> @@ -2,7 +2,8 @@
> The intent of this file is to give a brief summary of hugetlbpage support in
> the Linux kernel. This support is built on top of multiple page size support
> that is provided by most modern architectures. For example, i386
> -architecture supports 4K and 4M (2M in PAE mode) page sizes, ia64
> +architecture supports 4K and 4M (2M in PAE mode) page sizes, x86_64
> +architecture supports 4K, 2M and 1G (SandyBridge or later) page sizes. ia64
> architecture supports multiple page sizes 4K, 8K, 64K, 256K, 1M, 4M, 16M,
> 256M and ppc64 supports 4K and 16M. A TLB is a cache of virtual-to-physical
> translations. Typically this is a very scarce resource on processor.
I wouldn't mention SandyBridge. Not all x86 CPUs are Intel. :)
Also, what of the Intel CPUs like the Xeon Phi or the Atom cores? I
have an IvyBridge (>= Sandybridge) mobile CPU in this laptop which does
not support 1G pages.
I would axe the i386-specific reference and just say something generic like:
For example, x86 CPUs normally support 4K and 2M (1G sometimes).
Luiz, Dave,
Thanks for comments.
I understand that there are some exception cases which doesn't support 1G
large pages on newer CPUs.
I like Dave's example, at the same time I would like to add "pdpe1gb flag" in
the document.
For example, x86 CPUs normally support 4K and 2M (1G if pdpe1gb flag exist).
Masanari
On Tue, Nov 4, 2014 at 3:18 AM, Dave Hansen <[email protected]> wrote:
> On 10/31/2014 09:01 AM, Masanari Iida wrote:
>> --- a/Documentation/vm/hugetlbpage.txt
>> +++ b/Documentation/vm/hugetlbpage.txt
>> @@ -2,7 +2,8 @@
>> The intent of this file is to give a brief summary of hugetlbpage support in
>> the Linux kernel. This support is built on top of multiple page size support
>> that is provided by most modern architectures. For example, i386
>> -architecture supports 4K and 4M (2M in PAE mode) page sizes, ia64
>> +architecture supports 4K and 4M (2M in PAE mode) page sizes, x86_64
>> +architecture supports 4K, 2M and 1G (SandyBridge or later) page sizes. ia64
>> architecture supports multiple page sizes 4K, 8K, 64K, 256K, 1M, 4M, 16M,
>> 256M and ppc64 supports 4K and 16M. A TLB is a cache of virtual-to-physical
>> translations. Typically this is a very scarce resource on processor.
>
> I wouldn't mention SandyBridge. Not all x86 CPUs are Intel. :)
>
> Also, what of the Intel CPUs like the Xeon Phi or the Atom cores? I
> have an IvyBridge (>= Sandybridge) mobile CPU in this laptop which does
> not support 1G pages.
>
> I would axe the i386-specific reference and just say something generic like:
>
> For example, x86 CPUs normally support 4K and 2M (1G sometimes).
>
>
On 11/05/2014 07:21 AM, Masanari Iida wrote:
> Luiz, Dave,
> Thanks for comments.
>
> I understand that there are some exception cases which doesn't support 1G
> large pages on newer CPUs.
> I like Dave's example, at the same time I would like to add "pdpe1gb flag" in
> the document.
>
> For example, x86 CPUs normally support 4K and 2M (1G if pdpe1gb flag exist).
Is 1G supported on CPUs that have pdpe1gb and are running a 32-bit kernel?
Dave Hansen <[email protected]> writes:
> On 11/05/2014 07:21 AM, Masanari Iida wrote:
>> Luiz, Dave,
>> Thanks for comments.
>>
>> I understand that there are some exception cases which doesn't support 1G
>> large pages on newer CPUs.
>> I like Dave's example, at the same time I would like to add "pdpe1gb flag" in
>> the document.
>>
>> For example, x86 CPUs normally support 4K and 2M (1G if pdpe1gb flag exist).
>
> Is 1G supported on CPUs that have pdpe1gb and are running a 32-bit kernel?
No, 1GB pages is a 64bit only feature.
-Andi
--
[email protected] -- Speaking for myself only
On 11/05/2014 02:58 PM, Andi Kleen wrote:
>>> >> I understand that there are some exception cases which doesn't support 1G
>>> >> large pages on newer CPUs.
>>> >> I like Dave's example, at the same time I would like to add "pdpe1gb flag" in
>>> >> the document.
>>> >>
>>> >> For example, x86 CPUs normally support 4K and 2M (1G if pdpe1gb flag exist).
>> >
>> > Is 1G supported on CPUs that have pdpe1gb and are running a 32-bit kernel?
> No, 1GB pages is a 64bit only feature.
This is one sentence in a document that nobody reads, so we're all
putting way more brainpower in to this than we should.
We can't universally say that "1G if pdpe1gb flag exist" since a 64-bit
CPU running a 32-bit kernel doesn't support 1G pages *despite* the
presence of pdpe1gb. I think that makes it a pretty crappy thing to put
in a document since it's just misleading. We can't spell out all the
pitfalls or all the possible combinations, and it's not the place of our
stupid documentation to repeat what's in the architecture manuals.
For example, x86 CPUs normally support 4K and 2M (1G if
architecturally supported).
This patch adds 1GB large page support information in
Documentation/vm/hugetlbpage.txt
Reference:
https://lkml.org/lkml/2014/10/31/366
Signed-off-by: Masanari Iida <[email protected]>
---
Documentation/vm/hugetlbpage.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/vm/hugetlbpage.txt b/Documentation/vm/hugetlbpage.txt
index b64e0af..f2d3a10 100644
--- a/Documentation/vm/hugetlbpage.txt
+++ b/Documentation/vm/hugetlbpage.txt
@@ -1,8 +1,8 @@
The intent of this file is to give a brief summary of hugetlbpage support in
the Linux kernel. This support is built on top of multiple page size support
-that is provided by most modern architectures. For example, i386
-architecture supports 4K and 4M (2M in PAE mode) page sizes, ia64
+that is provided by most modern architectures. For example, x86 CPUs normally
+support 4K and 2M (1G if architecturally supported) page sizes, ia64
architecture supports multiple page sizes 4K, 8K, 64K, 256K, 1M, 4M, 16M,
256M and ppc64 supports 4K and 16M. A TLB is a cache of virtual-to-physical
translations. Typically this is a very scarce resource on processor.
--
2.2.0.rc0.2.gf745acb
On Fri, 7 Nov 2014 00:31:15 +0900
Masanari Iida <[email protected]> wrote:
> This patch adds 1GB large page support information in
> Documentation/vm/hugetlbpage.txt
>
> Reference:
> https://lkml.org/lkml/2014/10/31/366
>
> Signed-off-by: Masanari Iida <[email protected]>
> ---
> Documentation/vm/hugetlbpage.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/vm/hugetlbpage.txt b/Documentation/vm/hugetlbpage.txt
> index b64e0af..f2d3a10 100644
> --- a/Documentation/vm/hugetlbpage.txt
> +++ b/Documentation/vm/hugetlbpage.txt
> @@ -1,8 +1,8 @@
>
> The intent of this file is to give a brief summary of hugetlbpage support in
> the Linux kernel. This support is built on top of multiple page size support
> -that is provided by most modern architectures. For example, i386
> -architecture supports 4K and 4M (2M in PAE mode) page sizes, ia64
> +that is provided by most modern architectures. For example, x86 CPUs normally
> +support 4K and 2M (1G if architecturally supported) page sizes, ia64
> architecture supports multiple page sizes 4K, 8K, 64K, 256K, 1M, 4M, 16M,
> 256M and ppc64 supports 4K and 16M. A TLB is a cache of virtual-to-physical
> translations. Typically this is a very scarce resource on processor.
Looks good to me:
Reviewed-by: Luiz Capitulino <[email protected]>
On Fri, 7 Nov 2014 00:31:15 +0900
Masanari Iida <[email protected]> wrote:
> This patch adds 1GB large page support information in
> Documentation/vm/hugetlbpage.txt
Applied, thanks.
jon