Hi Heikki,
On Fri, Jan 23, 2015 at 05:12:56PM +0200, Heikki Krogerus wrote:
> Registers DWC3's ULPI interface with the ULPI bus when it's
> available.
>
> Signed-off-by: Heikki Krogerus <[email protected]>
> ---
> drivers/usb/dwc3/Kconfig | 7 +++
> drivers/usb/dwc3/Makefile | 4 ++
> drivers/usb/dwc3/core.c | 6 +++
> drivers/usb/dwc3/core.h | 13 ++++++
> drivers/usb/dwc3/ulpi.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++
> 5 files changed, 142 insertions(+)
> create mode 100644 drivers/usb/dwc3/ulpi.c
>
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> index 58b5b2c..cda82ad 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -11,6 +11,13 @@ config USB_DWC3
>
> if USB_DWC3
>
> +config USB_DWC3_ULPI
> + bool "Register ULPI PHY Interface"
> + depends on USB_ULPI_BUS=y
> + help
> + Select this if you have ULPI type PHY attached to your DWC3
> + controller.
> +
> choice
> bool "DWC3 Mode Selection"
> default USB_DWC3_DUAL_ROLE if (USB && USB_GADGET)
> diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
> index bb34fbc..2fc44e0 100644
> --- a/drivers/usb/dwc3/Makefile
> +++ b/drivers/usb/dwc3/Makefile
> @@ -16,6 +16,10 @@ ifneq ($(filter y,$(CONFIG_USB_DWC3_GADGET) $(CONFIG_USB_DWC3_DUAL_ROLE)),)
> dwc3-y += gadget.o ep0.o
> endif
>
> +ifneq ($(CONFIG_USB_DWC3_ULPI),)
> + dwc3-y += ulpi.o
> +endif
> +
> ifneq ($(CONFIG_DEBUG_FS),)
> dwc3-y += debugfs.o
> endif
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index a8c9062..66cbf38 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -879,6 +879,10 @@ static int dwc3_probe(struct platform_device *pdev)
> platform_set_drvdata(pdev, dwc);
> dwc3_cache_hwparams(dwc);
>
> + ret = dwc3_ulpi_init(dwc);
If I understood correctly, this call will result in enumerating the phy
via ULPI bus, then registering the correct ULPI device.
Can you guarantee ULPI will be always accessible at this point if we
remove dwc3 module and load it again?
Br, David
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index a8c9062..66cbf38 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -879,6 +879,10 @@ static int dwc3_probe(struct platform_device *pdev)
> > platform_set_drvdata(pdev, dwc);
> > dwc3_cache_hwparams(dwc);
> >
> > + ret = dwc3_ulpi_init(dwc);
>
> If I understood correctly, this call will result in enumerating the phy
> via ULPI bus, then registering the correct ULPI device.
> Can you guarantee ULPI will be always accessible at this point if we
> remove dwc3 module and load it again?
OK, got it. So yes, I can guarantee that ULPI will be acessible at
this point. If we are in a state where we could soft reset dwc3, we
know we can access ULPI. The fact that dwc3 itself expects to be able
to write to the ULPI registers at that point guarantees it for us.
So in practice when ever dwc3 is powered we will be able to access
ULPI for as long as the USB2 PHY interface is not suspended separately
with GUSB2PHYCFG SusPHY bit. And even then we would only need to
resume it with the same bit and ULPI is accessible again.
Cheers,
--
heikki
On Thu, Feb 12, 2015 at 02:12:14PM +0200, Heikki Krogerus wrote:
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index a8c9062..66cbf38 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -879,6 +879,10 @@ static int dwc3_probe(struct platform_device *pdev)
> > > platform_set_drvdata(pdev, dwc);
> > > dwc3_cache_hwparams(dwc);
> > >
> > > + ret = dwc3_ulpi_init(dwc);
> >
> > If I understood correctly, this call will result in enumerating the phy
> > via ULPI bus, then registering the correct ULPI device.
> > Can you guarantee ULPI will be always accessible at this point if we
> > remove dwc3 module and load it again?
>
> OK, got it. So yes, I can guarantee that ULPI will be acessible at
> this point. If we are in a state where we could soft reset dwc3, we
> know we can access ULPI. The fact that dwc3 itself expects to be able
> to write to the ULPI registers at that point guarantees it for us.
I just double checked DWC3 TRM.
You are correct, by the time we're executing dwc3_core_soft_reset() ULPI
bus is already accessible. But the TRM also specifies an ULPI phy would
be reset by DCTL's core soft reset, which is executed by dwc3_core_init()
before calling dwc3_core_soft_reset(). It does mention DWC3 writes data
to an ULPI phy register during reset, but it also mentions the clock
sync happens during that time.
That makes no even OK, but more correct IMO to power on phy before
core's soft reset (i.e. by ACPI methods). But it lets us in a grey area
whether ULPI is reliably accessible before core's soft reset.
I believe if you move the dwc3_ulpi_init() to dwc3_core_init(), after
core's soft reset we've got no more grey area.
Br, David
>
> So in practice when ever dwc3 is powered we will be able to access
> ULPI for as long as the USB2 PHY interface is not suspended separately
> with GUSB2PHYCFG SusPHY bit. And even then we would only need to
> resume it with the same bit and ULPI is accessible again.
>
>
> Cheers,
>
> --
> heikki
On Thu, Feb 12, 2015 at 05:41:30PM -0800, David Cohen wrote:
> On Thu, Feb 12, 2015 at 02:12:14PM +0200, Heikki Krogerus wrote:
> > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > index a8c9062..66cbf38 100644
> > > > --- a/drivers/usb/dwc3/core.c
> > > > +++ b/drivers/usb/dwc3/core.c
> > > > @@ -879,6 +879,10 @@ static int dwc3_probe(struct platform_device *pdev)
> > > > platform_set_drvdata(pdev, dwc);
> > > > dwc3_cache_hwparams(dwc);
> > > >
> > > > + ret = dwc3_ulpi_init(dwc);
> > >
> > > If I understood correctly, this call will result in enumerating the phy
> > > via ULPI bus, then registering the correct ULPI device.
> > > Can you guarantee ULPI will be always accessible at this point if we
> > > remove dwc3 module and load it again?
> >
> > OK, got it. So yes, I can guarantee that ULPI will be acessible at
> > this point. If we are in a state where we could soft reset dwc3, we
> > know we can access ULPI. The fact that dwc3 itself expects to be able
> > to write to the ULPI registers at that point guarantees it for us.
>
> I just double checked DWC3 TRM.
> You are correct, by the time we're executing dwc3_core_soft_reset() ULPI
> bus is already accessible. But the TRM also specifies an ULPI phy would
> be reset by DCTL's core soft reset, which is executed by dwc3_core_init()
> before calling dwc3_core_soft_reset(). It does mention DWC3 writes data
> to an ULPI phy register during reset, but it also mentions the clock
> sync happens during that time.
>
> That makes no even OK, but more correct IMO to power on phy before
Sorry for the typo. I meant:
That makes not only OK, but more correct...
> core's soft reset (i.e. by ACPI methods). But it lets us in a grey area
> whether ULPI is reliably accessible before core's soft reset.
>
> I believe if you move the dwc3_ulpi_init() to dwc3_core_init(), after
> core's soft reset we've got no more grey area.
>
> Br, David
>
> >
> > So in practice when ever dwc3 is powered we will be able to access
> > ULPI for as long as the USB2 PHY interface is not suspended separately
> > with GUSB2PHYCFG SusPHY bit. And even then we would only need to
> > resume it with the same bit and ULPI is accessible again.
> >
> >
> > Cheers,
> >
> > --
> > heikki
On Thu, Feb 12, 2015 at 05:41:30PM -0800, David Cohen wrote:
> On Thu, Feb 12, 2015 at 02:12:14PM +0200, Heikki Krogerus wrote:
> > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > index a8c9062..66cbf38 100644
> > > > --- a/drivers/usb/dwc3/core.c
> > > > +++ b/drivers/usb/dwc3/core.c
> > > > @@ -879,6 +879,10 @@ static int dwc3_probe(struct platform_device *pdev)
> > > > platform_set_drvdata(pdev, dwc);
> > > > dwc3_cache_hwparams(dwc);
> > > >
> > > > + ret = dwc3_ulpi_init(dwc);
> > >
> > > If I understood correctly, this call will result in enumerating the phy
> > > via ULPI bus, then registering the correct ULPI device.
> > > Can you guarantee ULPI will be always accessible at this point if we
> > > remove dwc3 module and load it again?
> >
> > OK, got it. So yes, I can guarantee that ULPI will be acessible at
> > this point. If we are in a state where we could soft reset dwc3, we
> > know we can access ULPI. The fact that dwc3 itself expects to be able
> > to write to the ULPI registers at that point guarantees it for us.
>
> I just double checked DWC3 TRM.
> You are correct, by the time we're executing dwc3_core_soft_reset() ULPI
> bus is already accessible. But the TRM also specifies an ULPI phy would
> be reset by DCTL's core soft reset, which is executed by dwc3_core_init()
> before calling dwc3_core_soft_reset(). It does mention DWC3 writes data
> to an ULPI phy register during reset, but it also mentions the clock
> sync happens during that time.
>
> That makes no even OK, but more correct IMO to power on phy before
> core's soft reset (i.e. by ACPI methods). But it lets us in a grey area
> whether ULPI is reliably accessible before core's soft reset.
>
> I believe if you move the dwc3_ulpi_init() to dwc3_core_init(), after
> core's soft reset we've got no more grey area.
Well, we have already requested the phys in dwc3_probe before that so
some refactoring will be needed. It's probable no a problem.
Btw, I'm sorry about telling this so late, but I'm going to be on
vacation for the next two weeks.
Cheers,
--
heikki
Hi Heikki,
On Fri, Feb 13, 2015 at 03:16:40PM +0200, Heikki Krogerus wrote:
> On Thu, Feb 12, 2015 at 05:41:30PM -0800, David Cohen wrote:
> > On Thu, Feb 12, 2015 at 02:12:14PM +0200, Heikki Krogerus wrote:
> > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > index a8c9062..66cbf38 100644
> > > > > --- a/drivers/usb/dwc3/core.c
> > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > @@ -879,6 +879,10 @@ static int dwc3_probe(struct platform_device *pdev)
> > > > > platform_set_drvdata(pdev, dwc);
> > > > > dwc3_cache_hwparams(dwc);
> > > > >
> > > > > + ret = dwc3_ulpi_init(dwc);
> > > >
> > > > If I understood correctly, this call will result in enumerating the phy
> > > > via ULPI bus, then registering the correct ULPI device.
> > > > Can you guarantee ULPI will be always accessible at this point if we
> > > > remove dwc3 module and load it again?
> > >
> > > OK, got it. So yes, I can guarantee that ULPI will be acessible at
> > > this point. If we are in a state where we could soft reset dwc3, we
> > > know we can access ULPI. The fact that dwc3 itself expects to be able
> > > to write to the ULPI registers at that point guarantees it for us.
> >
> > I just double checked DWC3 TRM.
> > You are correct, by the time we're executing dwc3_core_soft_reset() ULPI
> > bus is already accessible. But the TRM also specifies an ULPI phy would
> > be reset by DCTL's core soft reset, which is executed by dwc3_core_init()
> > before calling dwc3_core_soft_reset(). It does mention DWC3 writes data
> > to an ULPI phy register during reset, but it also mentions the clock
> > sync happens during that time.
> >
> > That makes no even OK, but more correct IMO to power on phy before
> > core's soft reset (i.e. by ACPI methods). But it lets us in a grey area
> > whether ULPI is reliably accessible before core's soft reset.
> >
> > I believe if you move the dwc3_ulpi_init() to dwc3_core_init(), after
> > core's soft reset we've got no more grey area.
>
> Well, we have already requested the phys in dwc3_probe before that so
> some refactoring will be needed. It's probable no a problem.
Sounds good :)
>
> Btw, I'm sorry about telling this so late, but I'm going to be on
> vacation for the next two weeks.
Thanks for the notice.
Br, David
>
>
> Cheers,
>
> --
> heikki
On Fri, Feb 13, 2015 at 02:03:45PM -0800, David Cohen wrote:
> Hi Heikki,
>
> On Fri, Feb 13, 2015 at 03:16:40PM +0200, Heikki Krogerus wrote:
> > On Thu, Feb 12, 2015 at 05:41:30PM -0800, David Cohen wrote:
> > > On Thu, Feb 12, 2015 at 02:12:14PM +0200, Heikki Krogerus wrote:
> > > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > > index a8c9062..66cbf38 100644
> > > > > > --- a/drivers/usb/dwc3/core.c
> > > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > > @@ -879,6 +879,10 @@ static int dwc3_probe(struct platform_device *pdev)
> > > > > > platform_set_drvdata(pdev, dwc);
> > > > > > dwc3_cache_hwparams(dwc);
> > > > > >
> > > > > > + ret = dwc3_ulpi_init(dwc);
> > > > >
> > > > > If I understood correctly, this call will result in enumerating the phy
> > > > > via ULPI bus, then registering the correct ULPI device.
> > > > > Can you guarantee ULPI will be always accessible at this point if we
> > > > > remove dwc3 module and load it again?
> > > >
> > > > OK, got it. So yes, I can guarantee that ULPI will be acessible at
> > > > this point. If we are in a state where we could soft reset dwc3, we
> > > > know we can access ULPI. The fact that dwc3 itself expects to be able
> > > > to write to the ULPI registers at that point guarantees it for us.
> > >
> > > I just double checked DWC3 TRM.
> > > You are correct, by the time we're executing dwc3_core_soft_reset() ULPI
> > > bus is already accessible. But the TRM also specifies an ULPI phy would
> > > be reset by DCTL's core soft reset, which is executed by dwc3_core_init()
> > > before calling dwc3_core_soft_reset(). It does mention DWC3 writes data
> > > to an ULPI phy register during reset, but it also mentions the clock
> > > sync happens during that time.
> > >
> > > That makes no even OK, but more correct IMO to power on phy before
> > > core's soft reset (i.e. by ACPI methods). But it lets us in a grey area
> > > whether ULPI is reliably accessible before core's soft reset.
> > >
> > > I believe if you move the dwc3_ulpi_init() to dwc3_core_init(), after
> > > core's soft reset we've got no more grey area.
> >
> > Well, we have already requested the phys in dwc3_probe before that so
> > some refactoring will be needed. It's probable no a problem.
>
> Sounds good :)
>
> >
> > Btw, I'm sorry about telling this so late, but I'm going to be on
> > vacation for the next two weeks.
>
> Thanks for the notice.
you'll be back right around merge window closing time :-) Not to worry,
we'll have time to get this into the next merge window.
--
balbi