Hello, Robert.
Maybe qualifying the subject that it's only for single IRQ would be a
good idea?
> @@ -52,6 +53,7 @@
>
> enum {
> AHCI_PCI_BAR_STA2X11 = 0,
> + AHCI_PCI_BAR_CAVIUM = 0,
> AHCI_PCI_BAR_ENMOTUS = 2,
> AHCI_PCI_BAR_STANDARD = 5,
I thought I already asked but please separate out CAVIUM specific
changes from msix implementation and follow up with why cavium depends
on msix support.
> +static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports,
> + struct ahci_host_priv *hpriv)
> +{
Please add a comment describing that it's for single msix only and why
that'd be necessary for certain controllers.
...
> + /*
> + * Per-port msix interrupts are not supported. Assume single
> + * port interrupts for:
> + *
> + * n_ports == 1, or
> + * nvec < n_ports.
> + *
> + * We also need to check for n_ports != 0 which is implicitly
> + * covered here since nvec > 0.
> + */
> + if (n_ports != 1 && nvec >= n_ports) {
> + rc = -ENOSYS;
> + goto fail;
> + }
Didn't I ask this one too the last time? Can you explain why we can't
initialize single IRQ mode if nvec >= n_ports?
> @@ -1260,6 +1339,10 @@ static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
> if (nvec >= 0)
> return nvec;
>
> + nvec = ahci_init_msix(pdev, n_ports, hpriv);
> + if (nvec >= 0)
> + return nvec;
Please add a comment explaining why we're doing msix after msi.
Thanks.
--
tejun
Tejun,
thanks for applying first 2 patches of this series already.
I will address the comments you made on this patch in my next
submission. But see my question below.
On 03.06.15 14:44:22, Tejun Heo wrote:
> > + /*
> > + * Per-port msix interrupts are not supported. Assume single
> > + * port interrupts for:
> > + *
> > + * n_ports == 1, or
> > + * nvec < n_ports.
> > + *
> > + * We also need to check for n_ports != 0 which is implicitly
> > + * covered here since nvec > 0.
> > + */
> > + if (n_ports != 1 && nvec >= n_ports) {
> > + rc = -ENOSYS;
> > + goto fail;
> > + }
>
> Didn't I ask this one too the last time? Can you explain why we can't
> initialize single IRQ mode if nvec >= n_ports?
I was hoping the comment above the code explains it. Since the code is
generic I implemented it a bit conservative wrt enabling msix. So the
above does not enable msix for devices with more than one port if the
number of interrupts is greater than the number of ports. In this case
the device could be multiple IRQ capable.
Now, after reading the section in the ahci spec about multiple IRQs
more detailed, I tend to be less stricter here. Single IRQ mode is
default for each device and multi mode must be explicitly enabled.
Thus, we could just enable single msix support for all kind of
devices.
There are 2 options now. One is to keep the above which means we need
to enable multi IRQ capable devices later. The other would be to drop
the check above completly and enable single IRQ support for all msix
devices.
I can't estimate the impact to other devices of this change (option
2). If you think this will be ok I will remove the check. But we could
leave it in for the first time and remove it later once tested on such
a device. Please let me know your opinion on this.
Thanks,
-Robert
Hello, Robert.
On Thu, Jun 04, 2015 at 11:03:55AM +0200, Robert Richter wrote:
> I can't estimate the impact to other devices of this change (option
> 2). If you think this will be ok I will remove the check. But we could
> leave it in for the first time and remove it later once tested on such
> a device. Please let me know your opinion on this.
Yeah, let's just enable msix if supported. If some devices are
broken, they need to be blacklisted anyway.
Thanks.
--
tejun