This first patch-set contains various clock fixes for ST SoC.
Gabriel Fernandez (7):
drivers: clk: st: Incorrect clocks status
drivers: clk: st: Incorrect register offset used for lock_status
drivers: clk: st: Remove unused code
drivers: clk: st: Fix FSYN channel values
drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks
drivers: clk: st: Rename st_pll3200c32_407_c0_x into
st_pll3200c32_cx_x
ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Giuseppe Cavallaro (1):
drivers: clk: st: Fix flexgen lock init
Pankaj Dev (1):
drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
arch/arm/boot/dts/stih407-clock.dtsi | 4 ++--
arch/arm/boot/dts/stih410-clock.dtsi | 4 ++--
arch/arm/boot/dts/stih418-clock.dtsi | 4 ++--
drivers/clk/st/clk-flexgen.c | 4 +++-
drivers/clk/st/clkgen-fsyn.c | 20 +++++++----------
drivers/clk/st/clkgen-mux.c | 25 +++++++++++++---------
drivers/clk/st/clkgen-pll.c | 14 ++++++------
8 files changed, 41 insertions(+), 38 deletions(-)
--
1.9.1
In the clk_summary output, the h/w status of DivMux is incorrect
(Parent and Enable status), since the clk_mux_ops.get_parent()
returns -ERRCODE when clock is OFF.
Signed-off-by: Pankaj Dev <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/st/clkgen-mux.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 4fbe6e0..c94b56b 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -128,7 +128,7 @@ static int clkgena_divmux_is_enabled(struct clk_hw *hw)
__clk_hw_set_clk(mux_hw, hw);
- return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
+ return ((s8)clk_mux_ops.get_parent(mux_hw) >= 0);
}
static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
@@ -138,11 +138,13 @@ static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
__clk_hw_set_clk(mux_hw, hw);
- genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
- if ((s8)genamux->muxsel < 0) {
- pr_debug("%s: %s: Invalid parent, setting to default.\n",
- __func__, __clk_get_name(hw->clk));
- genamux->muxsel = 0;
+ if (genamux->muxsel == CKGAX_CLKOPSRC_SWITCH_OFF) {
+ genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
+ if ((s8)genamux->muxsel < 0) {
+ pr_debug("%s: %s: Invalid parent, setting to default.\n",
+ __func__, __clk_get_name(hw->clk));
+ genamux->muxsel = 0;
+ }
}
return genamux->muxsel;
@@ -254,6 +256,7 @@ static struct clk *clk_register_genamux(const char *name,
} else {
genamux->mux.reg = reg + muxdata->mux_offset;
}
+ genamux->muxsel = CKGAX_CLKOPSRC_SWITCH_OFF;
for (i = 0; i < NUM_INPUTS; i++) {
/*
--
1.9.1
Incorrect register offset used for sthi407 clockgenC
Signed-off-by: Pankaj Dev <[email protected]>
---
drivers/clk/st/clkgen-fsyn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index e94197f..e6d7073 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -340,7 +340,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
CLKGEN_FIELD(0x30c, 0xf, 20),
CLKGEN_FIELD(0x310, 0xf, 20) },
.lockstatus_present = true,
- .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
+ .lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
.powerup_polarity = 1,
.standby_polarity = 1,
.pll_ops = &st_quadfs_pll_c32_ops,
--
1.9.1
Remove this duplicated code due to a bad copy / paste.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/st/clkgen-fsyn.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index e6d7073..e7e6782 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -1082,10 +1082,6 @@ static const struct of_device_id quadfs_of_match[] = {
.compatible = "st,stih407-quadfs660-D",
.data = &st_fs660c32_D_407
},
- {
- .compatible = "st,stih407-quadfs660-D",
- .data = (void *)&st_fs660c32_D_407
- },
{}
};
--
1.9.1
This patch fixes the value for disabling the FSYN channel clock.
The 'is_enabled' returned value is also fixed.
Signed-off-by: Pankaj Dev <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/st/clkgen-fsyn.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index e7e6782..9e26099 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -489,7 +489,7 @@ static int quadfs_pll_is_enabled(struct clk_hw *hw)
struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
u32 npda = CLKGEN_READ(pll, npda);
- return !!npda;
+ return pll->data->powerup_polarity ? !npda : !!npda;
}
static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs,
@@ -774,7 +774,7 @@ static void quadfs_fsynth_disable(struct clk_hw *hw)
if (fs->lock)
spin_lock_irqsave(fs->lock, flags);
- CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
+ CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity);
if (fs->lock)
spin_unlock_irqrestore(fs->lock, flags);
--
1.9.1
From: Giuseppe Cavallaro <[email protected]>
While proving lock, the following warning happens
and it is fixed after initializing lock in the setup
function
INFO: trying to register non-static key.
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.27-02861-g39df285-dirty #33
[<c00154ac>] (unwind_backtrace+0x0/0xf4) from [<c0011b50>] (show_stack+0x10/0x14)
[<c0011b50>] (show_stack+0x10/0x14) from [<c00689ac>] (__lock_acquire+0x900/0xb14)
[<c00689ac>] (__lock_acquire+0x900/0xb14) from [<c0069394>] (lock_acquire+0x68/0x7c)
[<c0069394>] (lock_acquire+0x68/0x7c) from [<c04958f8>] (_raw_spin_lock_irqsave+0x48/0x5c)
[<c04958f8>] (_raw_spin_lock_irqsave+0x48/0x5c) from [<c0381e6c>] (clk_gate_endisable+0x28/0x88)
[<c0381e6c>] (clk_gate_endisable+0x28/0x88) from [<c0381ee0>] (clk_gate_enable+0xc/0x14)
[<c0381ee0>] (clk_gate_enable+0xc/0x14) from [<c0386c68>] (flexgen_enable+0x28/0x40)
[<c0386c68>] (flexgen_enable+0x28/0x40) from [<c037f260>] (__clk_enable+0x5c/0x9c)
[<c037f260>] (__clk_enable+0x5c/0x9c) from [<c037f558>] (clk_enable+0x18/0x2c)
[<c037f558>] (clk_enable+0x18/0x2c) from [<c064a1dc>] (st_lpc_of_register+0xc0/0x248)
[<c064a1dc>] (st_lpc_of_register+0xc0/0x248) from [<c0649e44>] (clocksource_of_init+0x34/0x58)
[<c0649e44>] (clocksource_of_init+0x34/0x58) from [<c0637ddc>] (sti_timer_init+0x10/0x18)
[<c0637ddc>] (sti_timer_init+0x10/0x18) from [<c06343f8>] (time_init+0x20/0x30)
[<c06343f8>] (time_init+0x20/0x30) from [<c0632984>] (start_kernel+0x20c/0x2e8)
[<c0632984>] (start_kernel+0x20c/0x2e8) from [<40008074>] (0x40008074)
Signed-off-by: Giuseppe Cavallaro <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/st/clk-flexgen.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 657ca14..be06d2a 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -303,6 +303,8 @@ static void __init st_of_flexgen_setup(struct device_node *np)
if (!rlock)
goto err;
+ spin_lock_init(rlock);
+
for (i = 0; i < clk_data->clk_num; i++) {
struct clk *clk;
const char *clk_name;
--
1.9.1
From: Pankaj Dev <[email protected]>
Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops,
so that they reflect Hw rate after CPS wake-up when a clk_get_rate()
is called
Signed-off-by: Pankaj Dev <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/st/clk-flexgen.c | 2 +-
drivers/clk/st/clkgen-fsyn.c | 2 +-
drivers/clk/st/clkgen-mux.c | 8 +++++---
drivers/clk/st/clkgen-pll.c | 2 +-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index be06d2a..8dd8cce 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -190,7 +190,7 @@ static struct clk *clk_register_flexgen(const char *name,
init.name = name;
init.ops = &flexgen_ops;
- init.flags = CLK_IS_BASIC | flexgen_flags;
+ init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE | flexgen_flags;
init.parent_names = parent_names;
init.num_parents = num_parents;
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 9e26099..d9eb2e1 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -635,7 +635,7 @@ static struct clk * __init st_clk_register_quadfs_pll(
init.name = name;
init.ops = quadfs->pll_ops;
- init.flags = CLK_IS_BASIC;
+ init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
init.parent_names = &parent_name;
init.num_parents = 1;
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index c94b56b..3919a67 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -239,7 +239,7 @@ static struct clk *clk_register_genamux(const char *name,
init.name = name;
init.ops = &clkgena_divmux_ops;
- init.flags = CLK_IS_BASIC;
+ init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
init.parent_names = parent_names;
init.num_parents = num_parents;
@@ -516,7 +516,8 @@ static void __init st_of_clkgena_prediv_setup(struct device_node *np)
0, &clk_name))
return;
- clk = clk_register_divider_table(NULL, clk_name, parent_name, 0,
+ clk = clk_register_divider_table(NULL, clk_name, parent_name,
+ CLK_GET_RATE_NOCACHE,
reg + data->offset, data->shift, 1,
0, data->table, NULL);
if (IS_ERR(clk))
@@ -789,7 +790,8 @@ static void __init st_of_clkgen_vcc_setup(struct device_node *np)
&mux->hw, &clk_mux_ops,
&div->hw, &clk_divider_ops,
&gate->hw, &clk_gate_ops,
- data->clk_flags);
+ data->clk_flags |
+ CLK_GET_RATE_NOCACHE);
if (IS_ERR(clk)) {
kfree(gate);
kfree(div);
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 1065322..72d1c27 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -406,7 +406,7 @@ static struct clk * __init clkgen_pll_register(const char *parent_name,
init.name = clk_name;
init.ops = pll_data->ops;
- init.flags = CLK_IS_BASIC;
+ init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
init.parent_names = &parent_name;
init.num_parents = 1;
--
1.9.1
This patch fixes the mux bit-setting for ClockgenA9.
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/st/clkgen-mux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 3919a67..ecb492e 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -586,7 +586,7 @@ static struct clkgen_mux_data stih416_a9_mux_data = {
};
static struct clkgen_mux_data stih407_a9_mux_data = {
.offset = 0x1a4,
- .shift = 1,
+ .shift = 0,
.width = 2,
};
--
1.9.1
Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez <[email protected]>
---
drivers/clk/st/clkgen-fsyn.c | 8 ++++----
drivers/clk/st/clkgen-pll.c | 12 ++++++------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index d9eb2e1..a2239cf 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -306,7 +306,7 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
+static const struct clkgen_quadfs_data st_fs660c32_C = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
CLKGEN_FIELD(0x2f0, 0x1, 1),
@@ -349,7 +349,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
.get_rate = clk_fs660c32_dig_get_rate,
};
-static const struct clkgen_quadfs_data st_fs660c32_D_407 = {
+static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
CLKGEN_FIELD(0x2a0, 0x1, 1),
@@ -1076,11 +1076,11 @@ static const struct of_device_id quadfs_of_match[] = {
},
{
.compatible = "st,stih407-quadfs660-C",
- .data = &st_fs660c32_C_407
+ .data = &st_fs660c32_C
},
{
.compatible = "st,stih407-quadfs660-D",
- .data = &st_fs660c32_D_407
+ .data = &st_fs660c32_D
},
{}
};
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 72d1c27..6742b3d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -192,7 +192,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
.ops = &stm_pll3200c32_ops,
};
-static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
+static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
/* 407 C0 PLL0 */
.pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
.locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
@@ -204,7 +204,7 @@ static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
.ops = &stm_pll3200c32_ops,
};
-static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
+static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
.locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
@@ -623,12 +623,12 @@ static const struct of_device_id c32_pll_of_match[] = {
.data = &st_pll3200c32_407_a0,
},
{
- .compatible = "st,stih407-plls-c32-c0_0",
- .data = &st_pll3200c32_407_c0_0,
+ .compatible = "st,plls-c32-cx_0",
+ .data = &st_pll3200c32_cx_0,
},
{
- .compatible = "st,stih407-plls-c32-c0_1",
- .data = &st_pll3200c32_407_c0_1,
+ .compatible = "st,plls-c32-cx_1",
+ .data = &st_pll3200c32_cx_1,
},
{
.compatible = "st,stih407-plls-c32-a9",
--
1.9.1
Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez <[email protected]>
---
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
arch/arm/boot/dts/stih407-clock.dtsi | 4 ++--
arch/arm/boot/dts/stih410-clock.dtsi | 4 ++--
arch/arm/boot/dts/stih418-clock.dtsi | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index efb51cf..d8b168e 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -21,8 +21,8 @@ Required properties:
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
- "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
- "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
+ "sst,plls-c32-cx_0", "st,clkgen-plls-c32"
+ "sst,plls-c32-cx_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index e65744f..ad45f5e 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -134,7 +134,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -143,7 +143,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index 6b5803a..d1f2aca 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -137,7 +137,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -146,7 +146,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 0ab23da..148e177 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -137,7 +137,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -146,7 +146,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
--
1.9.1
On 06/23/2015 07:09 AM, Gabriel Fernandez wrote:
> In the clk_summary output, the h/w status of DivMux is incorrect
> (Parent and Enable status), since the clk_mux_ops.get_parent()
> returns -ERRCODE when clock is OFF.
>
> Signed-off-by: Pankaj Dev <[email protected]>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
> drivers/clk/st/clkgen-mux.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
> index 4fbe6e0..c94b56b 100644
> --- a/drivers/clk/st/clkgen-mux.c
> +++ b/drivers/clk/st/clkgen-mux.c
> @@ -128,7 +128,7 @@ static int clkgena_divmux_is_enabled(struct clk_hw *hw)
>
> __clk_hw_set_clk(mux_hw, hw);
>
> - return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
> + return ((s8)clk_mux_ops.get_parent(mux_hw) >= 0);
Useless parentheses around it all, please drop.
> }
>
> static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
> @@ -138,11 +138,13 @@ static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
>
> __clk_hw_set_clk(mux_hw, hw);
>
> - genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
> - if ((s8)genamux->muxsel < 0) {
> - pr_debug("%s: %s: Invalid parent, setting to default.\n",
> - __func__, __clk_get_name(hw->clk));
> - genamux->muxsel = 0;
> + if (genamux->muxsel == CKGAX_CLKOPSRC_SWITCH_OFF) {
> + genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
Hm.. maybe we should fix clk_mux_ops to return 0 if it can't find the
parent? Or when this clock is registered we should read the hardware and
set a default parent so that we can't get an error code here.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 06/23/2015 07:09 AM, Gabriel Fernandez wrote:
> Incorrect register offset used for sthi407 clockgenC
>
> Signed-off-by: Pankaj Dev <[email protected]>
This needs your Signed-off-by too
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
Hi Stephen,
Thanks for reviewing
On 24 June 2015 at 22:02, Stephen Boyd <[email protected]> wrote:
> On 06/23/2015 07:09 AM, Gabriel Fernandez wrote:
>> In the clk_summary output, the h/w status of DivMux is incorrect
>> (Parent and Enable status), since the clk_mux_ops.get_parent()
>> returns -ERRCODE when clock is OFF.
>>
>> Signed-off-by: Pankaj Dev <[email protected]>
>> Signed-off-by: Gabriel Fernandez <[email protected]>
>> ---
>> drivers/clk/st/clkgen-mux.c | 15 +++++++++------
>> 1 file changed, 9 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
>> index 4fbe6e0..c94b56b 100644
>> --- a/drivers/clk/st/clkgen-mux.c
>> +++ b/drivers/clk/st/clkgen-mux.c
>> @@ -128,7 +128,7 @@ static int clkgena_divmux_is_enabled(struct clk_hw *hw)
>>
>> __clk_hw_set_clk(mux_hw, hw);
>>
>> - return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
>> + return ((s8)clk_mux_ops.get_parent(mux_hw) >= 0);
>
> Useless parentheses around it all, please drop.
>
Ok
>> }
>>
>> static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
>> @@ -138,11 +138,13 @@ static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
>>
>> __clk_hw_set_clk(mux_hw, hw);
>>
>> - genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
>> - if ((s8)genamux->muxsel < 0) {
>> - pr_debug("%s: %s: Invalid parent, setting to default.\n",
>> - __func__, __clk_get_name(hw->clk));
>> - genamux->muxsel = 0;
>> + if (genamux->muxsel == CKGAX_CLKOPSRC_SWITCH_OFF) {
>> + genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
>
> Hm.. maybe we should fix clk_mux_ops to return 0 if it can't find the
> parent? Or when this clock is registered we should read the hardware and
> set a default parent so that we can't get an error code here.
>
I 'll try the second solution.
Best regards
Gabriel
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
On 06/23, Gabriel Fernandez wrote:
> Use a generic name for this kind of PLL
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
Is this just a cleanup/nicety? I could take this patch but patch
9 needs to go through arm-soc and then we have to deal with DT
incompatibility. How about we drop these last two patches?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 06/23, Gabriel Fernandez wrote:
> Remove this duplicated code due to a bad copy / paste.
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 06/23, Gabriel Fernandez wrote:
> This patch fixes the value for disabling the FSYN channel clock.
> The 'is_enabled' returned value is also fixed.
>
> Signed-off-by: Pankaj Dev <[email protected]>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 06/23, Gabriel Fernandez wrote:
> From: Giuseppe Cavallaro <[email protected]>
>
> While proving lock, the following warning happens
> and it is fixed after initializing lock in the setup
> function
>
> INFO: trying to register non-static key.
> the code is fine but needs lockdep annotation.
> turning off the locking correctness validator.
> CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.27-02861-g39df285-dirty #33
> [<c00154ac>] (unwind_backtrace+0x0/0xf4) from [<c0011b50>] (show_stack+0x10/0x14)
> [<c0011b50>] (show_stack+0x10/0x14) from [<c00689ac>] (__lock_acquire+0x900/0xb14)
> [<c00689ac>] (__lock_acquire+0x900/0xb14) from [<c0069394>] (lock_acquire+0x68/0x7c)
> [<c0069394>] (lock_acquire+0x68/0x7c) from [<c04958f8>] (_raw_spin_lock_irqsave+0x48/0x5c)
> [<c04958f8>] (_raw_spin_lock_irqsave+0x48/0x5c) from [<c0381e6c>] (clk_gate_endisable+0x28/0x88)
> [<c0381e6c>] (clk_gate_endisable+0x28/0x88) from [<c0381ee0>] (clk_gate_enable+0xc/0x14)
> [<c0381ee0>] (clk_gate_enable+0xc/0x14) from [<c0386c68>] (flexgen_enable+0x28/0x40)
> [<c0386c68>] (flexgen_enable+0x28/0x40) from [<c037f260>] (__clk_enable+0x5c/0x9c)
> [<c037f260>] (__clk_enable+0x5c/0x9c) from [<c037f558>] (clk_enable+0x18/0x2c)
> [<c037f558>] (clk_enable+0x18/0x2c) from [<c064a1dc>] (st_lpc_of_register+0xc0/0x248)
> [<c064a1dc>] (st_lpc_of_register+0xc0/0x248) from [<c0649e44>] (clocksource_of_init+0x34/0x58)
> [<c0649e44>] (clocksource_of_init+0x34/0x58) from [<c0637ddc>] (sti_timer_init+0x10/0x18)
> [<c0637ddc>] (sti_timer_init+0x10/0x18) from [<c06343f8>] (time_init+0x20/0x30)
> [<c06343f8>] (time_init+0x20/0x30) from [<c0632984>] (start_kernel+0x20c/0x2e8)
> [<c0632984>] (start_kernel+0x20c/0x2e8) from [<40008074>] (0x40008074)
>
> Signed-off-by: Giuseppe Cavallaro <[email protected]>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 06/23, Gabriel Fernandez wrote:
> From: Pankaj Dev <[email protected]>
>
> Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops,
> so that they reflect Hw rate after CPS wake-up when a clk_get_rate()
> is called
>
> Signed-off-by: Pankaj Dev <[email protected]>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 06/23, Gabriel Fernandez wrote:
> This patch fixes the mux bit-setting for ClockgenA9.
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
Hi Stephen,
Sorry for the delay i was in day off.
Yes it's just a cleanup but it's to prepare introduction of new
platform which use this PLL.
If you want apply only fixes we can drop these last two patches.
And in a second phase, deals with Maxime to avoid break compatibility.
BR
Gabriel.
On 2 July 2015 at 18:59, Stephen Boyd <[email protected]> wrote:
> On 06/23, Gabriel Fernandez wrote:
>> Use a generic name for this kind of PLL
>>
>> Signed-off-by: Gabriel Fernandez <[email protected]>
>
> Is this just a cleanup/nicety? I could take this patch but patch
> 9 needs to go through arm-soc and then we have to deal with DT
> incompatibility. How about we drop these last two patches?
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
Hi Stephen,
Can you drop also this patch because it's concerns an old platform and
there no values to make more changes.
BR
Gabriel.
On 25 June 2015 at 10:41, Gabriel Fernandez
<[email protected]> wrote:
> Hi Stephen,
>
> Thanks for reviewing
>
>
> On 24 June 2015 at 22:02, Stephen Boyd <[email protected]> wrote:
>> On 06/23/2015 07:09 AM, Gabriel Fernandez wrote:
>>> In the clk_summary output, the h/w status of DivMux is incorrect
>>> (Parent and Enable status), since the clk_mux_ops.get_parent()
>>> returns -ERRCODE when clock is OFF.
>>>
>>> Signed-off-by: Pankaj Dev <[email protected]>
>>> Signed-off-by: Gabriel Fernandez <[email protected]>
>>> ---
>>> drivers/clk/st/clkgen-mux.c | 15 +++++++++------
>>> 1 file changed, 9 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
>>> index 4fbe6e0..c94b56b 100644
>>> --- a/drivers/clk/st/clkgen-mux.c
>>> +++ b/drivers/clk/st/clkgen-mux.c
>>> @@ -128,7 +128,7 @@ static int clkgena_divmux_is_enabled(struct clk_hw *hw)
>>>
>>> __clk_hw_set_clk(mux_hw, hw);
>>>
>>> - return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
>>> + return ((s8)clk_mux_ops.get_parent(mux_hw) >= 0);
>>
>> Useless parentheses around it all, please drop.
>>
> Ok
>
>>> }
>>>
>>> static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
>>> @@ -138,11 +138,13 @@ static u8 clkgena_divmux_get_parent(struct clk_hw *hw)
>>>
>>> __clk_hw_set_clk(mux_hw, hw);
>>>
>>> - genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
>>> - if ((s8)genamux->muxsel < 0) {
>>> - pr_debug("%s: %s: Invalid parent, setting to default.\n",
>>> - __func__, __clk_get_name(hw->clk));
>>> - genamux->muxsel = 0;
>>> + if (genamux->muxsel == CKGAX_CLKOPSRC_SWITCH_OFF) {
>>> + genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
>>
>> Hm.. maybe we should fix clk_mux_ops to return 0 if it can't find the
>> parent? Or when this clock is registered we should read the hardware and
>> set a default parent so that we can't get an error code here.
>>
> I 'll try the second solution.
>
> Best regards
>
> Gabriel
>> --
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>> a Linux Foundation Collaborative Project
>>
On 07/06/2015 01:11 AM, Gabriel Fernandez wrote:
> Hi Stephen,
>
> Can you drop also this patch because it's concerns an old platform and
> there no values to make more changes.
Ok, so I think this series is all applied then. Let me know if anything
is missing from -next.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 07/06, Stephen Boyd wrote:
> On 07/06/2015 01:11 AM, Gabriel Fernandez wrote:
> > Hi Stephen,
> >
> > Can you drop also this patch because it's concerns an old platform and
> > there no values to make more changes.
>
> Ok, so I think this series is all applied then. Let me know if anything
> is missing from -next.
>
Except for patch 2. Please resend that with your Signed-off-by.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
Hi Gabriel,
On 06/23/2015 04:09 PM, Gabriel Fernandez wrote:
> Use a generic name for this kind of PLL
>
> Signed-off-by: Gabriel Fernandez <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
> arch/arm/boot/dts/stih407-clock.dtsi | 4 ++--
> arch/arm/boot/dts/stih410-clock.dtsi | 4 ++--
> arch/arm/boot/dts/stih418-clock.dtsi | 4 ++--
> 4 files changed, 8 insertions(+), 8 deletions(-)
>
>
Patch applied to sti-dt-for-v4.3.
Thanks!
Maxime