Hi,
It was discovered that all the slow clock user were not properly claiming it.
This can end up in a system hang because the last registered user is releasing
it, and it gets disabled.
commit dca1a4b5ff6e ("clk: at91: keep slow clk enabled to prevent system hang")
was a workaround. This series is adding the slow clock to the necessary drivers
to avoid the issue and then removes that workaround.
The Documentation updates and DT patches should probably go through the AT91
tree this cycle to avoid breakage.
Then the other patches can go through each subsystem tree. They are trivial
enough to also go in this cycle.
The final clk patch depends on the other ones and may be taken for the next
cycle to avoid synchronization issues.
I've thrown in a cleanup for at91-reset as it avoids adding support for that
clock to the platform data initialization
Cc: Alessandro Zummo <[email protected]>
Cc: [email protected]
Cc: Wim Van Sebroeck <[email protected]>
Cc: [email protected]
Cc: Sebastian Reichel <[email protected]>
Cc: Dmitry Eremin-Solenikov <[email protected]>
Cc: [email protected]
Cc: Daniel Lezcano <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Alexandre Belloni (20):
Documentation: dt: atmel-at91: add clocks to system timer, rstc and
shdwc
Documentation: watchdog: at91sam9_wdt: add clocks property
Documentation: dt: rtc: at91rm9200: add clocks property
ARM: at91/dt: at91rm9200: use slow clock where necessary
ARM: at91/dt: at91sam9260: use slow clock where necessary
ARM: at91/dt: at91sam9261: use slow clock where necessary
ARM: at91/dt: at91sam9263: use slow clock where necessary
ARM: at91/dt: at91sam9g45: use slow clock where necessary
ARM: at91/dt: at91sam9n12: use slow clock where necessary
ARM: at91/dt: at91sam9rl: use slow clock where necessary
ARM: at91/dt: at91sam9x5: use slow clock where necessary
ARM: at91/dt: sama5d3: use slow clock where necessary
ARM: at91/dt: sama5d4: use slow clock where necessary
rtc: at91rm9200: get and use slow clock
watchdog: at91sam9: get and use slow clock
power/reset: at91-reset: remove useless at91_reset_platform_probe()
power/reset: at91-reset: get and use slow clock
power/reset: at91-poweroff: get and use slow clock
clocksource: atmel-st: get and use slow clock
clk: at91: Revert "keep slow clk enabled to prevent system hang"
.../devicetree/bindings/arm/atmel-at91.txt | 11 +++--
.../bindings/rtc/atmel,at91rm9200-rtc.txt | 2 +
.../devicetree/bindings/watchdog/atmel-wdt.txt | 2 +
arch/arm/boot/dts/at91rm9200.dtsi | 2 +
arch/arm/boot/dts/at91sam9260.dtsi | 3 ++
arch/arm/boot/dts/at91sam9261.dtsi | 3 ++
arch/arm/boot/dts/at91sam9263.dtsi | 3 ++
arch/arm/boot/dts/at91sam9g45.dtsi | 4 ++
arch/arm/boot/dts/at91sam9n12.dtsi | 4 ++
arch/arm/boot/dts/at91sam9rl.dtsi | 4 ++
arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++
arch/arm/boot/dts/sama5d3.dtsi | 4 ++
arch/arm/boot/dts/sama5d4.dtsi | 4 ++
drivers/clk/at91/clk-slow.c | 27 -------------
drivers/clocksource/timer-atmel-st.c | 31 +++++++++-----
drivers/power/reset/at91-poweroff.c | 13 ++++++
drivers/power/reset/at91-reset.c | 47 ++++++----------------
drivers/rtc/rtc-at91rm9200.c | 27 +++++++++++--
drivers/watchdog/at91sam9_wdt.c | 22 +++++++++-
19 files changed, 138 insertions(+), 79 deletions(-)
--
2.1.4
The system timer (at91rm9200), the reset controller and the shutdown
controller need an input clock. This is the slow clock and they will not
function without it.
Also fix the shutdown controller example.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Sebastian Reichel <[email protected]>
Cc: Dmitry Eremin-Solenikov <[email protected]>
Cc: [email protected]
Documentation/devicetree/bindings/arm/atmel-at91.txt | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 424ac8cbfa08..209710cdf3aa 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -50,6 +50,7 @@ System Timer (ST) required properties:
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for the ST which is the IRQ line
shared across all System Controller members.
+- clocks: phandle to input clock.
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
@@ -89,12 +90,14 @@ RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
<chip> can be "at91sam9260" or "at91sam9g45"
- reg: Should contain registers location and length
+- clocks: phandle to input clock.
Example:
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
};
RAMC SDRAM/DDR Controller required properties:
@@ -117,6 +120,7 @@ required properties:
- compatible: Should be "atmel,<chip>-shdwc".
<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
- reg: Should contain registers location and length
+- clocks: phandle to input clock.
optional properties:
- atmel,wakeup-mode: String, operation mode of the wakeup mode.
@@ -135,9 +139,10 @@ optional at91sam9x5 properties:
Example:
- rstc@fffffd00 {
- compatible = "atmel,at91sam9260-rstc";
- reg = <0xfffffd00 0x10>;
+ shdwc@fffffd10 {
+ compatible = "atmel,at91sam9260-shdwc";
+ reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
};
Special Function Registers (SFR)
--
2.1.4
The watchdog has an input clock, the slow clock. It is required as it will
not function without it.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Wim Van Sebroeck <[email protected]>
Cc: [email protected]
Documentation/devicetree/bindings/watchdog/atmel-wdt.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
index a4d869744f59..86fa6de1019b 100644
--- a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
@@ -6,6 +6,7 @@ Required properties:
- compatible: must be "atmel,at91sam9260-wdt".
- reg: physical base address of the controller and length of memory mapped
region.
+- clocks: phandle to input clock.
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.
@@ -39,6 +40,7 @@ Example:
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
timeout-sec = <15>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
--
2.1.4
The RTC needs an input clock, it is the slow clock. It is required as it
will not function without it.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Alessandro Zummo <[email protected]>
Cc: [email protected]
Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
index 34c1505774bf..5d3791e789c6 100644
--- a/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt
@@ -5,6 +5,7 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: rtc alarm/event interrupt
+- clocks: phandle to input clock.
Example:
@@ -12,4 +13,5 @@ rtc@fffffe00 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x100>;
interrupts = <1 4 7>;
+ clocks = <&clk32k>;
};
--
2.1.4
The system timer and the RTC need the slow clock, add it.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Jean-Christophe Plagniol-Villard <[email protected]>
arch/arm/boot/dts/at91rm9200.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index e3cfb9972f54..385e0c36dece 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -359,6 +359,7 @@
compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
reg = <0xfffffd00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
watchdog {
compatible = "atmel,at91rm9200-wdt";
@@ -369,6 +370,7 @@
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
status = "disabled";
};
--
2.1.4
The watchdog, the reset controller, the real-time timer and the shutdown
controller need the slow clock, add it where necessary.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Jean-Christophe Plagniol-Villard <[email protected]>
arch/arm/boot/dts/at91sam9260.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 4bc347549102..03c1b43cb3ee 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -359,11 +359,13 @@
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffd30 {
@@ -973,6 +975,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
--
2.1.4
The watchdog, the reset controller, the real-time timer and the shutdown
controller need the slow clock, add it where necessary.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Jean-Christophe Plagniol-Villard <[email protected]>
arch/arm/boot/dts/at91sam9261.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index b2c44a07a3d0..4f338d433f3c 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -820,11 +820,13 @@
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&slow_xtal>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
+ clocks = <&slow_xtal>;
};
pit: timer@fffffd30 {
@@ -846,6 +848,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
status = "disabled";
};
--
2.1.4
The watchdog, the reset controller, the two real-time timers and the
shutdown controller need the slow clock, add it where necessary.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Jean-Christophe Plagniol-Villard <[email protected]>
arch/arm/boot/dts/at91sam9263.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index e36d966ef5e8..dc168acfebdd 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -384,11 +384,13 @@
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&slow_xtal>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
+ clocks = <&slow_xtal>;
};
pinctrl@fffff200 {
@@ -902,6 +904,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
--
2.1.4
The watchdog, the reset controller, the RTC, the real-time timer and the
shutdown controller need the slow clock, add it where necessary.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Jean-Christophe Plagniol-Villard <[email protected]>
arch/arm/boot/dts/at91sam9g45.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 18177f5a7464..74e54fb08898 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -387,6 +387,7 @@
rstc@fffffd00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffd30 {
@@ -400,6 +401,7 @@
shdwc@fffffd10 {
compatible = "atmel,at91sam9rl-shdwc";
reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
};
tcb0: timer@fff7c000 {
@@ -1113,6 +1115,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@@ -1247,6 +1250,7 @@
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffdb0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
status = "disabled";
};
--
2.1.4
The watchdog, the reset controller, the RTC and the shutdown controller
need the slow clock, add it where necessary.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Jean-Christophe Plagniol-Villard <[email protected]>
arch/arm/boot/dts/at91sam9n12.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 5c2a8c8c8bd4..b1c2f52dea05 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -376,6 +376,7 @@
rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffe30 {
@@ -388,6 +389,7 @@
shdwc@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>;
+ clocks = <&clk32k>;
};
sckc@fffffe50 {
@@ -891,6 +893,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@@ -901,6 +904,7 @@
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
status = "disabled";
};
--
2.1.4
The watchdog, the reset controller, the RTC, the real-time timer and the
shutdown controller need the slow clock, add it where necessary.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Jean-Christophe Plagniol-Villard <[email protected]>
arch/arm/boot/dts/at91sam9rl.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index c9920c64791c..9ee4a136e3e0 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -1018,11 +1018,13 @@
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffd30 {
@@ -1036,6 +1038,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
status = "disabled";
};
@@ -1083,6 +1086,7 @@
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
status = "disabled";
};
--
2.1.4
The watchdog, the reset controller, the RTC and the shutdown controller
need the slow clock, add it where necessary.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Jean-Christophe Plagniol-Villard <[email protected]>
arch/arm/boot/dts/at91sam9x5.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index b6c8df8d380e..2d8c9f5caff9 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -376,11 +376,13 @@
rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
+ clocks = <&clk32k>;
};
shdwc@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffe30 {
@@ -1173,6 +1175,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@@ -1183,6 +1186,7 @@
compatible = "atmel,at91sam9x5-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
status = "disabled";
};
--
2.1.4
The watchdog, the reset controller, the RTC and the shutdown controller
need the slow clock, add it where necessary.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Jean-Christophe Plagniol-Villard <[email protected]>
arch/arm/boot/dts/sama5d3.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 9e2444b07bce..6e2cfef98ff2 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1261,11 +1261,13 @@
rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
+ clocks = <&clk32k>;
};
shutdown-controller@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffe30 {
@@ -1279,6 +1281,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@@ -1315,6 +1318,7 @@
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffeb0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
};
};
--
2.1.4
The watchdog, the reset controller, the RTC and the shutdown
controller need the slow clock, add it where necessary.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Jean-Christophe Plagniol-Villard <[email protected]>
arch/arm/boot/dts/sama5d4.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 3ee22ee13c5a..d5bec50d14e0 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -1279,11 +1279,13 @@
rstc@fc068600 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfc068600 0x10>;
+ clocks = <&clk32k>;
};
shdwc@fc068610 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfc068610 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fc068630 {
@@ -1296,6 +1298,7 @@
watchdog@fc068640 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfc068640 0x10>;
+ clocks = <&clk32k>;
status = "disabled";
};
@@ -1329,6 +1332,7 @@
compatible = "atmel,at91rm9200-rtc";
reg = <0xfc0686b0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
};
dbgu: serial@fc069000 {
--
2.1.4
Commit dca1a4b5ff6e ("clk: at91: keep slow clk enabled to prevent system
hang") added a workaround for the slow clock as it is not properly handled
by its users.
Get and use the slow clock as it is necessary for the at91rm9200 rtc.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Alessandro Zummo <[email protected]>
Cc: [email protected]
drivers/rtc/rtc-at91rm9200.c | 27 ++++++++++++++++++++++++---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index 35efd3f75b18..8093d9e50619 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -24,6 +24,7 @@
#include <linux/time.h>
#include <linux/rtc.h>
#include <linux/bcd.h>
+#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/ioctl.h>
@@ -59,6 +60,7 @@ static bool suspended;
static DEFINE_SPINLOCK(suspended_lock);
static unsigned long cached_events;
static u32 at91_rtc_imr;
+static struct clk *sclk;
static void at91_rtc_write_ier(u32 mask)
{
@@ -407,6 +409,16 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ sclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(sclk))
+ return PTR_ERR(sclk);
+
+ ret = clk_prepare_enable(sclk);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not enable slow clock\n");
+ return ret;
+ }
+
at91_rtc_write(AT91_RTC_CR, 0);
at91_rtc_write(AT91_RTC_MR, 0); /* 24 hour mode */
@@ -420,7 +432,7 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
"at91_rtc", pdev);
if (ret) {
dev_err(&pdev->dev, "IRQ %d already in use.\n", irq);
- return ret;
+ goto err_clk;
}
/* cpu init code should really have flagged this device as
@@ -431,8 +443,10 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
&at91_rtc_ops, THIS_MODULE);
- if (IS_ERR(rtc))
- return PTR_ERR(rtc);
+ if (IS_ERR(rtc)) {
+ ret = PTR_ERR(rtc);
+ goto err_clk;
+ }
platform_set_drvdata(pdev, rtc);
/* enable SECEV interrupt in order to initialize at91_rtc_upd_rdy
@@ -442,6 +456,11 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
dev_info(&pdev->dev, "AT91 Real Time Clock driver.\n");
return 0;
+
+err_clk:
+ clk_disable_unprepare(sclk);
+
+ return ret;
}
/*
@@ -454,6 +473,8 @@ static int __exit at91_rtc_remove(struct platform_device *pdev)
AT91_RTC_SECEV | AT91_RTC_TIMEV |
AT91_RTC_CALEV);
+ clk_disable_unprepare(sclk);
+
return 0;
}
--
2.1.4
Commit dca1a4b5ff6e ("clk: at91: keep slow clk enabled to prevent system
hang") added a workaround for the slow clock as it is not properly handled
by its users.
Get and use the slow clock as it is necessary for the at91sam9 watchdog.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Wim Van Sebroeck <[email protected]>
Cc: [email protected]
drivers/watchdog/at91sam9_wdt.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c
index e4698f7c5f93..7e6acaf3ece4 100644
--- a/drivers/watchdog/at91sam9_wdt.c
+++ b/drivers/watchdog/at91sam9_wdt.c
@@ -17,6 +17,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/interrupt.h>
@@ -90,6 +91,7 @@ struct at91wdt {
unsigned long heartbeat; /* WDT heartbeat in jiffies */
bool nowayout;
unsigned int irq;
+ struct clk *sclk;
};
/* ......................................................................... */
@@ -352,15 +354,25 @@ static int __init at91wdt_probe(struct platform_device *pdev)
if (IS_ERR(wdt->base))
return PTR_ERR(wdt->base);
+ wdt->sclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(wdt->sclk))
+ return PTR_ERR(wdt->sclk);
+
+ err = clk_prepare_enable(wdt->sclk);
+ if (err) {
+ dev_err(&pdev->dev, "Could not enable slow clock\n");
+ return err;
+ }
+
if (pdev->dev.of_node) {
err = of_at91wdt_init(pdev->dev.of_node, wdt);
if (err)
- return err;
+ goto err_clk;
}
err = at91_wdt_init(pdev, wdt);
if (err)
- return err;
+ goto err_clk;
platform_set_drvdata(pdev, wdt);
@@ -368,6 +380,11 @@ static int __init at91wdt_probe(struct platform_device *pdev)
wdt->wdd.timeout, wdt->nowayout);
return 0;
+
+err_clk:
+ clk_disable_unprepare(wdt->sclk);
+
+ return err;
}
static int __exit at91wdt_remove(struct platform_device *pdev)
@@ -377,6 +394,7 @@ static int __exit at91wdt_remove(struct platform_device *pdev)
pr_warn("I quit now, hardware will probably reboot!\n");
del_timer(&wdt->timer);
+ clk_disable_unprepare(wdt->sclk);
return 0;
}
--
2.1.4
Since all the at91 platforms are now DT only, at91_reset_platform_probe()
is now useless, remove it.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Sebastian Reichel <[email protected]>
Cc: Dmitry Eremin-Solenikov <[email protected]>
Cc: [email protected]
drivers/power/reset/at91-reset.c | 36 +-----------------------------------
1 file changed, 1 insertion(+), 35 deletions(-)
diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c
index 36dc52fb2ec8..3e8f478385c1 100644
--- a/drivers/power/reset/at91-reset.c
+++ b/drivers/power/reset/at91-reset.c
@@ -195,46 +195,12 @@ static int at91_reset_of_probe(struct platform_device *pdev)
return register_restart_handler(&at91_restart_nb);
}
-static int at91_reset_platform_probe(struct platform_device *pdev)
-{
- const struct platform_device_id *match;
- struct resource *res;
- int idx = 0;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- at91_rstc_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(at91_rstc_base)) {
- dev_err(&pdev->dev, "Could not map reset controller address\n");
- return PTR_ERR(at91_rstc_base);
- }
-
- for (idx = 0; idx < 2; idx++) {
- res = platform_get_resource(pdev, IORESOURCE_MEM, idx + 1 );
- at91_ramc_base[idx] = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!at91_ramc_base[idx]) {
- dev_err(&pdev->dev, "Could not map ram controller address\n");
- return -ENOMEM;
- }
- }
-
- match = platform_get_device_id(pdev);
- at91_restart_nb.notifier_call =
- (int (*)(struct notifier_block *,
- unsigned long, void *)) match->driver_data;
-
- return register_restart_handler(&at91_restart_nb);
-}
-
static int at91_reset_probe(struct platform_device *pdev)
{
int ret;
- if (pdev->dev.of_node)
- ret = at91_reset_of_probe(pdev);
- else
- ret = at91_reset_platform_probe(pdev);
+ ret = at91_reset_of_probe(pdev);
if (ret)
return ret;
--
2.1.4
Commit dca1a4b5ff6e ("clk: at91: keep slow clk enabled to prevent system
hang") added a workaround for the slow clock as it is not properly handled
by its users.
Get and use the slow clock as it is necessary for the at91 reset
controller.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Sebastian Reichel <[email protected]>
Cc: Dmitry Eremin-Solenikov <[email protected]>
Cc: [email protected]
drivers/power/reset/at91-reset.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c
index 3e8f478385c1..cd277570af6e 100644
--- a/drivers/power/reset/at91-reset.c
+++ b/drivers/power/reset/at91-reset.c
@@ -11,6 +11,7 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
@@ -46,6 +47,7 @@ enum reset_type {
};
static void __iomem *at91_ramc_base[2], *at91_rstc_base;
+static struct clk *sclk;
/*
* unless the SDRAM is cleanly shutdown before we hit the
@@ -199,6 +201,15 @@ static int at91_reset_probe(struct platform_device *pdev)
{
int ret;
+ sclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(sclk))
+ return PTR_ERR(sclk);
+
+ ret = clk_prepare_enable(sclk);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not enable slow clock\n");
+ return ret;
+ }
ret = at91_reset_of_probe(pdev);
if (ret)
--
2.1.4
Commit dca1a4b5ff6e ("clk: at91: keep slow clk enabled to prevent system
hang") added a workaround for the slow clock as it is not properly handled
by its users.
Get and use the slow clock as it is necessary for the at91 shutdown
controller.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Sebastian Reichel <[email protected]>
Cc: Dmitry Eremin-Solenikov <[email protected]>
Cc: [email protected]
drivers/power/reset/at91-poweroff.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/power/reset/at91-poweroff.c b/drivers/power/reset/at91-poweroff.c
index 9847cfb7e23d..fadd1a41729b 100644
--- a/drivers/power/reset/at91-poweroff.c
+++ b/drivers/power/reset/at91-poweroff.c
@@ -10,6 +10,7 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -48,6 +49,7 @@ static const char *shdwc_wakeup_modes[] = {
};
static void __iomem *at91_shdwc_base;
+static struct clk *sclk;
static void __init at91_wakeup_status(void)
{
@@ -122,6 +124,7 @@ static void at91_poweroff_dt_set_wakeup_mode(struct platform_device *pdev)
static int at91_poweroff_probe(struct platform_device *pdev)
{
struct resource *res;
+ int ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
at91_shdwc_base = devm_ioremap_resource(&pdev->dev, res);
@@ -130,6 +133,16 @@ static int at91_poweroff_probe(struct platform_device *pdev)
return PTR_ERR(at91_shdwc_base);
}
+ sclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(sclk))
+ return PTR_ERR(sclk);
+
+ ret = clk_prepare_enable(sclk);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not enable slow clock\n");
+ return ret;
+ }
+
at91_wakeup_status();
if (pdev->dev.of_node)
--
2.1.4
The current slow clock rate is hardcoded. Properly get the slow clock
and use its rate.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Daniel Lezcano <[email protected]>
Cc: Thomas Gleixner <[email protected]>
drivers/clocksource/timer-atmel-st.c | 31 ++++++++++++++++++++++---------
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/clocksource/timer-atmel-st.c b/drivers/clocksource/timer-atmel-st.c
index 1692e17e096b..c61089d990c6 100644
--- a/drivers/clocksource/timer-atmel-st.c
+++ b/drivers/clocksource/timer-atmel-st.c
@@ -22,6 +22,7 @@
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/export.h>
#include <linux/mfd/syscon.h>
@@ -33,9 +34,8 @@ static unsigned long last_crtr;
static u32 irqmask;
static struct clock_event_device clkevt;
static struct regmap *regmap_st;
-
-#define AT91_SLOW_CLOCK 32768
-#define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ)
+struct clk *sclk;
+int timer_latch;
/*
* The ST_CRTR is updated asynchronously to the master clock ... but
@@ -82,8 +82,8 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
if (sr & AT91_ST_PITS) {
u32 crtr = read_CRTR();
- while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
- last_crtr += RM9200_TIMER_LATCH;
+ while (((crtr - last_crtr) & AT91_ST_CRTV) >= timer_latch) {
+ last_crtr += timer_latch;
clkevt.event_handler(&clkevt);
}
return IRQ_HANDLED;
@@ -120,7 +120,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
case CLOCK_EVT_MODE_PERIODIC:
/* PIT for periodic irqs; fixed rate of 1/HZ */
irqmask = AT91_ST_PITS;
- regmap_write(regmap_st, AT91_ST_PIMR, RM9200_TIMER_LATCH);
+ regmap_write(regmap_st, AT91_ST_PIMR, timer_latch);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* ALM for oneshot irqs, set by next_event()
@@ -182,7 +182,7 @@ static struct clock_event_device clkevt = {
*/
static void __init atmel_st_timer_init(struct device_node *node)
{
- unsigned int val;
+ unsigned int sclk_rate, val;
int irq, ret;
regmap_st = syscon_node_to_regmap(node);
@@ -206,6 +206,19 @@ static void __init atmel_st_timer_init(struct device_node *node)
if (ret)
panic(pr_fmt("Unable to setup IRQ\n"));
+ sclk = of_clk_get(node, 0);
+ if (IS_ERR(sclk))
+ panic(pr_fmt("Unable to get slow clock\n"));
+
+ clk_prepare_enable(sclk);
+ if (ret)
+ panic(pr_fmt("Could not enable slow clock\n"));
+
+ sclk_rate = clk_get_rate(sclk);
+ if (!sclk_rate)
+ panic(pr_fmt("Invalid slow clock rate\n"));
+ timer_latch = (sclk_rate + HZ / 2) / HZ;
+
/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
* directly for the clocksource and all clockevents, after adjusting
* its prescaler from the 1 Hz default.
@@ -214,11 +227,11 @@ static void __init atmel_st_timer_init(struct device_node *node)
/* Setup timer clockevent, with minimum of two ticks (important!!) */
clkevt.cpumask = cpumask_of(0);
- clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
+ clockevents_config_and_register(&clkevt, sclk_rate,
2, AT91_ST_ALMV);
/* register clocksource */
- clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
+ clocksource_register_hz(&clk32k, sclk_rate);
}
CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
atmel_st_timer_init);
--
2.1.4
Commit dca1a4b5ff6e ("clk: at91: keep slow clk enabled to prevent system
hang") added a workaround for the slow clock as it is not properly handled
by its users.
Now that the slow clock is taken properly by the drivers, this workaround
is not necessary anymore, revert it.
Signed-off-by: Alexandre Belloni <[email protected]>
---
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
drivers/clk/at91/clk-slow.c | 27 ---------------------------
1 file changed, 27 deletions(-)
diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c
index 98a84a865fe1..2c59d6a64dd5 100644
--- a/drivers/clk/at91/clk-slow.c
+++ b/drivers/clk/at91/clk-slow.c
@@ -70,7 +70,6 @@ struct clk_sam9x5_slow {
#define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
-static struct clk *slow_clk;
static int clk_slow_osc_prepare(struct clk_hw *hw)
{
@@ -358,8 +357,6 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
clk = clk_register(NULL, &slowck->hw);
if (IS_ERR(clk))
kfree(slowck);
- else
- slow_clk = clk;
return clk;
}
@@ -436,8 +433,6 @@ at91_clk_register_sam9260_slow(struct at91_pmc *pmc,
clk = clk_register(NULL, &slowck->hw);
if (IS_ERR(clk))
kfree(slowck);
- else
- slow_clk = clk;
return clk;
}
@@ -470,25 +465,3 @@ void __init of_at91sam9260_clk_slow_setup(struct device_node *np,
of_clk_add_provider(np, of_clk_src_simple_get, clk);
}
-
-/*
- * FIXME: All slow clk users are not properly claiming it (get + prepare +
- * enable) before using it.
- * If all users properly claiming this clock decide that they don't need it
- * anymore (or are removed), it is disabled while faulty users are still
- * requiring it, and the system hangs.
- * Prevent this clock from being disabled until all users are properly
- * requesting it.
- * Once this is done we should remove this function and the slow_clk variable.
- */
-static int __init of_at91_clk_slow_retain(void)
-{
- if (!slow_clk)
- return 0;
-
- __clk_get(slow_clk);
- clk_prepare_enable(slow_clk);
-
- return 0;
-}
-arch_initcall(of_at91_clk_slow_retain);
--
2.1.4
On 07/29/2015 05:21 PM, Alexandre Belloni wrote:
> The watchdog has an input clock, the slow clock. It is required as it will
> not function without it.
>
> Signed-off-by: Alexandre Belloni <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
On 07/29/2015 05:22 PM, Alexandre Belloni wrote:
> Commit dca1a4b5ff6e ("clk: at91: keep slow clk enabled to prevent system
> hang") added a workaround for the slow clock as it is not properly handled
> by its users.
>
> Get and use the slow clock as it is necessary for the at91sam9 watchdog.
>
> Signed-off-by: Alexandre Belloni <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Dear Alexandre Belloni,
On Thu, 30 Jul 2015 02:22:02 +0200, Alexandre Belloni wrote:
> static int at91_reset_probe(struct platform_device *pdev)
> {
> int ret;
>
> - if (pdev->dev.of_node)
> - ret = at91_reset_of_probe(pdev);
> - else
> - ret = at91_reset_platform_probe(pdev);
>
> + ret = at91_reset_of_probe(pdev);
Maybe it no longer makes sense to have separate at91_reset_probe() and
at91_reset_of_probe() functions then.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Dear Alexandre Belloni,
On Thu, 30 Jul 2015 02:22:05 +0200, Alexandre Belloni wrote:
> -#define AT91_SLOW_CLOCK 32768
> -#define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ)
> +struct clk *sclk;
> +int timer_latch;
static ?
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On 07/30/2015 02:22 AM, Alexandre Belloni wrote:
> The current slow clock rate is hardcoded. Properly get the slow clock
> and use its rate.
>
> Signed-off-by: Alexandre Belloni <[email protected]>
> ---
[ ... ]
> +struct clk *sclk;
Do you need this variable global ? AFAICS, its scope is in the init
function, no ?
> +int timer_latch;
static.
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
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On 04/08/2015 at 12:31:19 +0200, Daniel Lezcano wrote :
> On 07/30/2015 02:22 AM, Alexandre Belloni wrote:
> >The current slow clock rate is hardcoded. Properly get the slow clock
> >and use its rate.
> >
> >Signed-off-by: Alexandre Belloni <[email protected]>
> >---
>
> [ ... ]
>
> >+struct clk *sclk;
>
> Do you need this variable global ? AFAICS, its scope is in the init
> function, no ?
>
Indeed.
> >+int timer_latch;
>
> static.
>
Yeah, this was changed in v2 (that I forgot to label as v2).
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Quoting Alexandre Belloni (2015-07-29 17:22:06)
> Commit dca1a4b5ff6e ("clk: at91: keep slow clk enabled to prevent system
> hang") added a workaround for the slow clock as it is not properly handled
> by its users.
>
> Now that the slow clock is taken properly by the drivers, this workaround
> is not necessary anymore, revert it.
>
> Signed-off-by: Alexandre Belloni <[email protected]>
> ---
> Cc: Michael Turquette <[email protected]>
> Cc: Stephen Boyd <[email protected]>
> Cc: [email protected]
> drivers/clk/at91/clk-slow.c | 27 ---------------------------
> 1 file changed, 27 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c
> index 98a84a865fe1..2c59d6a64dd5 100644
> --- a/drivers/clk/at91/clk-slow.c
> +++ b/drivers/clk/at91/clk-slow.c
> @@ -70,7 +70,6 @@ struct clk_sam9x5_slow {
>
> #define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
>
> -static struct clk *slow_clk;
>
Might want to remove one extra line of white space?
> static int clk_slow_osc_prepare(struct clk_hw *hw)
> {
> @@ -358,8 +357,6 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
> clk = clk_register(NULL, &slowck->hw);
> if (IS_ERR(clk))
> kfree(slowck);
> - else
> - slow_clk = clk;
>
> return clk;
> }
> @@ -436,8 +433,6 @@ at91_clk_register_sam9260_slow(struct at91_pmc *pmc,
> clk = clk_register(NULL, &slowck->hw);
> if (IS_ERR(clk))
> kfree(slowck);
> - else
> - slow_clk = clk;
>
> return clk;
> }
> @@ -470,25 +465,3 @@ void __init of_at91sam9260_clk_slow_setup(struct device_node *np,
>
> of_clk_add_provider(np, of_clk_src_simple_get, clk);
> }
> -
> -/*
> - * FIXME: All slow clk users are not properly claiming it (get + prepare +
> - * enable) before using it.
> - * If all users properly claiming this clock decide that they don't need it
> - * anymore (or are removed), it is disabled while faulty users are still
> - * requiring it, and the system hangs.
> - * Prevent this clock from being disabled until all users are properly
> - * requesting it.
> - * Once this is done we should remove this function and the slow_clk variable.
> - */
> -static int __init of_at91_clk_slow_retain(void)
> -{
> - if (!slow_clk)
> - return 0;
> -
> - __clk_get(slow_clk);
> - clk_prepare_enable(slow_clk);
> -
> - return 0;
> -}
> -arch_initcall(of_at91_clk_slow_retain);
This is a cool series. Thanks. Feel free to add my Ack, or we can take
this through clk-next once the other patches are applied.
Regards,
Mike
> --
> 2.1.4
>
> --
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