Hi everyone,
This series extends irqchip-sunxi-nmi to add support for the NMI
controller found in Allwinner's A80 SoC.
All Allwinner SoCs have an external NMI pin which the PMIC uses to
signal interrupts to the processor. On multi-core chips, there's an
NMI controller handling this pin and chaining interrupts to the GIC.
We already have support for this on previous sun[678]i family chips.
This series extends support to the A80 SoC. This is needed to add
support for the PMICs. A complete series, including PMIC support,
can be found here:
https://github.com/wens/linux/tree/axp809
Patch 1 renames the binding doc, to remove the SoC specific bits from
the filename.
Patch 2 adds a new compatible string for the A80 variant.
Patch 3 adds driver support for the A80 variant.
Patch 4 adds the NMI controller device node to the A80 dtsi file.
Chen-Yu Tsai (4):
irqchip/sunxi-nmi: Rename binding doc filename to
allwinner,sunxi-nmi.txt
irqchip/sunxi-nmi: Add sun9i-a80 variant to binding doc
irqchip/sunxi-nmi: Support sun9i A80 NMI controller
ARM: dts: sun9i: Add NMI controller device node
...{allwinner,sun67i-sc-nmi.txt => allwinner,sunxi-nmi.txt} | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 8 ++++++++
drivers/irqchip/irq-sunxi-nmi.c | 13 +++++++++++++
3 files changed, 22 insertions(+), 1 deletion(-)
rename Documentation/devicetree/bindings/interrupt-controller/{allwinner,sun67i-sc-nmi.txt => allwinner,sunxi-nmi.txt} (94%)
--
2.6.2
The NMI controller is found in all Allwinner multi-core SoCs. It is not
limited to sun[67]i, nor is it always found in the "system controller"
block. On sun[68]i, it is in the RTC block, while on sun9i, it is in the
PRCM block.
Drop these 2 specific bits from the binding doc filename.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
.../{allwinner,sun67i-sc-nmi.txt => allwinner,sunxi-nmi.txt} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/interrupt-controller/{allwinner,sun67i-sc-nmi.txt => allwinner,sunxi-nmi.txt} (100%)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
similarity index 100%
rename from Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt
rename to Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
--
2.6.2
sun9i A80 introduces a new variant of the NMI controller. The registers
are reordered, but the functionality remains the same.
Add a new compatible string for it.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
.../devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
index d1c5cdabc3e0..81cd3692405e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
@@ -4,7 +4,7 @@ Allwinner Sunxi NMI Controller
Required properties:
- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
- "allwinner,sun6i-a31-sc-nmi"
+ "allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
--
2.6.2
The A80 moves the NMI controller into the PRCM address space, and also
rearranges the registers.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
drivers/irqchip/irq-sunxi-nmi.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index 4ef178078e5b..0820f67cc9a7 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -50,6 +50,12 @@ static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
.enable = 0x34,
};
+static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
+ .ctrl = 0x00,
+ .pend = 0x08,
+ .enable = 0x04,
+};
+
static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
u32 val)
{
@@ -207,3 +213,10 @@ static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
}
IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
+
+static int __init sun9i_nmi_irq_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs);
+}
+IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);
--
2.6.2
The Allwinner A80 SoC has an NMI controller. NMI is an external
interrupt pin exclusely used with PMICs and other system critical
peripherals (such as RTC) in Allwinner's reference designs.
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index dc666c69f6ab..e838f206f2a0 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -858,6 +858,14 @@
#reset-cells = <1>;
};
+ nmi_intc: interrupt-controller@080015a0 {
+ compatible = "allwinner,sun9i-a80-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x080015a0 0xc>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
r_ir: ir@08002000 {
compatible = "allwinner,sun5i-a13-ir";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
--
2.6.2
Hi,
On 03-12-15 09:20, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This series extends irqchip-sunxi-nmi to add support for the NMI
> controller found in Allwinner's A80 SoC.
>
> All Allwinner SoCs have an external NMI pin which the PMIC uses to
> signal interrupts to the processor. On multi-core chips, there's an
> NMI controller handling this pin and chaining interrupts to the GIC.
> We already have support for this on previous sun[678]i family chips.
>
> This series extends support to the A80 SoC. This is needed to add
> support for the PMICs. A complete series, including PMIC support,
> can be found here:
>
> https://github.com/wens/linux/tree/axp809
>
> Patch 1 renames the binding doc, to remove the SoC specific bits from
> the filename.
>
> Patch 2 adds a new compatible string for the A80 variant.
>
> Patch 3 adds driver support for the A80 variant.
>
> Patch 4 adds the NMI controller device node to the A80 dtsi file.
>
> Chen-Yu Tsai (4):
> irqchip/sunxi-nmi: Rename binding doc filename to
> allwinner,sunxi-nmi.txt
> irqchip/sunxi-nmi: Add sun9i-a80 variant to binding doc
> irqchip/sunxi-nmi: Support sun9i A80 NMI controller
> ARM: dts: sun9i: Add NMI controller device node
Series looks good to me and is:
Reviewed-by: Hans de Goede <[email protected]>
Regards,
Hans
On Thu, Dec 03, 2015 at 04:20:10PM +0800, Chen-Yu Tsai wrote:
> The NMI controller is found in all Allwinner multi-core SoCs. It is not
> limited to sun[67]i, nor is it always found in the "system controller"
> block. On sun[68]i, it is in the RTC block, while on sun9i, it is in the
> PRCM block.
>
> Drop these 2 specific bits from the binding doc filename.
>
> Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Thu, Dec 03, 2015 at 04:20:11PM +0800, Chen-Yu Tsai wrote:
> sun9i A80 introduces a new variant of the NMI controller. The registers
> are reordered, but the functionality remains the same.
>
> Add a new compatible string for it.
>
> Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Thu, Dec 03, 2015 at 04:20:12PM +0800, Chen-Yu Tsai wrote:
> The A80 moves the NMI controller into the PRCM address space, and also
> rearranges the registers.
>
> Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Thu, Dec 03, 2015 at 04:20:13PM +0800, Chen-Yu Tsai wrote:
> The Allwinner A80 SoC has an NMI controller. NMI is an external
> interrupt pin exclusely used with PMICs and other system critical
> peripherals (such as RTC) in Allwinner's reference designs.
>
> Signed-off-by: Chen-Yu Tsai <[email protected]>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Chen-Yu,
On Thu, Dec 03, 2015 at 04:20:09PM +0800, Chen-Yu Tsai wrote:
> This series extends support to the A80 SoC. This is needed to add
> support for the PMICs. A complete series, including PMIC support,
> can be found here:
>
> https://github.com/wens/linux/tree/axp809
I'll pull all but the last patch in this series into a separate, stable
branch you can base off of at some point today.
thx,
Jason.
On Thu, Dec 03, 2015 at 04:20:09PM +0800, Chen-Yu Tsai wrote:
> Patch 1 renames the binding doc, to remove the SoC specific bits from
> the filename.
>
> Patch 2 adds a new compatible string for the A80 variant.
>
> Patch 3 adds driver support for the A80 variant.
Applied to irqchip/sunxi. Once this has had a day or two in -next, you
can consider it stable. I'll also merge it into irqchip/core around
that time. Added Maxime and Hans' tags.
thx,
Jason.