Hi Andy,
Here are 3 patches for smem/hwspinlock which I have tested with QDSP on IFC6410.
Also a fix from Ivan which I think can be taken aswell.
Thanks,
srini
Ivan T. Ivanov (1):
ARM: dts: qcom: apq8064-ifc6410 Use hardware flow control for GSBI6
Srinivas Kandagatla (3):
arm: dts: apq8064: add shared memory into dt reserved-memory
arm: dts: apq8064: add hwspinlock nodes
arm: dts: apq8064: add shared memory node
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 2 +-
arch/arm/boot/dts/qcom-apq8064.dtsi | 29 +++++++++++++++++++++++++++++
2 files changed, 30 insertions(+), 1 deletion(-)
--
1.9.1
From: "Ivan T. Ivanov" <[email protected]>
GSBI6 UART module is connected to BT chip, which uses
hardware flow control lines. Enable them on SoC side.
Signed-off-by: Ivan T. Ivanov <[email protected]>
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
index 11ac608..80c6695 100644
--- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -164,7 +164,7 @@
gsbi@16500000 {
status = "ok";
- qcom,mode = <GSBI_PROT_I2C_UART>;
+ qcom,mode = <GSBI_PROT_UART_W_FC>;
serial@16540000 {
status = "ok";
--
1.9.1
This patch adds the shared memory in the Device tree reserved memory
list so that kernel would not map it as normal memory.
Signed-off-by: Srinivas Kandagatla <[email protected]>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index a4c1762..09f0e27 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -11,6 +11,17 @@
compatible = "qcom,apq8064";
interrupt-parent = <&intc>;
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ smem:smem@80000000 {
+ reg = <0x80000000 0x200000>;
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
1.9.1
This patch adds support hwspinlock devicetree node.
Signed-off-by: Srinivas Kandagatla <[email protected]>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 09f0e27..829028a 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -670,5 +670,17 @@
compatible = "qcom,tcsr-apq8064", "syscon";
reg = <0x1a400000 0x100>;
};
+
+ sfpb_syscon:syscon@01200600 {
+ compatible = "syscon";
+ reg = <0x01200600 0x100>;
+ };
+
+ sfpb_mutex: hwlock {
+ compatible = "qcom,sfpb-mutex";
+ syscon = <&sfpb_syscon 0x4 0x4>;
+ #hwlock-cells = <1>;
+ };
+
};
};
--
1.9.1
This patch adds support to qcom,smem device.
Signed-off-by: Srinivas Kandagatla <[email protected]>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 829028a..40dd6b4 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -682,5 +682,11 @@
#hwlock-cells = <1>;
};
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem>;
+ hwlocks = <&sfpb_mutex 3>;
+ };
+
};
};
--
1.9.1
On Fri, Dec 11, 2015 at 06:33:09PM +0000, Srinivas Kandagatla wrote:
> This patch adds support to qcom,smem device.
>
> Signed-off-by: Srinivas Kandagatla <[email protected]>
> ---
> arch/arm/boot/dts/qcom-apq8064.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 829028a..40dd6b4 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -682,5 +682,11 @@
> #hwlock-cells = <1>;
> };
>
> + smem {
> + compatible = "qcom,smem";
> + memory-region = <&smem>;
> + hwlocks = <&sfpb_mutex 3>;
> + };
> +
smem needs to be outside the soc as there is no reg entry.
On Fri, Dec 11, 2015 at 06:29:58PM +0000, Srinivas Kandagatla wrote:
> From: "Ivan T. Ivanov" <[email protected]>
>
> GSBI6 UART module is connected to BT chip, which uses
> hardware flow control lines. Enable them on SoC side.
>
> Signed-off-by: Ivan T. Ivanov <[email protected]>
Looks fine to me. Thanks for the patch.
On Fri, Dec 11, 2015 at 06:32:11PM +0000, Srinivas Kandagatla wrote:
> This patch adds support hwspinlock devicetree node.
>
> Signed-off-by: Srinivas Kandagatla <[email protected]>
Looks fine to me. Thanks for the patch.
On Fri, Dec 11, 2015 at 06:31:47PM +0000, Srinivas Kandagatla wrote:
> This patch adds the shared memory in the Device tree reserved memory
> list so that kernel would not map it as normal memory.
>
> Signed-off-by: Srinivas Kandagatla <[email protected]>
Looks fine to me.
On Fri 11 Dec 10:26 PST 2015, Srinivas Kandagatla wrote:
> Hi Andy,
>
> Here are 3 patches for smem/hwspinlock which I have tested with QDSP on IFC6410.
> Also a fix from Ivan which I think can be taken aswell.
>
As far as I can tell my patch for adding smem and hwmutex are already in
linux-next, via Andy's tree. Am I missing something?
Regards,
Bjorn
On 12/12/15 00:22, Bjorn Andersson wrote:
> On Fri 11 Dec 10:26 PST 2015, Srinivas Kandagatla wrote:
>
>> Hi Andy,
>>
>> Here are 3 patches for smem/hwspinlock which I have tested with QDSP on IFC6410.
>> Also a fix from Ivan which I think can be taken aswell.
>>
>
> As far as I can tell my patch for adding smem and hwmutex are already in
> linux-next, via Andy's tree. Am I missing something?
My bad, I should have checked linux-next before sending..
--srini
>
> Regards,
> Bjorn
>