This patch series brings no functional changes.
It prefixes all common port registers macros with MV88E6XXX_PORT.
If registers or some bits differs between switch models, a reference
model is chosen (e.g. MV88E6390_PORT_MAC_CTL_SPEED_10000.)
The register names are documented as found in the datasheets.
Avoid BIT() and shifts defines and prefer a better representation of the
Marvell switch registers with ordered, hexadecimal, 16-bit values.
Vivien Didelot (13):
net: dsa: mv88e6xxx: prefix Port Status macros
net: dsa: mv88e6xxx: prefix Port MAC Control macros
net: dsa: mv88e6xxx: prefix Port Jamming macros
net: dsa: mv88e6xxx: prefix Port Switch ID macros
net: dsa: mv88e6xxx: prefix Port Control macros
net: dsa: mv88e6xxx: prefix Port Control 1 macros
net: dsa: mv88e6xxx: prefix Port Based VLAN macros
net: dsa: mv88e6xxx: prefix Port Default VLAN macros
net: dsa: mv88e6xxx: prefix Port Control 2 macros
net: dsa: mv88e6xxx: prefix Port Egress Rate Control macros
net: dsa: mv88e6xxx: prefix Port Association Vector macros
net: dsa: mv88e6xxx: prefix Port IEEE Priority mapping macros
net: dsa: mv88e6xxx: prefix remaining port macros
drivers/net/dsa/mv88e6xxx/chip.c | 90 ++++-----
drivers/net/dsa/mv88e6xxx/port.c | 336 ++++++++++++++++----------------
drivers/net/dsa/mv88e6xxx/port.h | 379 +++++++++++++++++++++----------------
drivers/net/dsa/mv88e6xxx/serdes.c | 38 ++--
4 files changed, 462 insertions(+), 381 deletions(-)
--
2.13.1
For implicit namespacing and clarity, prefix the common Port Default
VLAN Register macros with MV88E6XXX_PORT_DEFAULT_VLAN.
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 2 +-
drivers/net/dsa/mv88e6xxx/port.c | 15 +++++++++------
drivers/net/dsa/mv88e6xxx/port.h | 6 ++++--
3 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index b1a8cbe1c215..937a43d37f37 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -1950,7 +1950,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
/* Default VLAN ID and priority: don't set a default VLAN
* ID, and set the default packet priority to zero.
*/
- return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
}
static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 3cd3b4b7c944..77e4048962d1 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -706,11 +706,12 @@ int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
u16 reg;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
+ ®);
if (err)
return err;
- *pvid = reg & PORT_DEFAULT_VLAN_MASK;
+ *pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
return 0;
}
@@ -720,14 +721,16 @@ int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
u16 reg;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
+ ®);
if (err)
return err;
- reg &= ~PORT_DEFAULT_VLAN_MASK;
- reg |= pvid & PORT_DEFAULT_VLAN_MASK;
+ reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
+ reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
- err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
+ reg);
if (err)
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 23d94f61cac7..44ac1327e9a2 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -150,8 +150,10 @@
#define MV88E6XXX_PORT_BASE_VLAN 0x06
#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000
-#define PORT_DEFAULT_VLAN 0x07
-#define PORT_DEFAULT_VLAN_MASK 0xfff
+/* Offset 0x07: Default Port VLAN ID & Priority */
+#define MV88E6XXX_PORT_DEFAULT_VLAN 0x07
+#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff
+
#define PORT_CONTROL_2 0x08
#define PORT_CONTROL_2_IGNORE_FCS BIT(15)
#define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
--
2.13.1
For implicit namespacing and clarity, prefix the common Port Control 1
Register macros with MV88E6XXX_PORT_CTL1.
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/port.c | 17 ++++++++++-------
drivers/net/dsa/mv88e6xxx/port.h | 8 +++++---
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index a51d766b3c76..6b972626f326 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -595,16 +595,16 @@ int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
u16 val;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, &val);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1, &val);
if (err)
return err;
if (message_port)
- val |= PORT_CONTROL_1_MESSAGE_PORT;
+ val |= MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
else
- val &= ~PORT_CONTROL_1_MESSAGE_PORT;
+ val &= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT;
- return mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, val);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1, val);
}
/* Offset 0x06: Port Based VLAN Map */
@@ -646,7 +646,8 @@ int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
/* Port's default FID upper bits are located in reg 0x05, offset 0 */
if (upper_mask) {
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
+ ®);
if (err)
return err;
@@ -679,14 +680,16 @@ int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
/* Port's default FID upper bits are located in reg 0x05, offset 0 */
if (upper_mask) {
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL1,
+ ®);
if (err)
return err;
reg &= ~upper_mask;
reg |= (fid >> 4) & upper_mask;
- err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL1,
+ reg);
if (err)
return err;
}
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 880f1b117248..451f99fd81cf 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -141,9 +141,11 @@
#define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002
#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003
-#define PORT_CONTROL_1 0x05
-#define PORT_CONTROL_1_MESSAGE_PORT BIT(15)
-#define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0)
+/* Offset 0x05: Port Control 1 */
+#define MV88E6XXX_PORT_CTL1 0x05
+#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000
+#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff
+
#define PORT_BASE_VLAN 0x06
#define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12)
#define PORT_DEFAULT_VLAN 0x07
--
2.13.1
For implicit namespacing and clarity, prefix the common MAC Control
Register macros with MV88E6XXX_PORT_MAC_CTL and the ones which differ
between implementations with a chosen reference model
(e.g. MV88E6065_PORT_MAC_CTL_SPEED_200.)
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/port.c | 80 +++++++++++++++++++++-------------------
drivers/net/dsa/mv88e6xxx/port.h | 40 ++++++++++----------
2 files changed, 64 insertions(+), 56 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 906b9112e28c..60c31b6c2f47 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -49,23 +49,23 @@ static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
u16 reg;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
if (err)
return err;
- reg &= ~(PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
- PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
+ reg &= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
+ MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK);
switch (mode) {
case PHY_INTERFACE_MODE_RGMII_RXID:
- reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
+ reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK;
break;
case PHY_INTERFACE_MODE_RGMII_TXID:
- reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
+ reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
break;
case PHY_INTERFACE_MODE_RGMII_ID:
- reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
- PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
+ reg |= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK |
+ MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK;
break;
case PHY_INTERFACE_MODE_RGMII:
break;
@@ -73,13 +73,13 @@ static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
return 0;
}
- err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
if (err)
return err;
dev_dbg(chip->dev, "p%d: delay RXCLK %s, TXCLK %s\n", port,
- reg & PORT_PCS_CTRL_RGMII_DELAY_RXCLK ? "yes" : "no",
- reg & PORT_PCS_CTRL_RGMII_DELAY_TXCLK ? "yes" : "no");
+ reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK ? "yes" : "no",
+ reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK ? "yes" : "no");
return 0;
}
@@ -107,18 +107,20 @@ int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
u16 reg;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
if (err)
return err;
- reg &= ~(PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP);
+ reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
+ MV88E6XXX_PORT_MAC_CTL_LINK_UP);
switch (link) {
case LINK_FORCED_DOWN:
- reg |= PORT_PCS_CTRL_FORCE_LINK;
+ reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK;
break;
case LINK_FORCED_UP:
- reg |= PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP;
+ reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK |
+ MV88E6XXX_PORT_MAC_CTL_LINK_UP;
break;
case LINK_UNFORCED:
/* normal link detection */
@@ -127,13 +129,13 @@ int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link)
return -EINVAL;
}
- err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
if (err)
return err;
dev_dbg(chip->dev, "p%d: %s link %s\n", port,
- reg & PORT_PCS_CTRL_FORCE_LINK ? "Force" : "Unforce",
- reg & PORT_PCS_CTRL_LINK_UP ? "up" : "down");
+ reg & MV88E6XXX_PORT_MAC_CTL_FORCE_LINK ? "Force" : "Unforce",
+ reg & MV88E6XXX_PORT_MAC_CTL_LINK_UP ? "up" : "down");
return 0;
}
@@ -143,18 +145,20 @@ int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
u16 reg;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
if (err)
return err;
- reg &= ~(PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL);
+ reg &= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
+ MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL);
switch (dup) {
case DUPLEX_HALF:
- reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
+ reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX;
break;
case DUPLEX_FULL:
- reg |= PORT_PCS_CTRL_FORCE_DUPLEX | PORT_PCS_CTRL_DUPLEX_FULL;
+ reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX |
+ MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL;
break;
case DUPLEX_UNFORCED:
/* normal duplex detection */
@@ -163,13 +167,13 @@ int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup)
return -EINVAL;
}
- err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
if (err)
return err;
dev_dbg(chip->dev, "p%d: %s %s duplex\n", port,
- reg & PORT_PCS_CTRL_FORCE_DUPLEX ? "Force" : "Unforce",
- reg & PORT_PCS_CTRL_DUPLEX_FULL ? "full" : "half");
+ reg & MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX ? "Force" : "Unforce",
+ reg & MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL ? "full" : "half");
return 0;
}
@@ -182,47 +186,49 @@ static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip *chip, int port,
switch (speed) {
case 10:
- ctrl = PORT_PCS_CTRL_SPEED_10;
+ ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_10;
break;
case 100:
- ctrl = PORT_PCS_CTRL_SPEED_100;
+ ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100;
break;
case 200:
if (alt_bit)
- ctrl = PORT_PCS_CTRL_SPEED_100 | PORT_PCS_CTRL_ALTSPEED;
+ ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_100 |
+ MV88E6390_PORT_MAC_CTL_ALTSPEED;
else
- ctrl = PORT_PCS_CTRL_SPEED_200;
+ ctrl = MV88E6065_PORT_MAC_CTL_SPEED_200;
break;
case 1000:
- ctrl = PORT_PCS_CTRL_SPEED_1000;
+ ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_1000;
break;
case 2500:
- ctrl = PORT_PCS_CTRL_SPEED_10000 | PORT_PCS_CTRL_ALTSPEED;
+ ctrl = MV88E6390_PORT_MAC_CTL_SPEED_10000 |
+ MV88E6390_PORT_MAC_CTL_ALTSPEED;
break;
case 10000:
/* all bits set, fall through... */
case SPEED_UNFORCED:
- ctrl = PORT_PCS_CTRL_SPEED_UNFORCED;
+ ctrl = MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED;
break;
default:
return -EOPNOTSUPP;
}
- err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
if (err)
return err;
- reg &= ~PORT_PCS_CTRL_SPEED_MASK;
+ reg &= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK;
if (alt_bit)
- reg &= ~PORT_PCS_CTRL_ALTSPEED;
+ reg &= ~MV88E6390_PORT_MAC_CTL_ALTSPEED;
if (force_bit) {
- reg &= ~PORT_PCS_CTRL_FORCE_SPEED;
+ reg &= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
if (speed != SPEED_UNFORCED)
- ctrl |= PORT_PCS_CTRL_FORCE_SPEED;
+ ctrl |= MV88E6390_PORT_MAC_CTL_FORCE_SPEED;
}
reg |= ctrl;
- err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
if (err)
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index be7cfd979e49..260096b34d2b 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -42,25 +42,27 @@
#define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c
#define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d
-#define PORT_PCS_CTRL 0x01
-#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15)
-#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14)
-#define PORT_PCS_CTRL_FORCE_SPEED BIT(13) /* 6390 */
-#define PORT_PCS_CTRL_ALTSPEED BIT(12) /* 6390 */
-#define PORT_PCS_CTRL_200BASE BIT(12) /* 6352 */
-#define PORT_PCS_CTRL_FC BIT(7)
-#define PORT_PCS_CTRL_FORCE_FC BIT(6)
-#define PORT_PCS_CTRL_LINK_UP BIT(5)
-#define PORT_PCS_CTRL_FORCE_LINK BIT(4)
-#define PORT_PCS_CTRL_DUPLEX_FULL BIT(3)
-#define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2)
-#define PORT_PCS_CTRL_SPEED_MASK (0x03)
-#define PORT_PCS_CTRL_SPEED_10 (0x00)
-#define PORT_PCS_CTRL_SPEED_100 (0x01)
-#define PORT_PCS_CTRL_SPEED_200 (0x02) /* 6065 and non Gb chips */
-#define PORT_PCS_CTRL_SPEED_1000 (0x02)
-#define PORT_PCS_CTRL_SPEED_10000 (0x03) /* 6390X */
-#define PORT_PCS_CTRL_SPEED_UNFORCED (0x03)
+/* Offset 0x01: MAC (or PCS or Physical) Control Register */
+#define MV88E6XXX_PORT_MAC_CTL 0x01
+#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000
+#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000
+#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000
+#define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000
+#define MV88E6352_PORT_MAC_CTL_200BASE 0x1000
+#define MV88E6XXX_PORT_MAC_CTL_FC 0x0080
+#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040
+#define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020
+#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010
+#define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008
+#define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004
+#define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003
+#define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000
+#define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001
+#define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002
+#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002
+#define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003
+#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003
+
#define PORT_PAUSE_CTRL 0x02
#define PORT_FLOW_CTRL_LIMIT_IN ((0x00 << 8) | BIT(15))
#define PORT_FLOW_CTRL_LIMIT_OUT ((0x01 << 8) | BIT(15))
--
2.13.1
For implicit namespacing and clarity, prefix the common Switch ID
Register macros with MV88E6XXX_PORT_SWITCH_ID.
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers, this means shifting their values by 4.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 60 ++++++++++++++++++++--------------------
drivers/net/dsa/mv88e6xxx/port.h | 58 ++++++++++++++++++++------------------
2 files changed, 61 insertions(+), 57 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 0a2bac1cde44..7d0868a45cdc 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2181,7 +2181,7 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
* the mv88e6390 family model number instead.
*/
if (!(val & 0x3f0))
- val |= PORT_SWITCH_ID_PROD_NUM_6390;
+ val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
}
return err ? err : val;
@@ -3162,7 +3162,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
static const struct mv88e6xxx_info mv88e6xxx_table[] = {
[MV88E6085] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
.family = MV88E6XXX_FAMILY_6097,
.name = "Marvell 88E6085",
.num_databases = 4096,
@@ -3180,7 +3180,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6095] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
.family = MV88E6XXX_FAMILY_6095,
.name = "Marvell 88E6095/88E6095F",
.num_databases = 256,
@@ -3197,7 +3197,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6097] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
.family = MV88E6XXX_FAMILY_6097,
.name = "Marvell 88E6097/88E6097F",
.num_databases = 4096,
@@ -3215,7 +3215,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6123] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
.family = MV88E6XXX_FAMILY_6165,
.name = "Marvell 88E6123",
.num_databases = 4096,
@@ -3233,7 +3233,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6131] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
.family = MV88E6XXX_FAMILY_6185,
.name = "Marvell 88E6131",
.num_databases = 256,
@@ -3250,7 +3250,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6141] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
.family = MV88E6XXX_FAMILY_6341,
.name = "Marvell 88E6341",
.num_databases = 4096,
@@ -3267,7 +3267,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6161] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
.family = MV88E6XXX_FAMILY_6165,
.name = "Marvell 88E6161",
.num_databases = 4096,
@@ -3285,7 +3285,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6165] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
.family = MV88E6XXX_FAMILY_6165,
.name = "Marvell 88E6165",
.num_databases = 4096,
@@ -3303,7 +3303,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6171] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
.family = MV88E6XXX_FAMILY_6351,
.name = "Marvell 88E6171",
.num_databases = 4096,
@@ -3321,7 +3321,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6172] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
.family = MV88E6XXX_FAMILY_6352,
.name = "Marvell 88E6172",
.num_databases = 4096,
@@ -3339,7 +3339,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6175] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
.family = MV88E6XXX_FAMILY_6351,
.name = "Marvell 88E6175",
.num_databases = 4096,
@@ -3357,7 +3357,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6176] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
.family = MV88E6XXX_FAMILY_6352,
.name = "Marvell 88E6176",
.num_databases = 4096,
@@ -3375,7 +3375,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6185] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
.family = MV88E6XXX_FAMILY_6185,
.name = "Marvell 88E6185",
.num_databases = 256,
@@ -3392,7 +3392,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6190] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
.family = MV88E6XXX_FAMILY_6390,
.name = "Marvell 88E6190",
.num_databases = 4096,
@@ -3410,7 +3410,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6190X] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
.family = MV88E6XXX_FAMILY_6390,
.name = "Marvell 88E6190X",
.num_databases = 4096,
@@ -3428,7 +3428,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6191] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
.family = MV88E6XXX_FAMILY_6390,
.name = "Marvell 88E6191",
.num_databases = 4096,
@@ -3446,7 +3446,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6240] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
.family = MV88E6XXX_FAMILY_6352,
.name = "Marvell 88E6240",
.num_databases = 4096,
@@ -3464,7 +3464,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6290] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
.family = MV88E6XXX_FAMILY_6390,
.name = "Marvell 88E6290",
.num_databases = 4096,
@@ -3482,7 +3482,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6320] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
.family = MV88E6XXX_FAMILY_6320,
.name = "Marvell 88E6320",
.num_databases = 4096,
@@ -3500,7 +3500,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6321] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
.family = MV88E6XXX_FAMILY_6320,
.name = "Marvell 88E6321",
.num_databases = 4096,
@@ -3517,7 +3517,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6341] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
.family = MV88E6XXX_FAMILY_6341,
.name = "Marvell 88E6341",
.num_databases = 4096,
@@ -3534,7 +3534,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6350] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
.family = MV88E6XXX_FAMILY_6351,
.name = "Marvell 88E6350",
.num_databases = 4096,
@@ -3552,7 +3552,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6351] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
.family = MV88E6XXX_FAMILY_6351,
.name = "Marvell 88E6351",
.num_databases = 4096,
@@ -3570,7 +3570,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
},
[MV88E6352] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
.family = MV88E6XXX_FAMILY_6352,
.name = "Marvell 88E6352",
.num_databases = 4096,
@@ -3587,7 +3587,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.ops = &mv88e6352_ops,
},
[MV88E6390] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
.family = MV88E6XXX_FAMILY_6390,
.name = "Marvell 88E6390",
.num_databases = 4096,
@@ -3604,7 +3604,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.ops = &mv88e6390_ops,
},
[MV88E6390X] = {
- .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
+ .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
.family = MV88E6XXX_FAMILY_6390,
.name = "Marvell 88E6390X",
.num_databases = 4096,
@@ -3641,13 +3641,13 @@ static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
int err;
mutex_lock(&chip->reg_lock);
- err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
+ err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
mutex_unlock(&chip->reg_lock);
if (err)
return err;
- prod_num = (id & 0xfff0) >> 4;
- rev = id & 0x000f;
+ prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
+ rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
info = mv88e6xxx_lookup_info(prod_num);
if (!info)
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 5226a0651d8e..dc99c3159038 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -76,33 +76,37 @@
#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100
#define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff
-#define PORT_SWITCH_ID 0x03
-#define PORT_SWITCH_ID_PROD_NUM_6085 0x04a
-#define PORT_SWITCH_ID_PROD_NUM_6095 0x095
-#define PORT_SWITCH_ID_PROD_NUM_6097 0x099
-#define PORT_SWITCH_ID_PROD_NUM_6131 0x106
-#define PORT_SWITCH_ID_PROD_NUM_6320 0x115
-#define PORT_SWITCH_ID_PROD_NUM_6123 0x121
-#define PORT_SWITCH_ID_PROD_NUM_6141 0x340
-#define PORT_SWITCH_ID_PROD_NUM_6161 0x161
-#define PORT_SWITCH_ID_PROD_NUM_6165 0x165
-#define PORT_SWITCH_ID_PROD_NUM_6171 0x171
-#define PORT_SWITCH_ID_PROD_NUM_6172 0x172
-#define PORT_SWITCH_ID_PROD_NUM_6175 0x175
-#define PORT_SWITCH_ID_PROD_NUM_6176 0x176
-#define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7
-#define PORT_SWITCH_ID_PROD_NUM_6190 0x190
-#define PORT_SWITCH_ID_PROD_NUM_6190X 0x0a0
-#define PORT_SWITCH_ID_PROD_NUM_6191 0x191
-#define PORT_SWITCH_ID_PROD_NUM_6240 0x240
-#define PORT_SWITCH_ID_PROD_NUM_6290 0x290
-#define PORT_SWITCH_ID_PROD_NUM_6321 0x310
-#define PORT_SWITCH_ID_PROD_NUM_6341 0x341
-#define PORT_SWITCH_ID_PROD_NUM_6352 0x352
-#define PORT_SWITCH_ID_PROD_NUM_6350 0x371
-#define PORT_SWITCH_ID_PROD_NUM_6351 0x375
-#define PORT_SWITCH_ID_PROD_NUM_6390 0x390
-#define PORT_SWITCH_ID_PROD_NUM_6390X 0x0a1
+/* Offset 0x03: Switch Identifier Register */
+#define MV88E6XXX_PORT_SWITCH_ID 0x03
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750
+#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900
+#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f
+
#define PORT_CONTROL 0x04
#define PORT_CONTROL_USE_CORE_TAG BIT(15)
#define PORT_CONTROL_DROP_ON_LOCK BIT(14)
--
2.13.1
For implicit namespacing and clarity, prefix the common Port Control 2
Register macros with MV88E6XXX_PORT_CTL2 and the ones which differ
between implementations with a chosen reference model
(e.g. MV88E6095_PORT_CTL2_CPU_PORT_MASK.)
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 6 ++---
drivers/net/dsa/mv88e6xxx/port.c | 48 ++++++++++++++++++++--------------------
drivers/net/dsa/mv88e6xxx/port.h | 44 ++++++++++++++++++------------------
3 files changed, 50 insertions(+), 48 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 937a43d37f37..efc57003b9ee 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -1213,8 +1213,8 @@ static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
bool vlan_filtering)
{
struct mv88e6xxx_chip *chip = ds->priv;
- u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
- PORT_CONTROL_2_8021Q_DISABLED;
+ u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
+ MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
int err;
if (!chip->info->max_vid)
@@ -1872,7 +1872,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
}
err = mv88e6xxx_port_set_8021q_mode(chip, port,
- PORT_CONTROL_2_8021Q_DISABLED);
+ MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
if (err)
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 77e4048962d1..ad86b2e30ac5 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -742,10 +742,10 @@ int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
/* Offset 0x08: Port Control 2 Register */
static const char * const mv88e6xxx_port_8021q_mode_names[] = {
- [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
- [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
- [PORT_CONTROL_2_8021Q_CHECK] = "Check",
- [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
+ [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED] = "Disabled",
+ [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK] = "Fallback",
+ [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK] = "Check",
+ [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE] = "Secure",
};
static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
@@ -754,16 +754,16 @@ static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,
int err;
u16 reg;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
if (err)
return err;
if (multicast)
- reg |= PORT_CONTROL_2_DEFAULT_FORWARD;
+ reg |= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
else
- reg &= ~PORT_CONTROL_2_DEFAULT_FORWARD;
+ reg &= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD;
- return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
}
int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
@@ -784,14 +784,14 @@ int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
int err;
u16 reg;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
if (err)
return err;
- reg &= ~PORT_CONTROL_2_UPSTREAM_MASK;
+ reg &= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK;
reg |= upstream_port;
- return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
}
int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
@@ -800,14 +800,14 @@ int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
u16 reg;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
if (err)
return err;
- reg &= ~PORT_CONTROL_2_8021Q_MASK;
- reg |= mode & PORT_CONTROL_2_8021Q_MASK;
+ reg &= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
+ reg |= mode & MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK;
- err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
if (err)
return err;
@@ -822,13 +822,13 @@ int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)
u16 reg;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
if (err)
return err;
- reg |= PORT_CONTROL_2_MAP_DA;
+ reg |= MV88E6XXX_PORT_CTL2_MAP_DA;
- return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
}
int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
@@ -837,22 +837,22 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
u16 reg;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®);
if (err)
return err;
- reg &= ~PORT_CONTROL_2_JUMBO_MASK;
+ reg &= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK;
if (size <= 1522)
- reg |= PORT_CONTROL_2_JUMBO_1522;
+ reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522;
else if (size <= 2048)
- reg |= PORT_CONTROL_2_JUMBO_2048;
+ reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048;
else if (size <= 10240)
- reg |= PORT_CONTROL_2_JUMBO_10240;
+ reg |= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240;
else
return -ERANGE;
- return mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg);
}
/* Offset 0x09: Port Rate Control */
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 44ac1327e9a2..ce236f06db6d 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -154,27 +154,29 @@
#define MV88E6XXX_PORT_DEFAULT_VLAN 0x07
#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff
-#define PORT_CONTROL_2 0x08
-#define PORT_CONTROL_2_IGNORE_FCS BIT(15)
-#define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
-#define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
-#define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
-#define PORT_CONTROL_2_JUMBO_MASK (0x03 << 12)
-#define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12)
-#define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12)
-#define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12)
-#define PORT_CONTROL_2_8021Q_MASK (0x03 << 10)
-#define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10)
-#define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10)
-#define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10)
-#define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10)
-#define PORT_CONTROL_2_DISCARD_TAGGED BIT(9)
-#define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
-#define PORT_CONTROL_2_MAP_DA BIT(7)
-#define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6)
-#define PORT_CONTROL_2_EGRESS_MONITOR BIT(5)
-#define PORT_CONTROL_2_INGRESS_MONITOR BIT(4)
-#define PORT_CONTROL_2_UPSTREAM_MASK 0x0f
+/* Offset 0x08: Port Control 2 Register */
+#define MV88E6XXX_PORT_CTL2 0x08
+#define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000
+#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000
+#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000
+#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000
+#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000
+#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000
+#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000
+#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000
+#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00
+#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000
+#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400
+#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800
+#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00
+#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200
+#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100
+#define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080
+#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040
+#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020
+#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010
+#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f
+
#define PORT_RATE_CONTROL 0x09
#define PORT_RATE_CONTROL_2 0x0a
#define PORT_ASSOC_VECTOR 0x0b
--
2.13.1
For implicit namespacing and clarity, prefix the common Port Egress Rate
Control and Port Egress Rate Control 2 registers macros with
MV88E6XXX_PORT_EGRESS_RATE_CTL1 and MV88E6XXX_PORT_EGRESS_RATE_CTL2.
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 3 ++-
drivers/net/dsa/mv88e6xxx/port.c | 6 ++++--
drivers/net/dsa/mv88e6xxx/port.h | 8 ++++++--
3 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index efc57003b9ee..8146c94e394d 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -1897,7 +1897,8 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
return err;
/* Egress rate control 2: disable egress rate control. */
- err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
+ 0x0000);
if (err)
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index ad86b2e30ac5..595f842c955b 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -859,12 +859,14 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
{
- return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0000);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
+ 0x0000);
}
int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
{
- return mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 0x0001);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1,
+ 0x0001);
}
/* Offset 0x0C: Port ATU Control */
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index ce236f06db6d..5bcba657a111 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -177,8 +177,12 @@
#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010
#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f
-#define PORT_RATE_CONTROL 0x09
-#define PORT_RATE_CONTROL_2 0x0a
+/* Offset 0x09: Egress Rate Control */
+#define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09
+
+/* Offset 0x0A: Egress Rate Control 2 */
+#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a
+
#define PORT_ASSOC_VECTOR 0x0b
#define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15)
#define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14)
--
2.13.1
For implicit namespacing and clarity, prefix the remaining common Port
Registers macros with MV88E6XXX_PORT.
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 4 ++--
drivers/net/dsa/mv88e6xxx/port.c | 6 +++---
drivers/net/dsa/mv88e6xxx/port.h | 35 +++++++++++++++++++++++++++--------
3 files changed, 32 insertions(+), 13 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index e04e780ffe90..fb950ca29081 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -1729,14 +1729,14 @@ static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
{
return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
MV88E6XXX_EGRESS_MODE_UNMODIFIED,
- PORT_ETH_TYPE_DEFAULT);
+ MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
}
static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
{
return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
MV88E6XXX_EGRESS_MODE_UNMODIFIED,
- PORT_ETH_TYPE_DEFAULT);
+ MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
}
static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 166208f062e3..73d825e08be3 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -873,14 +873,14 @@ int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port)
int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port)
{
- return mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, 0);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ATU_CTL, 0);
}
/* Offset 0x0D: (Priority) Override Register */
int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
{
- return mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, 0);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_PRI_OVERRIDE, 0);
}
/* Offset 0x0f: Port Ether type */
@@ -888,7 +888,7 @@ int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port)
int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
u16 etype)
{
- return mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, etype);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ETH_TYPE, etype);
}
/* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 5144941cb0db..8a34ea7c868a 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -191,14 +191,33 @@
#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000
#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800
-#define PORT_ATU_CONTROL 0x0c
-#define PORT_PRI_OVERRIDE 0x0d
-#define PORT_ETH_TYPE 0x0f
-#define PORT_ETH_TYPE_DEFAULT 0x9100
-#define PORT_IN_DISCARD_LO 0x10
-#define PORT_IN_DISCARD_HI 0x11
-#define PORT_IN_FILTERED 0x12
-#define PORT_OUT_FILTERED 0x13
+/* Offset 0x0C: Port ATU Control */
+#define MV88E6XXX_PORT_ATU_CTL 0x0c
+
+/* Offset 0x0D: Priority Override Register */
+#define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d
+
+/* Offset 0x0E: Policy Control Register */
+#define MV88E6XXX_PORT_POLICY_CTL 0x0e
+
+/* Offset 0x0F: Port Special Ether Type */
+#define MV88E6XXX_PORT_ETH_TYPE 0x0f
+#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100
+
+/* Offset 0x10: InDiscards Low Counter */
+#define MV88E6XXX_PORT_IN_DISCARD_LO 0x10
+
+/* Offset 0x11: InDiscards High Counter */
+#define MV88E6XXX_PORT_IN_DISCARD_HI 0x11
+
+/* Offset 0x12: InFiltered Counter */
+#define MV88E6XXX_PORT_IN_FILTERED 0x12
+
+/* Offset 0x13: OutFiltered Counter */
+#define MV88E6XXX_PORT_OUT_FILTERED 0x13
+
+/* Offset 0x16: LED Control */
+#define MV88E6XXX_PORT_LED_CONTROL 0x16
/* Offset 0x18: IEEE Priority Mapping Table */
#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18
--
2.13.1
For implicit namespacing and clarity, prefix the common Port Status
Register macros with MV88E6XXX_PORT_STS and the ones which differ
between implementations with a chosen reference model
(e.g. MV88E6352_PORT_STS_EEE.)
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 4 ++--
drivers/net/dsa/mv88e6xxx/port.c | 20 ++++++++--------
drivers/net/dsa/mv88e6xxx/port.h | 48 ++++++++++++++++++++------------------
drivers/net/dsa/mv88e6xxx/serdes.c | 38 +++++++++++++++---------------
4 files changed, 56 insertions(+), 54 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index a4cf0366765f..0a2bac1cde44 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -828,11 +828,11 @@ static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
e->eee_enabled = !!(reg & 0x0200);
e->tx_lpi_enabled = !!(reg & 0x0100);
- err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
if (err)
goto out;
- e->eee_active = !!(reg & PORT_STATUS_EEE);
+ e->eee_active = !!(reg & MV88E6352_PORT_STS_EEE);
out:
mutex_unlock(&chip->reg_lock);
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index efeb8d6b02e6..906b9112e28c 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -322,33 +322,33 @@ int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
switch (mode) {
case PHY_INTERFACE_MODE_1000BASEX:
- cmode = PORT_STATUS_CMODE_1000BASE_X;
+ cmode = MV88E6XXX_PORT_STS_CMODE_1000BASE_X;
break;
case PHY_INTERFACE_MODE_SGMII:
- cmode = PORT_STATUS_CMODE_SGMII;
+ cmode = MV88E6XXX_PORT_STS_CMODE_SGMII;
break;
case PHY_INTERFACE_MODE_2500BASEX:
- cmode = PORT_STATUS_CMODE_2500BASEX;
+ cmode = MV88E6XXX_PORT_STS_CMODE_2500BASEX;
break;
case PHY_INTERFACE_MODE_XGMII:
- cmode = PORT_STATUS_CMODE_XAUI;
+ cmode = MV88E6XXX_PORT_STS_CMODE_XAUI;
break;
case PHY_INTERFACE_MODE_RXAUI:
- cmode = PORT_STATUS_CMODE_RXAUI;
+ cmode = MV88E6XXX_PORT_STS_CMODE_RXAUI;
break;
default:
cmode = 0;
}
if (cmode) {
- err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
if (err)
return err;
- reg &= ~PORT_STATUS_CMODE_MASK;
+ reg &= ~MV88E6XXX_PORT_STS_CMODE_MASK;
reg |= cmode;
- err = mv88e6xxx_port_write(chip, port, PORT_STATUS, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
if (err)
return err;
}
@@ -361,11 +361,11 @@ int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
int err;
u16 reg;
- err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
if (err)
return err;
- *cmode = reg & PORT_STATUS_CMODE_MASK;
+ *cmode = reg & MV88E6XXX_PORT_STS_CMODE_MASK;
return 0;
}
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 8a59cabc20fa..be7cfd979e49 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -17,29 +17,31 @@
#include "chip.h"
-#define PORT_STATUS 0x00
-#define PORT_STATUS_PAUSE_EN BIT(15)
-#define PORT_STATUS_MY_PAUSE BIT(14)
-#define PORT_STATUS_HD_FLOW BIT(13)
-#define PORT_STATUS_PHY_DETECT BIT(12)
-#define PORT_STATUS_LINK BIT(11)
-#define PORT_STATUS_DUPLEX BIT(10)
-#define PORT_STATUS_SPEED_MASK 0x0300
-#define PORT_STATUS_SPEED_10 0x0000
-#define PORT_STATUS_SPEED_100 0x0100
-#define PORT_STATUS_SPEED_1000 0x0200
-#define PORT_STATUS_EEE BIT(6) /* 6352 */
-#define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
-#define PORT_STATUS_MGMII BIT(6) /* 6185 */
-#define PORT_STATUS_TX_PAUSED BIT(5)
-#define PORT_STATUS_FLOW_CTRL BIT(4)
-#define PORT_STATUS_CMODE_MASK 0x0f
-#define PORT_STATUS_CMODE_100BASE_X 0x8
-#define PORT_STATUS_CMODE_1000BASE_X 0x9
-#define PORT_STATUS_CMODE_SGMII 0xa
-#define PORT_STATUS_CMODE_2500BASEX 0xb
-#define PORT_STATUS_CMODE_XAUI 0xc
-#define PORT_STATUS_CMODE_RXAUI 0xd
+/* Offset 0x00: Port Status Register */
+#define MV88E6XXX_PORT_STS 0x00
+#define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
+#define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
+#define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
+#define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
+#define MV88E6XXX_PORT_STS_LINK 0x0800
+#define MV88E6XXX_PORT_STS_DUPLEX 0x0400
+#define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300
+#define MV88E6XXX_PORT_STS_SPEED_10 0x0000
+#define MV88E6XXX_PORT_STS_SPEED_100 0x0100
+#define MV88E6XXX_PORT_STS_SPEED_1000 0x0200
+#define MV88E6352_PORT_STS_EEE 0x0040
+#define MV88E6165_PORT_STS_AM_DIS 0x0040
+#define MV88E6185_PORT_STS_MGMII 0x0040
+#define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020
+#define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010
+#define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f
+#define MV88E6XXX_PORT_STS_CMODE_100BASE_X 0x0008
+#define MV88E6XXX_PORT_STS_CMODE_1000BASE_X 0x0009
+#define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a
+#define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b
+#define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c
+#define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d
+
#define PORT_PCS_CTRL 0x01
#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15)
#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14)
diff --git a/drivers/net/dsa/mv88e6xxx/serdes.c b/drivers/net/dsa/mv88e6xxx/serdes.c
index 78f5b1eb44ea..411b4f522792 100644
--- a/drivers/net/dsa/mv88e6xxx/serdes.c
+++ b/drivers/net/dsa/mv88e6xxx/serdes.c
@@ -64,9 +64,9 @@ int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, bool on)
if (err)
return err;
- if ((cmode == PORT_STATUS_CMODE_100BASE_X) ||
- (cmode == PORT_STATUS_CMODE_1000BASE_X) ||
- (cmode == PORT_STATUS_CMODE_SGMII)) {
+ if ((cmode == MV88E6XXX_PORT_STS_CMODE_100BASE_X) ||
+ (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X) ||
+ (cmode == MV88E6XXX_PORT_STS_CMODE_SGMII)) {
err = mv88e6352_serdes_power_set(chip, on);
if (err < 0)
return err;
@@ -139,15 +139,15 @@ static int mv88e6390_serdes_lower(struct mv88e6xxx_chip *chip, u8 cmode,
return err;
switch (cmode_donor) {
- case PORT_STATUS_CMODE_RXAUI:
+ case MV88E6XXX_PORT_STS_CMODE_RXAUI:
if (!rxaui)
break;
/* Fall through */
- case PORT_STATUS_CMODE_1000BASE_X:
- case PORT_STATUS_CMODE_SGMII:
- case PORT_STATUS_CMODE_2500BASEX:
- if (cmode == PORT_STATUS_CMODE_1000BASE_X ||
- cmode == PORT_STATUS_CMODE_SGMII)
+ case MV88E6XXX_PORT_STS_CMODE_1000BASE_X:
+ case MV88E6XXX_PORT_STS_CMODE_SGMII:
+ case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
+ if (cmode == MV88E6XXX_PORT_STS_CMODE_1000BASE_X ||
+ cmode == MV88E6XXX_PORT_STS_CMODE_SGMII)
return mv88e6390_serdes_sgmii(chip, lane, on);
}
return 0;
@@ -157,12 +157,12 @@ static int mv88e6390_serdes_port9(struct mv88e6xxx_chip *chip, u8 cmode,
bool on)
{
switch (cmode) {
- case PORT_STATUS_CMODE_1000BASE_X:
- case PORT_STATUS_CMODE_SGMII:
+ case MV88E6XXX_PORT_STS_CMODE_1000BASE_X:
+ case MV88E6XXX_PORT_STS_CMODE_SGMII:
return mv88e6390_serdes_sgmii(chip, MV88E6390_PORT9_LANE0, on);
- case PORT_STATUS_CMODE_XAUI:
- case PORT_STATUS_CMODE_RXAUI:
- case PORT_STATUS_CMODE_2500BASEX:
+ case MV88E6XXX_PORT_STS_CMODE_XAUI:
+ case MV88E6XXX_PORT_STS_CMODE_RXAUI:
+ case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
return mv88e6390_serdes_10g(chip, MV88E6390_PORT9_LANE0, on);
}
@@ -173,12 +173,12 @@ static int mv88e6390_serdes_port10(struct mv88e6xxx_chip *chip, u8 cmode,
bool on)
{
switch (cmode) {
- case PORT_STATUS_CMODE_SGMII:
+ case MV88E6XXX_PORT_STS_CMODE_SGMII:
return mv88e6390_serdes_sgmii(chip, MV88E6390_PORT10_LANE0, on);
- case PORT_STATUS_CMODE_XAUI:
- case PORT_STATUS_CMODE_RXAUI:
- case PORT_STATUS_CMODE_1000BASE_X:
- case PORT_STATUS_CMODE_2500BASEX:
+ case MV88E6XXX_PORT_STS_CMODE_XAUI:
+ case MV88E6XXX_PORT_STS_CMODE_RXAUI:
+ case MV88E6XXX_PORT_STS_CMODE_1000BASE_X:
+ case MV88E6XXX_PORT_STS_CMODE_2500BASEX:
return mv88e6390_serdes_10g(chip, MV88E6390_PORT10_LANE0, on);
}
--
2.13.1
For implicit namespacing and clarity, prefix the common Port Jamming
Control Register macros with MV88E6XXX_PORT_JAM_CTL and the ones which
differ between implementations with a chosen reference model
(e.g. MV88E6097_PORT_JAM_CTL.)
The 88E6390 family renamed the register to Flow Control and turned it
into an indirect table. Document that as well.
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/port.c | 15 +++++++++------
drivers/net/dsa/mv88e6xxx/port.h | 16 +++++++++++++---
2 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 60c31b6c2f47..615b8843ad8e 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -376,7 +376,7 @@ int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
return 0;
}
-/* Offset 0x02: Pause Control
+/* Offset 0x02: Jamming Control
*
* Do not limit the period of time that this port can be paused for by
* the remote end or the period of time that this port can pause the
@@ -385,7 +385,8 @@ int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
u8 out)
{
- return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, out << 8 | in);
+ return mv88e6xxx_port_write(chip, port, MV88E6097_PORT_JAM_CTL,
+ out << 8 | in);
}
int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
@@ -393,13 +394,15 @@ int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
{
int err;
- err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL,
- PORT_FLOW_CTRL_LIMIT_IN | in);
+ err = mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
+ MV88E6390_PORT_FLOW_CTL_UPDATE |
+ MV88E6390_PORT_FLOW_CTL_LIMIT_IN | in);
if (err)
return err;
- return mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL,
- PORT_FLOW_CTRL_LIMIT_OUT | out);
+ return mv88e6xxx_port_write(chip, port, MV88E6390_PORT_FLOW_CTL,
+ MV88E6390_PORT_FLOW_CTL_UPDATE |
+ MV88E6390_PORT_FLOW_CTL_LIMIT_OUT | out);
}
/* Offset 0x04: Port Control Register */
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 260096b34d2b..5226a0651d8e 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -63,9 +63,19 @@
#define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003
#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003
-#define PORT_PAUSE_CTRL 0x02
-#define PORT_FLOW_CTRL_LIMIT_IN ((0x00 << 8) | BIT(15))
-#define PORT_FLOW_CTRL_LIMIT_OUT ((0x01 << 8) | BIT(15))
+/* Offset 0x02: Jamming Control Register */
+#define MV88E6097_PORT_JAM_CTL 0x02
+#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00
+#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff
+
+/* Offset 0x02: Flow Control Register */
+#define MV88E6390_PORT_FLOW_CTL 0x02
+#define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000
+#define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00
+#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000
+#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100
+#define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff
+
#define PORT_SWITCH_ID 0x03
#define PORT_SWITCH_ID_PROD_NUM_6085 0x04a
#define PORT_SWITCH_ID_PROD_NUM_6095 0x095
--
2.13.1
For implicit namespacing and clarity, prefix the common Port Based VLAN
Register macros with MV88E6XXX_PORT_BASE_VLAN.
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/port.c | 10 +++++-----
drivers/net/dsa/mv88e6xxx/port.h | 6 ++++--
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 6b972626f326..3cd3b4b7c944 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -615,14 +615,14 @@ int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map)
u16 reg;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
if (err)
return err;
reg &= ~mask;
reg |= map & mask;
- err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
if (err)
return err;
@@ -638,7 +638,7 @@ int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid)
int err;
/* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
- err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
if (err)
return err;
@@ -667,14 +667,14 @@ int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid)
return -EINVAL;
/* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
- err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_BASE_VLAN, ®);
if (err)
return err;
reg &= 0x0fff;
reg |= (fid & 0x000f) << 12;
- err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_BASE_VLAN, reg);
if (err)
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 451f99fd81cf..23d94f61cac7 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -146,8 +146,10 @@
#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000
#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff
-#define PORT_BASE_VLAN 0x06
-#define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12)
+/* Offset 0x06: Port Based VLAN Map */
+#define MV88E6XXX_PORT_BASE_VLAN 0x06
+#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000
+
#define PORT_DEFAULT_VLAN 0x07
#define PORT_DEFAULT_VLAN_MASK 0xfff
#define PORT_CONTROL_2 0x08
--
2.13.1
For implicit namespacing and clarity, prefix the common Port Control
Register macros with MV88E6XXX_PORT_CTL0 and the ones which differ
between implementations with a chosen reference model
(e.g. MV88E6185_PORT_CTL0_USE_TAG.)
The reason for CTL0 is to make it clear between the badly named
"Port Control", "Port Control 1" and "Port Control 2" registers.
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 8 ++--
drivers/net/dsa/mv88e6xxx/port.c | 82 ++++++++++++++++++++--------------------
drivers/net/dsa/mv88e6xxx/port.h | 66 ++++++++++++++++----------------
3 files changed, 79 insertions(+), 77 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 7d0868a45cdc..b1a8cbe1c215 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -1828,10 +1828,10 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
* If this is the upstream port for this switch, enable
* forwarding of unknown unicasts and multicasts.
*/
- reg = PORT_CONTROL_IGMP_MLD_SNOOP |
- PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
- PORT_CONTROL_STATE_FORWARDING;
- err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
+ reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
+ MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
+ MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
if (err)
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 615b8843ad8e..a51d766b3c76 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -408,10 +408,10 @@ int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
/* Offset 0x04: Port Control Register */
static const char * const mv88e6xxx_port_state_names[] = {
- [PORT_CONTROL_STATE_DISABLED] = "Disabled",
- [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
- [PORT_CONTROL_STATE_LEARNING] = "Learning",
- [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
+ [MV88E6XXX_PORT_CTL0_STATE_DISABLED] = "Disabled",
+ [MV88E6XXX_PORT_CTL0_STATE_BLOCKING] = "Blocking/Listening",
+ [MV88E6XXX_PORT_CTL0_STATE_LEARNING] = "Learning",
+ [MV88E6XXX_PORT_CTL0_STATE_FORWARDING] = "Forwarding",
};
int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
@@ -419,25 +419,25 @@ int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
u16 reg;
int err;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
if (err)
return err;
- reg &= ~PORT_CONTROL_STATE_MASK;
+ reg &= ~MV88E6XXX_PORT_CTL0_STATE_MASK;
switch (state) {
case BR_STATE_DISABLED:
- state = PORT_CONTROL_STATE_DISABLED;
+ state = MV88E6XXX_PORT_CTL0_STATE_DISABLED;
break;
case BR_STATE_BLOCKING:
case BR_STATE_LISTENING:
- state = PORT_CONTROL_STATE_BLOCKING;
+ state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
break;
case BR_STATE_LEARNING:
- state = PORT_CONTROL_STATE_LEARNING;
+ state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
break;
case BR_STATE_FORWARDING:
- state = PORT_CONTROL_STATE_FORWARDING;
+ state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
break;
default:
return -EINVAL;
@@ -445,7 +445,7 @@ int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state)
reg |= state;
- err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
if (err)
return err;
@@ -461,30 +461,30 @@ int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
int err;
u16 reg;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
if (err)
return err;
- reg &= ~PORT_CONTROL_EGRESS_MASK;
+ reg &= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK;
switch (mode) {
case MV88E6XXX_EGRESS_MODE_UNMODIFIED:
- reg |= PORT_CONTROL_EGRESS_UNMODIFIED;
+ reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED;
break;
case MV88E6XXX_EGRESS_MODE_UNTAGGED:
- reg |= PORT_CONTROL_EGRESS_UNTAGGED;
+ reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED;
break;
case MV88E6XXX_EGRESS_MODE_TAGGED:
- reg |= PORT_CONTROL_EGRESS_TAGGED;
+ reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED;
break;
case MV88E6XXX_EGRESS_MODE_ETHERTYPE:
- reg |= PORT_CONTROL_EGRESS_ADD_TAG;
+ reg |= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA;
break;
default:
return -EINVAL;
}
- return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
}
int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
@@ -493,24 +493,24 @@ int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
int err;
u16 reg;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
if (err)
return err;
- reg &= ~PORT_CONTROL_FRAME_MASK;
+ reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
switch (mode) {
case MV88E6XXX_FRAME_MODE_NORMAL:
- reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
+ reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
break;
case MV88E6XXX_FRAME_MODE_DSA:
- reg |= PORT_CONTROL_FRAME_MODE_DSA;
+ reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
break;
default:
return -EINVAL;
}
- return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
}
int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
@@ -519,30 +519,30 @@ int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
int err;
u16 reg;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
if (err)
return err;
- reg &= ~PORT_CONTROL_FRAME_MASK;
+ reg &= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK;
switch (mode) {
case MV88E6XXX_FRAME_MODE_NORMAL:
- reg |= PORT_CONTROL_FRAME_MODE_NORMAL;
+ reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL;
break;
case MV88E6XXX_FRAME_MODE_DSA:
- reg |= PORT_CONTROL_FRAME_MODE_DSA;
+ reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA;
break;
case MV88E6XXX_FRAME_MODE_PROVIDER:
- reg |= PORT_CONTROL_FRAME_MODE_PROVIDER;
+ reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER;
break;
case MV88E6XXX_FRAME_MODE_ETHERTYPE:
- reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
+ reg |= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA;
break;
default:
return -EINVAL;
}
- return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
}
static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
@@ -551,16 +551,16 @@ static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,
int err;
u16 reg;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
if (err)
return err;
if (unicast)
- reg |= PORT_CONTROL_FORWARD_UNKNOWN;
+ reg |= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
else
- reg &= ~PORT_CONTROL_FORWARD_UNKNOWN;
+ reg &= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN;
- return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
}
int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
@@ -569,22 +569,22 @@ int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
int err;
u16 reg;
- err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
+ err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL0, ®);
if (err)
return err;
- reg &= ~PORT_CONTROL_EGRESS_FLOODS_MASK;
+ reg &= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK;
if (unicast && multicast)
- reg |= PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA;
+ reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA;
else if (unicast)
- reg |= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;
+ reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA;
else if (multicast)
- reg |= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;
+ reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA;
else
- reg |= PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA;
+ reg |= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA;
- return mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
+ return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
}
/* Offset 0x05: Port Control 1 */
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index dc99c3159038..880f1b117248 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -107,38 +107,40 @@
#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900
#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f
-#define PORT_CONTROL 0x04
-#define PORT_CONTROL_USE_CORE_TAG BIT(15)
-#define PORT_CONTROL_DROP_ON_LOCK BIT(14)
-#define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12)
-#define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12)
-#define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12)
-#define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12)
-#define PORT_CONTROL_EGRESS_MASK (0x3 << 12)
-#define PORT_CONTROL_HEADER BIT(11)
-#define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10)
-#define PORT_CONTROL_DOUBLE_TAG BIT(9)
-#define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8)
-#define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8)
-#define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8)
-#define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8)
-#define PORT_CONTROL_FRAME_MASK (0x3 << 8)
-#define PORT_CONTROL_DSA_TAG BIT(8)
-#define PORT_CONTROL_VLAN_TUNNEL BIT(7)
-#define PORT_CONTROL_TAG_IF_BOTH BIT(6)
-#define PORT_CONTROL_USE_IP BIT(5)
-#define PORT_CONTROL_USE_TAG BIT(4)
-#define PORT_CONTROL_FORWARD_UNKNOWN BIT(2)
-#define PORT_CONTROL_EGRESS_FLOODS_MASK (0x3 << 2)
-#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_DA (0x0 << 2)
-#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_MC_DA (0x1 << 2)
-#define PORT_CONTROL_EGRESS_FLOODS_NO_UNKNOWN_UC_DA (0x2 << 2)
-#define PORT_CONTROL_EGRESS_FLOODS_ALL_UNKNOWN_DA (0x3 << 2)
-#define PORT_CONTROL_STATE_MASK 0x03
-#define PORT_CONTROL_STATE_DISABLED 0x00
-#define PORT_CONTROL_STATE_BLOCKING 0x01
-#define PORT_CONTROL_STATE_LEARNING 0x02
-#define PORT_CONTROL_STATE_FORWARDING 0x03
+/* Offset 0x04: Port Control Register */
+#define MV88E6XXX_PORT_CTL0 0x04
+#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000
+#define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK 0x4000
+#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000
+#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000
+#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000
+#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000
+#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000
+#define MV88E6XXX_PORT_CTL0_HEADER 0x0800
+#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400
+#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200
+#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300
+#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000
+#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100
+#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200
+#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300
+#define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100
+#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080
+#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040
+#define MV88E6185_PORT_CTL0_USE_IP 0x0020
+#define MV88E6185_PORT_CTL0_USE_TAG 0x0010
+#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004
+#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK 0x000c
+#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA 0x0000
+#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA 0x0004
+#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA 0x0008
+#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA 0x000c
+#define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003
+#define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000
+#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001
+#define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002
+#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003
+
#define PORT_CONTROL_1 0x05
#define PORT_CONTROL_1_MESSAGE_PORT BIT(15)
#define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0)
--
2.13.1
For implicit namespacing and clarity, prefix the common Port IEEE
Priority Remapping registers macros with MV88E6095_PORT_IEEE_PRIO.
The 88E6390 family turned the 0x18 register into a single indirect
table, document that at the same time.
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Also fix the following checkpatch checks with a temporary variable:
CHECK: Alignment should match open parenthesis
#65: FILE: drivers/net/dsa/mv88e6xxx/port.c:932:
+ err = mv88e6xxx_port_ieeepmt_write(chip, port,
+ MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP,
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/port.c | 37 ++++++++++++++++++++-----------------
drivers/net/dsa/mv88e6xxx/port.h | 30 ++++++++++++++++++------------
2 files changed, 38 insertions(+), 29 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c
index 595f842c955b..166208f062e3 100644
--- a/drivers/net/dsa/mv88e6xxx/port.c
+++ b/drivers/net/dsa/mv88e6xxx/port.c
@@ -900,11 +900,15 @@ int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
int err;
/* Use a direct priority mapping for all IEEE tagged frames */
- err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, 0x3210);
+ err = mv88e6xxx_port_write(chip, port,
+ MV88E6095_PORT_IEEE_PRIO_REMAP_0123,
+ 0x3210);
if (err)
return err;
- return mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, 0x7654);
+ return mv88e6xxx_port_write(chip, port,
+ MV88E6095_PORT_IEEE_PRIO_REMAP_4567,
+ 0x7654);
}
static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
@@ -913,40 +917,39 @@ static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip *chip,
{
u16 reg;
- reg = PORT_IEEE_PRIO_MAP_TABLE_UPDATE |
+ reg = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE |
table |
- (pointer << PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT) |
+ (pointer << MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT) |
data;
- return mv88e6xxx_port_write(chip, port, PORT_IEEE_PRIO_MAP_TABLE, reg);
+ return mv88e6xxx_port_write(chip, port,
+ MV88E6390_PORT_IEEE_PRIO_MAP_TABLE, reg);
}
int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port)
{
int err, i;
+ u16 table;
for (i = 0; i <= 7; i++) {
- err = mv88e6xxx_port_ieeepmt_write(
- chip, port, PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP,
- i, (i | i << 4));
+ table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP;
+ err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i,
+ (i | i << 4));
if (err)
return err;
- err = mv88e6xxx_port_ieeepmt_write(
- chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP,
- i, i);
+ table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP;
+ err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
if (err)
return err;
- err = mv88e6xxx_port_ieeepmt_write(
- chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP,
- i, i);
+ table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP;
+ err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
if (err)
return err;
- err = mv88e6xxx_port_ieeepmt_write(
- chip, port, PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP,
- i, i);
+ table = MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP;
+ err = mv88e6xxx_port_ieeepmt_write(chip, port, table, i, i);
if (err)
return err;
}
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index a855409789c3..5144941cb0db 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -199,18 +199,24 @@
#define PORT_IN_DISCARD_HI 0x11
#define PORT_IN_FILTERED 0x12
#define PORT_OUT_FILTERED 0x13
-#define PORT_TAG_REGMAP_0123 0x18
-#define PORT_TAG_REGMAP_4567 0x19
-#define PORT_IEEE_PRIO_MAP_TABLE 0x18 /* 6390 */
-#define PORT_IEEE_PRIO_MAP_TABLE_UPDATE BIT(15)
-#define PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP (0x0 << 12)
-#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP (0x1 << 12)
-#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP (0x2 << 12)
-#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP (0x3 << 12)
-#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP (0x5 << 12)
-#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP (0x6 << 12)
-#define PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP (0x7 << 12)
-#define PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT 9
+
+/* Offset 0x18: IEEE Priority Mapping Table */
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000
+#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_POINTER_SHIFT 9
+
+/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
+#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18
+
+/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
+#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19
int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
u16 *val);
--
2.13.1
For implicit namespacing and clarity, prefix the common Port Association
Vector Register macros with MV88E6XXX_PORT_ASSOC_VECTOR.
Document the register and prefer ordered hex masks values for all
Marvell 16-bit registers.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 3 ++-
drivers/net/dsa/mv88e6xxx/port.h | 14 ++++++++------
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 8146c94e394d..e04e780ffe90 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -1892,7 +1892,8 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
if (dsa_is_cpu_port(ds, port))
reg = 0;
- err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
+ err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
+ reg);
if (err)
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h
index 5bcba657a111..a855409789c3 100644
--- a/drivers/net/dsa/mv88e6xxx/port.h
+++ b/drivers/net/dsa/mv88e6xxx/port.h
@@ -183,12 +183,14 @@
/* Offset 0x0A: Egress Rate Control 2 */
#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a
-#define PORT_ASSOC_VECTOR 0x0b
-#define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15)
-#define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14)
-#define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13)
-#define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12)
-#define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11)
+/* Offset 0x0B: Port Association Vector */
+#define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b
+#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000
+#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000
+#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000
+#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000
+#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800
+
#define PORT_ATU_CONTROL 0x0c
#define PORT_PRI_OVERRIDE 0x0d
#define PORT_ETH_TYPE 0x0f
--
2.13.1
From: Vivien Didelot <[email protected]>
Date: Mon, 12 Jun 2017 12:37:32 -0400
> This patch series brings no functional changes.
>
> It prefixes all common port registers macros with MV88E6XXX_PORT.
> If registers or some bits differs between switch models, a reference
> model is chosen (e.g. MV88E6390_PORT_MAC_CTL_SPEED_10000.)
>
> The register names are documented as found in the datasheets.
>
> Avoid BIT() and shifts defines and prefer a better representation of the
> Marvell switch registers with ordered, hexadecimal, 16-bit values.
Series applied, thanks.