This patch series is the 2/3 step of the register definitions cleanup.
It brings no functional changes.
It prefixes and documents all Global (1) registers with MV88E6XXX_G1_
(or a specific model like MV88E6352_G1_STS_PPU_STATE), and prefers a
16-bit hexadecimal representation of the Marvell registers layout.
The next and last patchset will prefix the Global 2 registers.
Vivien Didelot (8):
net: dsa: mv88e6xxx: prefix Global Status macros
net: dsa: mv88e6xxx: prefix Global Switch MAC macros
net: dsa: mv88e6xxx: prefix Global ATU macros
net: dsa: mv88e6xxx: prefix Global VTU macros
net: dsa: mv88e6xxx: prefix Global Control macros
net: dsa: mv88e6xxx: prefix Global Monitor Control macros
net: dsa: mv88e6xxx: prefix Global Stats macros
net: dsa: mv88e6xxx: prefix Global Prio and Tag macros
drivers/net/dsa/mv88e6xxx/chip.c | 118 +++++------
drivers/net/dsa/mv88e6xxx/chip.h | 4 +-
drivers/net/dsa/mv88e6xxx/global1.c | 168 ++++++++++------
drivers/net/dsa/mv88e6xxx/global1.h | 343 +++++++++++++++++++-------------
drivers/net/dsa/mv88e6xxx/global1_atu.c | 56 +++---
drivers/net/dsa/mv88e6xxx/global1_vtu.c | 62 +++---
drivers/net/dsa/mv88e6xxx/global2.c | 4 +-
7 files changed, 428 insertions(+), 327 deletions(-)
--
2.13.1
Prefix and document the Global Monitor Control Register macros
(which became the Global Monitor & MGMT Control Register with 88E6390)
and give a clear 16-bit registers representation.
Use __bf_shf to get the shift value at compile time instead of adding
new defined macros for it.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/global1.c | 65 ++++++++++++++++++++++---------------
drivers/net/dsa/mv88e6xxx/global1.h | 38 ++++++++++++----------
2 files changed, 60 insertions(+), 43 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c
index 63e3ad1ba52a..ee77840d5271 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.c
+++ b/drivers/net/dsa/mv88e6xxx/global1.c
@@ -12,6 +12,8 @@
* (at your option) any later version.
*/
+#include <linux/bitfield.h>
+
#include "chip.h"
#include "global1.h"
@@ -247,17 +249,17 @@ int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
u16 reg;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_MONITOR_CONTROL, ®);
+ err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
if (err)
return err;
- reg &= ~(GLOBAL_MONITOR_CONTROL_INGRESS_MASK |
- GLOBAL_MONITOR_CONTROL_EGRESS_MASK);
+ reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK |
+ MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
- reg |= port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
- port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT;
+ reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) |
+ port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
- return mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
+ return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
}
/* Older generations also call this the ARP destination. It has been
@@ -269,14 +271,14 @@ int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
u16 reg;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_MONITOR_CONTROL, ®);
+ err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®);
if (err)
return err;
- reg &= ~GLOBAL_MONITOR_CONTROL_ARP_MASK;
- reg |= port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
+ reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
+ reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
- return mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
+ return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
}
static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
@@ -284,55 +286,66 @@ static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
{
u16 reg;
- reg = GLOBAL_MONITOR_CONTROL_UPDATE | pointer | data;
+ reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
- return mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg);
+ return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
}
int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port)
{
+ u16 ptr;
int err;
- err = mv88e6390_g1_monitor_write(chip, GLOBAL_MONITOR_CONTROL_INGRESS,
- port);
+ ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
+ err = mv88e6390_g1_monitor_write(chip, ptr, port);
if (err)
return err;
- return mv88e6390_g1_monitor_write(chip, GLOBAL_MONITOR_CONTROL_EGRESS,
- port);
+ ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
+ err = mv88e6390_g1_monitor_write(chip, ptr, port);
+ if (err)
+ return err;
+
+ return 0;
}
int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
{
- return mv88e6390_g1_monitor_write(chip, GLOBAL_MONITOR_CONTROL_CPU_DEST,
- port);
+ u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
+
+ return mv88e6390_g1_monitor_write(chip, ptr, port);
}
int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
{
+ u16 ptr;
int err;
/* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */
- err = mv88e6390_g1_monitor_write(
- chip, GLOBAL_MONITOR_CONTROL_0180C280000000XLO, 0xff);
+ ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO;
+ err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
if (err)
return err;
/* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */
- err = mv88e6390_g1_monitor_write(
- chip, GLOBAL_MONITOR_CONTROL_0180C280000000XHI, 0xff);
+ ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI;
+ err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
if (err)
return err;
/* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */
- err = mv88e6390_g1_monitor_write(
- chip, GLOBAL_MONITOR_CONTROL_0180C280000002XLO, 0xff);
+ ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO;
+ err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
if (err)
return err;
/* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */
- return mv88e6390_g1_monitor_write(
- chip, GLOBAL_MONITOR_CONTROL_0180C280000002XHI, 0xff);
+ ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI;
+ err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
+ if (err)
+ return err;
+
+ return 0;
}
/* Offset 0x1c: Global Control 2 */
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index af1a510f7a45..020b21c0c9c3 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -156,23 +156,27 @@
#define GLOBAL_IP_PRI_7 0x17
#define GLOBAL_IEEE_PRI 0x18
#define GLOBAL_CORE_TAG_TYPE 0x19
-#define GLOBAL_MONITOR_CONTROL 0x1a
-#define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12
-#define GLOBAL_MONITOR_CONTROL_INGRESS_MASK (0xf << 12)
-#define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8
-#define GLOBAL_MONITOR_CONTROL_EGRESS_MASK (0xf << 8)
-#define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4
-#define GLOBAL_MONITOR_CONTROL_ARP_MASK (0xf << 4)
-#define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0
-#define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0)
-#define GLOBAL_MONITOR_CONTROL_UPDATE BIT(15)
-#define GLOBAL_MONITOR_CONTROL_0180C280000000XLO (0x00 << 8)
-#define GLOBAL_MONITOR_CONTROL_0180C280000000XHI (0x01 << 8)
-#define GLOBAL_MONITOR_CONTROL_0180C280000002XLO (0x02 << 8)
-#define GLOBAL_MONITOR_CONTROL_0180C280000002XHI (0x03 << 8)
-#define GLOBAL_MONITOR_CONTROL_INGRESS (0x20 << 8)
-#define GLOBAL_MONITOR_CONTROL_EGRESS (0x21 << 8)
-#define GLOBAL_MONITOR_CONTROL_CPU_DEST (0x30 << 8)
+
+/* Offset 0x1A: Monitor Control */
+#define MV88E6185_G1_MONITOR_CTL 0x1a
+#define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000
+#define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00
+#define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0
+#define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0
+#define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f
+
+/* Offset 0x1A: Monitor & MGMT Control Register */
+#define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a
+#define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000
+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00
+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO 0x0000
+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI 0x0100
+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO 0x0200
+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI 0x0300
+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000
+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100
+#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000
+#define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff
/* Offset 0x1C: Global Control 2 */
#define MV88E6XXX_G1_CTL2 0x1c
--
2.13.1
Prefix and document the Global Stats Operation and Counter registers and
give them a clear 16-bit registers representation.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 14 ++++++++------
drivers/net/dsa/mv88e6xxx/global1.c | 24 ++++++++++++++----------
drivers/net/dsa/mv88e6xxx/global1.h | 33 +++++++++++++++++++--------------
3 files changed, 41 insertions(+), 30 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index c31ad01c7f96..46e8d1871847 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -725,7 +725,7 @@ static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
{
return mv88e6xxx_stats_get_stats(chip, port, data,
STATS_TYPE_BANK0 | STATS_TYPE_PORT,
- 0, GLOBAL_STATS_OP_HIST_RX_TX);
+ 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
}
static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
@@ -733,8 +733,8 @@ static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
{
return mv88e6xxx_stats_get_stats(chip, port, data,
STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
- GLOBAL_STATS_OP_BANK_1_BIT_9,
- GLOBAL_STATS_OP_HIST_RX_TX);
+ MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
+ MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
}
static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
@@ -742,7 +742,8 @@ static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
{
return mv88e6xxx_stats_get_stats(chip, port, data,
STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
- GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
+ MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
+ 0);
}
static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
@@ -2057,8 +2058,9 @@ static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
return err;
/* Clear the statistics counters for all ports */
- err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
- GLOBAL_STATS_OP_FLUSH_ALL);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
+ MV88E6XXX_G1_STATS_OP_BUSY |
+ MV88E6XXX_G1_STATS_OP_FLUSH_ALL);
if (err)
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c
index ee77840d5271..d76d7c7ea819 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.c
+++ b/drivers/net/dsa/mv88e6xxx/global1.c
@@ -370,7 +370,8 @@ int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
{
- return mv88e6xxx_g1_wait(chip, GLOBAL_STATS_OP, GLOBAL_STATS_OP_BUSY);
+ return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP,
+ MV88E6XXX_G1_STATS_OP_BUSY);
}
int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
@@ -378,9 +379,10 @@ int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
int err;
/* Snapshot the hardware statistics counters for this port. */
- err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
- GLOBAL_STATS_OP_CAPTURE_PORT |
- GLOBAL_STATS_OP_HIST_RX_TX | port);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
+ MV88E6XXX_G1_STATS_OP_BUSY |
+ MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
+ MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
if (err)
return err;
@@ -402,8 +404,9 @@ int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
port = (port + 1) << 5;
/* Snapshot the hardware statistics counters for this port. */
- err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
- GLOBAL_STATS_OP_CAPTURE_PORT | port);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
+ MV88E6XXX_G1_STATS_OP_BUSY |
+ MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
if (err)
return err;
@@ -419,8 +422,9 @@ void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
*val = 0;
- err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
- GLOBAL_STATS_OP_READ_CAPTURED | stat);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
+ MV88E6XXX_G1_STATS_OP_BUSY |
+ MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
if (err)
return;
@@ -428,13 +432,13 @@ void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
if (err)
return;
- err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, ®);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®);
if (err)
return;
value = reg << 16;
- err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, ®);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®);
if (err)
return;
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index 020b21c0c9c3..16c21bd671c5 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -186,20 +186,25 @@
#define MV88E6XXX_G1_CTL2_HIST_TX 0x0080
#define MV88E6XXX_G1_CTL2_HIST_RX_TX 0x00c0
-#define GLOBAL_STATS_OP 0x1d
-#define GLOBAL_STATS_OP_BUSY BIT(15)
-#define GLOBAL_STATS_OP_NOP (0 << 12)
-#define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY)
-#define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY)
-#define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY)
-#define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY)
-#define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY)
-#define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY)
-#define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY)
-#define GLOBAL_STATS_OP_BANK_1_BIT_9 BIT(9)
-#define GLOBAL_STATS_OP_BANK_1_BIT_10 BIT(10)
-#define GLOBAL_STATS_COUNTER_32 0x1e
-#define GLOBAL_STATS_COUNTER_01 0x1f
+/* Offset 0x1D: Stats Operation Register */
+#define MV88E6XXX_G1_STATS_OP 0x1d
+#define MV88E6XXX_G1_STATS_OP_BUSY 0x8000
+#define MV88E6XXX_G1_STATS_OP_NOP 0x0000
+#define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000
+#define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000
+#define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000
+#define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000
+#define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400
+#define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800
+#define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00
+#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200
+#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400
+
+/* Offset 0x1E: Stats Counter Register Bytes 3 & 2
+ * Offset 0x1F: Stats Counter Register Bytes 1 & 0
+ */
+#define MV88E6XXX_G1_STATS_COUNTER_32 0x1e
+#define MV88E6XXX_G1_STATS_COUNTER_01 0x1f
int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
--
2.13.1
Prefix and document the Global ATU Registers macros and give clear
16-bit registers representation.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 22 +++++-----
drivers/net/dsa/mv88e6xxx/global1.h | 75 +++++++++++++++++++--------------
drivers/net/dsa/mv88e6xxx/global1_atu.c | 56 ++++++++++++------------
3 files changed, 85 insertions(+), 68 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index b048f851786a..066fa63c6b6e 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -1383,7 +1383,7 @@ static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
if (err)
return err;
- entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
+ entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
ether_addr_copy(entry.mac, addr);
eth_addr_dec(entry.mac);
@@ -1392,17 +1392,17 @@ static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
return err;
/* Initialize a fresh ATU entry if it isn't found */
- if (entry.state == GLOBAL_ATU_DATA_STATE_UNUSED ||
+ if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
!ether_addr_equal(entry.mac, addr)) {
memset(&entry, 0, sizeof(entry));
ether_addr_copy(entry.mac, addr);
}
/* Purge the ATU entry only if no port is using it anymore */
- if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
+ if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
entry.portvec &= ~BIT(port);
if (!entry.portvec)
- entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
+ entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
} else {
entry.portvec |= BIT(port);
entry.state = state;
@@ -1429,7 +1429,7 @@ static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
mutex_lock(&chip->reg_lock);
if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
- GLOBAL_ATU_DATA_STATE_UC_STATIC))
+ MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC))
dev_err(ds->dev, "p%d: failed to load unicast MAC address\n",
port);
mutex_unlock(&chip->reg_lock);
@@ -1443,7 +1443,7 @@ static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
mutex_lock(&chip->reg_lock);
err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
- GLOBAL_ATU_DATA_STATE_UNUSED);
+ MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
mutex_unlock(&chip->reg_lock);
return err;
@@ -1457,7 +1457,7 @@ static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
struct mv88e6xxx_atu_entry addr;
int err;
- addr.state = GLOBAL_ATU_DATA_STATE_UNUSED;
+ addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
eth_broadcast_addr(addr.mac);
do {
@@ -1465,7 +1465,7 @@ static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
if (err)
return err;
- if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
+ if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
break;
if (addr.trunk || (addr.portvec & BIT(port)) == 0)
@@ -1480,7 +1480,7 @@ static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
fdb->vid = vid;
ether_addr_copy(fdb->addr, addr.mac);
- if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
+ if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
fdb->ndm_state = NUD_NOARP;
else
fdb->ndm_state = NUD_REACHABLE;
@@ -3755,7 +3755,7 @@ static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
mutex_lock(&chip->reg_lock);
if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
- GLOBAL_ATU_DATA_STATE_MC_STATIC))
+ MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
port);
mutex_unlock(&chip->reg_lock);
@@ -3769,7 +3769,7 @@ static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
mutex_lock(&chip->reg_lock);
err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
- GLOBAL_ATU_DATA_STATE_UNUSED);
+ MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
mutex_unlock(&chip->reg_lock);
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index 267233d40cb3..126515532d53 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -44,7 +44,9 @@
#define MV88E6XXX_G1_MAC_23 0x02
#define MV88E6XXX_G1_MAC_45 0x03
-#define GLOBAL_ATU_FID 0x01
+/* Offset 0x01: ATU FID Register */
+#define MV88E6352_G1_ATU_FID 0x01
+
#define GLOBAL_VTU_FID 0x02
#define GLOBAL_VTU_FID_MASK 0xfff
#define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */
@@ -87,36 +89,47 @@
#define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01
#define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02
#define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03
-#define GLOBAL_ATU_CONTROL 0x0a
-#define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3)
-#define GLOBAL_ATU_OP 0x0b
-#define GLOBAL_ATU_OP_BUSY BIT(15)
-#define GLOBAL_ATU_OP_NOP (0 << 12)
-#define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
-#define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY)
-#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
-#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
-#define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
-#define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
-#define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY)
-#define GLOBAL_ATU_DATA 0x0c
-#define GLOBAL_ATU_DATA_TRUNK BIT(15)
-#define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0
-#define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4
-#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
-#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
-#define GLOBAL_ATU_DATA_STATE_MASK 0x0f
-#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
-#define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d
-#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
-#define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f
-#define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05
-#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
-#define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e
-#define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f
-#define GLOBAL_ATU_MAC_01 0x0d
-#define GLOBAL_ATU_MAC_23 0x0e
-#define GLOBAL_ATU_MAC_45 0x0f
+
+/* Offset 0x0A: ATU Control Register */
+#define MV88E6XXX_G1_ATU_CTL 0x0a
+#define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008
+
+/* Offset 0x0B: ATU Operation Register */
+#define MV88E6XXX_G1_ATU_OP 0x0b
+#define MV88E6XXX_G1_ATU_OP_BUSY 0x8000
+#define MV88E6XXX_G1_ATU_OP_MASK 0x7000
+#define MV88E6XXX_G1_ATU_OP_NOOP 0x0000
+#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000
+#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000
+#define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000
+#define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000
+#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000
+#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000
+#define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000
+
+/* Offset 0x0C: ATU Data Register */
+#define MV88E6XXX_G1_ATU_DATA 0x0c
+#define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000
+#define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0
+#define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
+#define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f
+#define MV88E6XXX_G1_ATU_DATA_STATE_UNUSED 0x0000
+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_MGMT 0x000d
+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e
+#define MV88E6XXX_G1_ATU_DATA_STATE_UC_PRIO_OVER 0x000f
+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_NONE_RATE 0x0005
+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007
+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_MGMT 0x000e
+#define MV88E6XXX_G1_ATU_DATA_STATE_MC_PRIO_OVER 0x000f
+
+/* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
+ * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
+ * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
+ */
+#define MV88E6XXX_G1_ATU_MAC01 0x0d
+#define MV88E6XXX_G1_ATU_MAC23 0x0e
+#define MV88E6XXX_G1_ATU_MAC45 0x0f
+
#define GLOBAL_IP_PRI_0 0x10
#define GLOBAL_IP_PRI_1 0x11
#define GLOBAL_IP_PRI_2 0x12
diff --git a/drivers/net/dsa/mv88e6xxx/global1_atu.c b/drivers/net/dsa/mv88e6xxx/global1_atu.c
index 6b0cf44dc07d..efeef4b01442 100644
--- a/drivers/net/dsa/mv88e6xxx/global1_atu.c
+++ b/drivers/net/dsa/mv88e6xxx/global1_atu.c
@@ -17,7 +17,7 @@
static int mv88e6xxx_g1_atu_fid_write(struct mv88e6xxx_chip *chip, u16 fid)
{
- return mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid & 0xfff);
+ return mv88e6xxx_g1_write(chip, MV88E6352_G1_ATU_FID, fid & 0xfff);
}
/* Offset 0x0A: ATU Control Register */
@@ -27,16 +27,16 @@ int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all)
u16 val;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
if (err)
return err;
if (learn2all)
- val |= GLOBAL_ATU_CONTROL_LEARN2ALL;
+ val |= MV88E6XXX_G1_ATU_CTL_LEARN2ALL;
else
- val &= ~GLOBAL_ATU_CONTROL_LEARN2ALL;
+ val &= ~MV88E6XXX_G1_ATU_CTL_LEARN2ALL;
- return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
+ return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
}
int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
@@ -55,7 +55,7 @@ int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
/* Round to nearest multiple of coeff */
age_time = (msecs + coeff / 2) / coeff;
- err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL, &val);
if (err)
return err;
@@ -63,7 +63,7 @@ int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
val &= ~0xff0;
val |= age_time << 4;
- err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL, val);
if (err)
return err;
@@ -77,7 +77,8 @@ int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
static int mv88e6xxx_g1_atu_op_wait(struct mv88e6xxx_chip *chip)
{
- return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
+ return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_ATU_OP,
+ MV88E6XXX_G1_ATU_OP_BUSY);
}
static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op)
@@ -93,12 +94,14 @@ static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op)
} else {
if (mv88e6xxx_num_databases(chip) > 16) {
/* ATU DBNum[7:4] are located in ATU Control 15:12 */
- err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_CTL,
+ &val);
if (err)
return err;
val = (val & 0x0fff) | ((fid << 8) & 0xf000);
- err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_CTL,
+ val);
if (err)
return err;
}
@@ -107,7 +110,8 @@ static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *chip, u16 fid, u16 op)
op |= fid & 0xf;
}
- err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, op);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_OP,
+ MV88E6XXX_G1_ATU_OP_BUSY | op);
if (err)
return err;
@@ -122,13 +126,13 @@ static int mv88e6xxx_g1_atu_data_read(struct mv88e6xxx_chip *chip,
u16 val;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_DATA, &val);
if (err)
return err;
entry->state = val & 0xf;
- if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
- entry->trunk = !!(val & GLOBAL_ATU_DATA_TRUNK);
+ if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
+ entry->trunk = !!(val & MV88E6XXX_G1_ATU_DATA_TRUNK);
entry->portvec = (val >> 4) & mv88e6xxx_port_mask(chip);
}
@@ -140,14 +144,14 @@ static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx_chip *chip,
{
u16 data = entry->state & 0xf;
- if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
+ if (entry->state != MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
if (entry->trunk)
- data |= GLOBAL_ATU_DATA_TRUNK;
+ data |= MV88E6XXX_G1_ATU_DATA_TRUNK;
data |= (entry->portvec & mv88e6xxx_port_mask(chip)) << 4;
}
- return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
+ return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data);
}
/* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
@@ -162,7 +166,7 @@ static int mv88e6xxx_g1_atu_mac_read(struct mv88e6xxx_chip *chip,
int i, err;
for (i = 0; i < 3; i++) {
- err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_ATU_MAC01 + i, &val);
if (err)
return err;
@@ -181,7 +185,7 @@ static int mv88e6xxx_g1_atu_mac_write(struct mv88e6xxx_chip *chip,
for (i = 0; i < 3; i++) {
val = (entry->mac[i * 2] << 8) | entry->mac[i * 2 + 1];
- err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i, val);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_MAC01 + i, val);
if (err)
return err;
}
@@ -201,13 +205,13 @@ int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
return err;
/* Write the MAC address to iterate from only once */
- if (entry->state == GLOBAL_ATU_DATA_STATE_UNUSED) {
+ if (entry->state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
err = mv88e6xxx_g1_atu_mac_write(chip, entry);
if (err)
return err;
}
- err = mv88e6xxx_g1_atu_op(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
+ err = mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_GET_NEXT_DB);
if (err)
return err;
@@ -235,7 +239,7 @@ int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
if (err)
return err;
- return mv88e6xxx_g1_atu_op(chip, fid, GLOBAL_ATU_OP_LOAD_DB);
+ return mv88e6xxx_g1_atu_op(chip, fid, MV88E6XXX_G1_ATU_OP_LOAD_DB);
}
static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid,
@@ -255,13 +259,13 @@ static int mv88e6xxx_g1_atu_flushmove(struct mv88e6xxx_chip *chip, u16 fid,
/* Flush/Move all or non-static entries from all or a given database */
if (all && fid)
- op = GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB;
+ op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB;
else if (fid)
- op = GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
+ op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
else if (all)
- op = GLOBAL_ATU_OP_FLUSH_MOVE_ALL;
+ op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL;
else
- op = GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
+ op = MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC;
return mv88e6xxx_g1_atu_op(chip, fid, op);
}
--
2.13.1
Prefix and document the Global VTU registers macros and give a clear
16-bit registers representation.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 23 ++++++-----
drivers/net/dsa/mv88e6xxx/chip.h | 4 +-
drivers/net/dsa/mv88e6xxx/global1.h | 69 ++++++++++++++++++++-------------
drivers/net/dsa/mv88e6xxx/global1_vtu.c | 62 +++++++++++++++--------------
4 files changed, 90 insertions(+), 68 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 066fa63c6b6e..f2ce054913e4 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -1047,7 +1047,8 @@ static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
if (!next.valid)
break;
- if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
+ if (next.member[port] ==
+ MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
continue;
/* reinit and dump this VLAN obj */
@@ -1055,7 +1056,8 @@ static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
vlan->vid_end = next.vid;
vlan->flags = 0;
- if (next.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
+ if (next.member[port] ==
+ MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED)
vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
if (next.vid == pvid)
@@ -1143,7 +1145,7 @@ static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
/* Exclude all ports */
for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
entry->member[i] =
- GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
+ MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
return mv88e6xxx_atu_new(chip, &entry->fid);
}
@@ -1185,7 +1187,7 @@ static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
continue;
if (vlan.member[i] ==
- GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
+ MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
continue;
if (ds->ports[i].bridge_dev ==
@@ -1281,11 +1283,11 @@ static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
return;
if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
- member = GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED;
+ member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
else if (untagged)
- member = GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED;
+ member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
else
- member = GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
+ member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
mutex_lock(&chip->reg_lock);
@@ -1312,15 +1314,16 @@ static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
return err;
/* Tell switchdev if this VLAN is handled in software */
- if (vlan.member[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
+ if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
return -EOPNOTSUPP;
- vlan.member[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
+ vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
/* keep the VLAN unless all ports are excluded */
vlan.valid = false;
for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
- if (vlan.member[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
+ if (vlan.member[i] !=
+ MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
vlan.valid = true;
break;
}
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index d70873498501..409452ebc4b9 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -127,12 +127,12 @@ enum mv88e6xxx_cap {
/* Per VLAN Spanning Tree Unit (STU).
* The Port State database, if present, is accessed through VTU
- * operations and dedicated SID registers. See GLOBAL_VTU_SID.
+ * operations and dedicated SID registers. See MV88E6352_G1_VTU_SID.
*/
MV88E6XXX_CAP_STU,
/* VLAN Table Unit.
- * The VTU is used to program 802.1Q VLANs. See GLOBAL_VTU_OP.
+ * The VTU is used to program 802.1Q VLANs. See MV88E6XXX_G1_VTU_OP.
*/
MV88E6XXX_CAP_VTU,
};
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index 126515532d53..56ba709628c7 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -47,10 +47,14 @@
/* Offset 0x01: ATU FID Register */
#define MV88E6352_G1_ATU_FID 0x01
-#define GLOBAL_VTU_FID 0x02
-#define GLOBAL_VTU_FID_MASK 0xfff
-#define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */
-#define GLOBAL_VTU_SID_MASK 0x3f
+/* Offset 0x02: VTU FID Register */
+#define MV88E6352_G1_VTU_FID 0x02
+#define MV88E6352_G1_VTU_FID_MASK 0x0fff
+
+/* Offset 0x03: VTU SID Register */
+#define MV88E6352_G1_VTU_SID 0x03
+#define MV88E6352_G1_VTU_SID_MASK 0x3f
+
#define GLOBAL_CONTROL 0x04
#define GLOBAL_CONTROL_SW_RESET BIT(15)
#define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
@@ -66,29 +70,40 @@
#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
#define GLOBAL_CONTROL_TCAM_EN BIT(1)
#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
-#define GLOBAL_VTU_OP 0x05
-#define GLOBAL_VTU_OP_BUSY BIT(15)
-#define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY)
-#define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY)
-#define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY)
-#define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY)
-#define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY)
-#define GLOBAL_VTU_VID 0x06
-#define GLOBAL_VTU_VID_MASK 0xfff
-#define GLOBAL_VTU_VID_PAGE BIT(13)
-#define GLOBAL_VTU_VID_VALID BIT(12)
-#define GLOBAL_VTU_DATA_0_3 0x07
-#define GLOBAL_VTU_DATA_4_7 0x08
-#define GLOBAL_VTU_DATA_8_11 0x09
-#define GLOBAL_VTU_STU_DATA_MASK 0x03
-#define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00
-#define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01
-#define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02
-#define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03
-#define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00
-#define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01
-#define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02
-#define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03
+
+/* Offset 0x05: VTU Operation Register */
+#define MV88E6XXX_G1_VTU_OP 0x05
+#define MV88E6XXX_G1_VTU_OP_BUSY 0x8000
+#define MV88E6XXX_G1_VTU_OP_MASK 0x7000
+#define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000
+#define MV88E6XXX_G1_VTU_OP_NOOP 0x2000
+#define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000
+#define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000
+#define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000
+#define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000
+
+/* Offset 0x06: VTU VID Register */
+#define MV88E6XXX_G1_VTU_VID 0x06
+#define MV88E6XXX_G1_VTU_VID_MASK 0x0fff
+#define MV88E6390_G1_VTU_VID_PAGE 0x2000
+#define MV88E6XXX_G1_VTU_VID_VALID 0x1000
+
+/* Offset 0x07: VTU/STU Data Register 1
+ * Offset 0x08: VTU/STU Data Register 2
+ * Offset 0x09: VTU/STU Data Register 3
+ */
+#define MV88E6XXX_G1_VTU_DATA1 0x07
+#define MV88E6XXX_G1_VTU_DATA2 0x08
+#define MV88E6XXX_G1_VTU_DATA3 0x09
+#define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003
+#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000
+#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001
+#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002
+#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003
+#define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000
+#define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001
+#define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002
+#define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003
/* Offset 0x0A: ATU Control Register */
#define MV88E6XXX_G1_ATU_CTL 0x0a
diff --git a/drivers/net/dsa/mv88e6xxx/global1_vtu.c b/drivers/net/dsa/mv88e6xxx/global1_vtu.c
index bf593c7aaa9b..8c8a0ec3d6e9 100644
--- a/drivers/net/dsa/mv88e6xxx/global1_vtu.c
+++ b/drivers/net/dsa/mv88e6xxx/global1_vtu.c
@@ -22,11 +22,11 @@ static int mv88e6xxx_g1_vtu_fid_read(struct mv88e6xxx_chip *chip,
u16 val;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6352_G1_VTU_FID, &val);
if (err)
return err;
- entry->fid = val & GLOBAL_VTU_FID_MASK;
+ entry->fid = val & MV88E6352_G1_VTU_FID_MASK;
return 0;
}
@@ -34,9 +34,9 @@ static int mv88e6xxx_g1_vtu_fid_read(struct mv88e6xxx_chip *chip,
static int mv88e6xxx_g1_vtu_fid_write(struct mv88e6xxx_chip *chip,
struct mv88e6xxx_vtu_entry *entry)
{
- u16 val = entry->fid & GLOBAL_VTU_FID_MASK;
+ u16 val = entry->fid & MV88E6352_G1_VTU_FID_MASK;
- return mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, val);
+ return mv88e6xxx_g1_write(chip, MV88E6352_G1_VTU_FID, val);
}
/* Offset 0x03: VTU SID Register */
@@ -47,11 +47,11 @@ static int mv88e6xxx_g1_vtu_sid_read(struct mv88e6xxx_chip *chip,
u16 val;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6352_G1_VTU_SID, &val);
if (err)
return err;
- entry->sid = val & GLOBAL_VTU_SID_MASK;
+ entry->sid = val & MV88E6352_G1_VTU_SID_MASK;
return 0;
}
@@ -59,23 +59,25 @@ static int mv88e6xxx_g1_vtu_sid_read(struct mv88e6xxx_chip *chip,
static int mv88e6xxx_g1_vtu_sid_write(struct mv88e6xxx_chip *chip,
struct mv88e6xxx_vtu_entry *entry)
{
- u16 val = entry->sid & GLOBAL_VTU_SID_MASK;
+ u16 val = entry->sid & MV88E6352_G1_VTU_SID_MASK;
- return mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, val);
+ return mv88e6xxx_g1_write(chip, MV88E6352_G1_VTU_SID, val);
}
/* Offset 0x05: VTU Operation Register */
static int mv88e6xxx_g1_vtu_op_wait(struct mv88e6xxx_chip *chip)
{
- return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
+ return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_VTU_OP,
+ MV88E6XXX_G1_VTU_OP_BUSY);
}
static int mv88e6xxx_g1_vtu_op(struct mv88e6xxx_chip *chip, u16 op)
{
int err;
- err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_OP,
+ MV88E6XXX_G1_VTU_OP_BUSY | op);
if (err)
return err;
@@ -90,16 +92,16 @@ static int mv88e6xxx_g1_vtu_vid_read(struct mv88e6xxx_chip *chip,
u16 val;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_VID, &val);
if (err)
return err;
entry->vid = val & 0xfff;
- if (val & GLOBAL_VTU_VID_PAGE)
+ if (val & MV88E6390_G1_VTU_VID_PAGE)
entry->vid |= 0x1000;
- entry->valid = !!(val & GLOBAL_VTU_VID_VALID);
+ entry->valid = !!(val & MV88E6XXX_G1_VTU_VID_VALID);
return 0;
}
@@ -110,12 +112,12 @@ static int mv88e6xxx_g1_vtu_vid_write(struct mv88e6xxx_chip *chip,
u16 val = entry->vid & 0xfff;
if (entry->vid & 0x1000)
- val |= GLOBAL_VTU_VID_PAGE;
+ val |= MV88E6390_G1_VTU_VID_PAGE;
if (entry->valid)
- val |= GLOBAL_VTU_VID_VALID;
+ val |= MV88E6XXX_G1_VTU_VID_VALID;
- return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, val);
+ return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_VID, val);
}
/* Offset 0x07: VTU/STU Data Register 1
@@ -134,7 +136,7 @@ static int mv88e6185_g1_vtu_data_read(struct mv88e6xxx_chip *chip,
u16 *reg = ®s[i];
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg);
if (err)
return err;
}
@@ -171,7 +173,7 @@ static int mv88e6185_g1_vtu_data_write(struct mv88e6xxx_chip *chip,
u16 reg = regs[i];
int err;
- err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg);
if (err)
return err;
}
@@ -189,7 +191,7 @@ static int mv88e6390_g1_vtu_data_read(struct mv88e6xxx_chip *chip, u8 *data)
u16 *reg = ®s[i];
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg);
if (err)
return err;
}
@@ -221,7 +223,7 @@ static int mv88e6390_g1_vtu_data_write(struct mv88e6xxx_chip *chip, u8 *data)
u16 reg = regs[i];
int err;
- err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_VTU_DATA1 + i, reg);
if (err)
return err;
}
@@ -240,7 +242,7 @@ static int mv88e6xxx_g1_vtu_stu_getnext(struct mv88e6xxx_chip *chip,
if (err)
return err;
- err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
+ err = mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_STU_GET_NEXT);
if (err)
return err;
@@ -295,7 +297,7 @@ static int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
return err;
}
- err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
+ err = mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT);
if (err)
return err;
@@ -320,7 +322,7 @@ int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
/* VTU DBNum[3:0] are located in VTU Operation 3:0
* VTU DBNum[7:4] are located in VTU Operation 11:8
*/
- err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_VTU_OP, &val);
if (err)
return err;
@@ -394,7 +396,7 @@ int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
struct mv88e6xxx_vtu_entry *entry)
{
- u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
+ u16 op = MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE;
int err;
err = mv88e6xxx_g1_vtu_op_wait(chip);
@@ -444,7 +446,8 @@ int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
return err;
/* Load STU entry */
- err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
+ err = mv88e6xxx_g1_vtu_op(chip,
+ MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE);
if (err)
return err;
@@ -454,7 +457,7 @@ int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
}
/* Load/Purge VTU entry */
- return mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
+ return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE);
}
int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
@@ -481,7 +484,8 @@ int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
return err;
/* Load STU entry */
- err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
+ err = mv88e6xxx_g1_vtu_op(chip,
+ MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE);
if (err)
return err;
@@ -496,7 +500,7 @@ int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
}
/* Load/Purge VTU entry */
- return mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
+ return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE);
}
int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip)
@@ -507,5 +511,5 @@ int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip)
if (err)
return err;
- return mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_FLUSH_ALL);
+ return mv88e6xxx_g1_vtu_op(chip, MV88E6XXX_G1_VTU_OP_FLUSH_ALL);
}
--
2.13.1
Prefix and document the Global Switch MAC Address Register macros and
give clear 16-bit register representation.
At the same time, move mv88e6xxx_g1_set_switch_mac in global1.c, where
it belongs.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 19 -------------------
drivers/net/dsa/mv88e6xxx/global1.c | 27 +++++++++++++++++++++++++++
drivers/net/dsa/mv88e6xxx/global1.h | 13 ++++++++++---
3 files changed, 37 insertions(+), 22 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 9cc10dadf17c..b048f851786a 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -1979,25 +1979,6 @@ static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
mutex_unlock(&chip->reg_lock);
}
-static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
-{
- int err;
-
- err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
- if (err)
- return err;
-
- err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
- if (err)
- return err;
-
- err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
- if (err)
- return err;
-
- return 0;
-}
-
static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
unsigned int ageing_time)
{
diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c
index 84559d22bf4e..0ddf1021442b 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.c
+++ b/drivers/net/dsa/mv88e6xxx/global1.c
@@ -125,6 +125,33 @@ static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
return 0;
}
+/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
+ * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
+ * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
+ */
+int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
+{
+ u16 reg;
+ int err;
+
+ reg = (addr[0] << 8) | addr[1];
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
+ if (err)
+ return err;
+
+ reg = (addr[2] << 8) | addr[3];
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
+ if (err)
+ return err;
+
+ reg = (addr[4] << 8) | addr[5];
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
+ if (err)
+ return err;
+
+ return 0;
+}
+
/* Offset 0x04: Switch Global Control Register */
int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index 7ad63a049249..267233d40cb3 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -36,9 +36,14 @@
#define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1
#define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
-#define GLOBAL_MAC_01 0x01
-#define GLOBAL_MAC_23 0x02
-#define GLOBAL_MAC_45 0x03
+/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
+ * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
+ * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
+ */
+#define MV88E6XXX_G1_MAC_01 0x01
+#define MV88E6XXX_G1_MAC_23 0x02
+#define MV88E6XXX_G1_MAC_45 0x03
+
#define GLOBAL_ATU_FID 0x01
#define GLOBAL_VTU_FID 0x02
#define GLOBAL_VTU_FID_MASK 0xfff
@@ -164,6 +169,8 @@ int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
+int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
+
int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
--
2.13.1
Prefix and document the Global Status Register macros and give clear
16-bit register representation.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 4 ++--
drivers/net/dsa/mv88e6xxx/global1.c | 20 ++++++++++----------
drivers/net/dsa/mv88e6xxx/global1.h | 36 +++++++++++++++++++-----------------
drivers/net/dsa/mv88e6xxx/global2.c | 4 ++--
4 files changed, 33 insertions(+), 31 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index fb950ca29081..9cc10dadf17c 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -261,7 +261,7 @@ static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
int err;
mutex_lock(&chip->reg_lock);
- err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
mutex_unlock(&chip->reg_lock);
if (err)
@@ -381,7 +381,7 @@ static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
goto out_disable;
/* Reading the interrupt status clears (most of) them */
- err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
if (err)
goto out_disable;
diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c
index 4081ff0d38a0..84559d22bf4e 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.c
+++ b/drivers/net/dsa/mv88e6xxx/global1.c
@@ -42,13 +42,13 @@ static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
int i, err;
for (i = 0; i < 16; i++) {
- err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &state);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
if (err)
return err;
/* Check the value of the PPUState bits 15:14 */
- state &= GLOBAL_STATUS_PPU_STATE_MASK;
- if (state != GLOBAL_STATUS_PPU_STATE_POLLING)
+ state &= MV88E6185_G1_STS_PPU_STATE_MASK;
+ if (state != MV88E6185_G1_STS_PPU_STATE_POLLING)
return 0;
usleep_range(1000, 2000);
@@ -63,13 +63,13 @@ static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
int i, err;
for (i = 0; i < 16; ++i) {
- err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &state);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
if (err)
return err;
/* Check the value of the PPUState bits 15:14 */
- state &= GLOBAL_STATUS_PPU_STATE_MASK;
- if (state == GLOBAL_STATUS_PPU_STATE_POLLING)
+ state &= MV88E6185_G1_STS_PPU_STATE_MASK;
+ if (state == MV88E6185_G1_STS_PPU_STATE_POLLING)
return 0;
usleep_range(1000, 2000);
@@ -84,12 +84,12 @@ static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
int i, err;
for (i = 0; i < 16; ++i) {
- err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &state);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state);
if (err)
return err;
/* Check the value of the PPUState (or InitState) bit 15 */
- if (state & GLOBAL_STATUS_PPU_STATE)
+ if (state & MV88E6352_G1_STS_PPU_STATE)
return 0;
usleep_range(1000, 2000);
@@ -109,11 +109,11 @@ static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
* have finished their initialization and are ready to accept frames.
*/
while (time_before(jiffies, timeout)) {
- err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
if (err)
return err;
- if (val & GLOBAL_STATUS_INIT_READY)
+ if (val & MV88E6XXX_G1_STS_INIT_READY)
break;
usleep_range(1000, 2000);
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index 3e2765c53f89..7ad63a049249 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -17,23 +17,25 @@
#include "chip.h"
-#define GLOBAL_STATUS 0x00
-#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
-#define GLOBAL_STATUS_PPU_STATE_MASK (0x3 << 14) /* 6165 6185 */
-#define GLOBAL_STATUS_PPU_STATE_DISABLED_RST (0x0 << 14)
-#define GLOBAL_STATUS_PPU_STATE_INITIALIZING (0x1 << 14)
-#define GLOBAL_STATUS_PPU_STATE_DISABLED (0x2 << 14)
-#define GLOBAL_STATUS_PPU_STATE_POLLING (0x3 << 14)
-#define GLOBAL_STATUS_INIT_READY BIT(11)
-#define GLOBAL_STATUS_IRQ_AVB 8
-#define GLOBAL_STATUS_IRQ_DEVICE 7
-#define GLOBAL_STATUS_IRQ_STATS 6
-#define GLOBAL_STATUS_IRQ_VTU_PROBLEM 5
-#define GLOBAL_STATUS_IRQ_VTU_DONE 4
-#define GLOBAL_STATUS_IRQ_ATU_PROBLEM 3
-#define GLOBAL_STATUS_IRQ_ATU_DONE 2
-#define GLOBAL_STATUS_IRQ_TCAM_DONE 1
-#define GLOBAL_STATUS_IRQ_EEPROM_DONE 0
+/* Offset 0x00: Switch Global Status Register */
+#define MV88E6XXX_G1_STS 0x00
+#define MV88E6352_G1_STS_PPU_STATE 0x8000
+#define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
+#define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
+#define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
+#define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
+#define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
+#define MV88E6XXX_G1_STS_INIT_READY 0x0800
+#define MV88E6XXX_G1_STS_IRQ_AVB 8
+#define MV88E6XXX_G1_STS_IRQ_DEVICE 7
+#define MV88E6XXX_G1_STS_IRQ_STATS 6
+#define MV88E6XXX_G1_STS_IRQ_VTU_PROBLEM 5
+#define MV88E6XXX_G1_STS_IRQ_VTU_DONE 4
+#define MV88E6XXX_G1_STS_IRQ_ATU_PROBLEM 3
+#define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2
+#define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1
+#define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
+
#define GLOBAL_MAC_01 0x01
#define GLOBAL_MAC_23 0x02
#define GLOBAL_MAC_45 0x03
diff --git a/drivers/net/dsa/mv88e6xxx/global2.c b/drivers/net/dsa/mv88e6xxx/global2.c
index d63af31e7840..8e8bc4ee464f 100644
--- a/drivers/net/dsa/mv88e6xxx/global2.c
+++ b/drivers/net/dsa/mv88e6xxx/global2.c
@@ -17,7 +17,7 @@
#include <linux/irqdomain.h>
#include "chip.h"
-#include "global1.h" /* for GLOBAL_STATUS_IRQ_DEVICE */
+#include "global1.h" /* for MV88E6XXX_G1_STS_IRQ_DEVICE */
#include "global2.h"
static int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
@@ -977,7 +977,7 @@ int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
chip->g2_irq.masked = ~0;
chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
- GLOBAL_STATUS_IRQ_DEVICE);
+ MV88E6XXX_G1_STS_IRQ_DEVICE);
if (chip->device_irq < 0) {
err = chip->device_irq;
goto out;
--
2.13.1
Prefix and document the Global Control and Control 2 registers macros
and give a clear 16-bit registers representation.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 18 +++++++--------
drivers/net/dsa/mv88e6xxx/global1.c | 32 +++++++++++++-------------
drivers/net/dsa/mv88e6xxx/global1.h | 46 ++++++++++++++++++++-----------------
3 files changed, 50 insertions(+), 46 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index f2ce054913e4..c31ad01c7f96 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -292,14 +292,14 @@ static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
u16 reg;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
if (err)
goto out;
reg &= ~mask;
reg |= (~chip->g1_irq.masked & mask);
- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
if (err)
goto out;
@@ -338,9 +338,9 @@ static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
int irq, virq;
u16 mask;
- mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
+ mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
mask |= GENMASK(chip->g1_irq.nirqs, 0);
- mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
+ mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
free_irq(chip->irq, chip);
@@ -370,13 +370,13 @@ static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
chip->g1_irq.masked = ~0;
- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
if (err)
goto out_mapping;
mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
if (err)
goto out_disable;
@@ -396,7 +396,7 @@ static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
out_disable:
mask |= GENMASK(chip->g1_irq.nirqs, 0);
- mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
+ mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
out_mapping:
for (irq = 0; irq < 16; irq++) {
@@ -2014,8 +2014,8 @@ static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
}
/* Disable remote management, and set the switch's DSA device number. */
- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
- GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2,
+ MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE |
(ds->index & 0x1f));
if (err)
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c
index 0ddf1021442b..63e3ad1ba52a 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.c
+++ b/drivers/net/dsa/mv88e6xxx/global1.c
@@ -162,14 +162,14 @@ int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
/* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
* the PPU, including re-doing PHY detection and initialization
*/
- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
if (err)
return err;
- val |= GLOBAL_CONTROL_SW_RESET;
- val |= GLOBAL_CONTROL_PPU_ENABLE;
+ val |= MV88E6XXX_G1_CTL1_SW_RESET;
+ val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
if (err)
return err;
@@ -186,13 +186,13 @@ int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
int err;
/* Set the SWReset bit 15 */
- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
if (err)
return err;
- val |= GLOBAL_CONTROL_SW_RESET;
+ val |= MV88E6XXX_G1_CTL1_SW_RESET;
- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
if (err)
return err;
@@ -208,13 +208,13 @@ int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
u16 val;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
if (err)
return err;
- val |= GLOBAL_CONTROL_PPU_ENABLE;
+ val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
if (err)
return err;
@@ -226,13 +226,13 @@ int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
u16 val;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
if (err)
return err;
- val &= ~GLOBAL_CONTROL_PPU_ENABLE;
+ val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
if (err)
return err;
@@ -342,13 +342,13 @@ int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
u16 val;
int err;
- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL_2, &val);
+ err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, &val);
if (err)
return err;
- val |= GLOBAL_CONTROL_2_HIST_RX_TX;
+ val |= MV88E6XXX_G1_CTL2_HIST_RX_TX;
- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, val);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, val);
return err;
}
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index 56ba709628c7..af1a510f7a45 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -55,21 +55,22 @@
#define MV88E6352_G1_VTU_SID 0x03
#define MV88E6352_G1_VTU_SID_MASK 0x3f
-#define GLOBAL_CONTROL 0x04
-#define GLOBAL_CONTROL_SW_RESET BIT(15)
-#define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
-#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */
-#define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */
-#define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */
-#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */
-#define GLOBAL_CONTROL_DEVICE_EN BIT(7)
-#define GLOBAL_CONTROL_STATS_DONE_EN BIT(6)
-#define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5)
-#define GLOBAL_CONTROL_VTU_DONE_EN BIT(4)
-#define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3)
-#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
-#define GLOBAL_CONTROL_TCAM_EN BIT(1)
-#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
+/* Offset 0x04: Switch Global Control Register */
+#define MV88E6XXX_G1_CTL1 0x04
+#define MV88E6XXX_G1_CTL1_SW_RESET 0x8000
+#define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000
+#define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000
+#define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800
+#define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400
+#define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200
+#define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080
+#define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040
+#define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020
+#define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010
+#define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008
+#define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004
+#define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002
+#define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001
/* Offset 0x05: VTU Operation Register */
#define MV88E6XXX_G1_VTU_OP 0x05
@@ -172,12 +173,15 @@
#define GLOBAL_MONITOR_CONTROL_INGRESS (0x20 << 8)
#define GLOBAL_MONITOR_CONTROL_EGRESS (0x21 << 8)
#define GLOBAL_MONITOR_CONTROL_CPU_DEST (0x30 << 8)
-#define GLOBAL_CONTROL_2 0x1c
-#define GLOBAL_CONTROL_2_NO_CASCADE 0xe000
-#define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000
-#define GLOBAL_CONTROL_2_HIST_RX (0x1 << 6)
-#define GLOBAL_CONTROL_2_HIST_TX (0x2 << 6)
-#define GLOBAL_CONTROL_2_HIST_RX_TX (0x3 << 6)
+
+/* Offset 0x1C: Global Control 2 */
+#define MV88E6XXX_G1_CTL2 0x1c
+#define MV88E6XXX_G1_CTL2_NO_CASCADE 0xe000
+#define MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE 0xf000
+#define MV88E6XXX_G1_CTL2_HIST_RX 0x0040
+#define MV88E6XXX_G1_CTL2_HIST_TX 0x0080
+#define MV88E6XXX_G1_CTL2_HIST_RX_TX 0x00c0
+
#define GLOBAL_STATS_OP 0x1d
#define GLOBAL_STATS_OP_BUSY BIT(15)
#define GLOBAL_STATS_OP_NOP (0 << 12)
--
2.13.1
Prefix and document the remaining Global IP and IEEE Priority and Core
Tag Type registers and give them a clear 16-bit register representation.
Signed-off-by: Vivien Didelot <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 18 +++++++++---------
drivers/net/dsa/mv88e6xxx/global1.h | 33 +++++++++++++++++++++++----------
2 files changed, 32 insertions(+), 19 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 46e8d1871847..19772e3dd67e 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2022,33 +2022,33 @@ static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
return err;
/* Configure the IP ToS mapping registers. */
- err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
if (err)
return err;
- err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
if (err)
return err;
- err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
if (err)
return err;
- err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
if (err)
return err;
- err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
if (err)
return err;
- err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
if (err)
return err;
- err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
if (err)
return err;
- err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
if (err)
return err;
/* Configure the IEEE 802.1p priority mapping register. */
- err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
+ err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
if (err)
return err;
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
index 16c21bd671c5..950b914f9251 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
@@ -146,16 +146,29 @@
#define MV88E6XXX_G1_ATU_MAC23 0x0e
#define MV88E6XXX_G1_ATU_MAC45 0x0f
-#define GLOBAL_IP_PRI_0 0x10
-#define GLOBAL_IP_PRI_1 0x11
-#define GLOBAL_IP_PRI_2 0x12
-#define GLOBAL_IP_PRI_3 0x13
-#define GLOBAL_IP_PRI_4 0x14
-#define GLOBAL_IP_PRI_5 0x15
-#define GLOBAL_IP_PRI_6 0x16
-#define GLOBAL_IP_PRI_7 0x17
-#define GLOBAL_IEEE_PRI 0x18
-#define GLOBAL_CORE_TAG_TYPE 0x19
+/* Offset 0x10: IP-PRI Mapping Register 0
+ * Offset 0x11: IP-PRI Mapping Register 1
+ * Offset 0x12: IP-PRI Mapping Register 2
+ * Offset 0x13: IP-PRI Mapping Register 3
+ * Offset 0x14: IP-PRI Mapping Register 4
+ * Offset 0x15: IP-PRI Mapping Register 5
+ * Offset 0x16: IP-PRI Mapping Register 6
+ * Offset 0x17: IP-PRI Mapping Register 7
+ */
+#define MV88E6XXX_G1_IP_PRI_0 0x10
+#define MV88E6XXX_G1_IP_PRI_1 0x11
+#define MV88E6XXX_G1_IP_PRI_2 0x12
+#define MV88E6XXX_G1_IP_PRI_3 0x13
+#define MV88E6XXX_G1_IP_PRI_4 0x14
+#define MV88E6XXX_G1_IP_PRI_5 0x15
+#define MV88E6XXX_G1_IP_PRI_6 0x16
+#define MV88E6XXX_G1_IP_PRI_7 0x17
+
+/* Offset 0x18: IEEE-PRI Register */
+#define MV88E6XXX_G1_IEEE_PRI 0x18
+
+/* Offset 0x19: Core Tag Type */
+#define MV88E6185_G1_CORE_TAG_TYPE 0x19
/* Offset 0x1A: Monitor Control */
#define MV88E6185_G1_MONITOR_CTL 0x1a
--
2.13.1
On Thu, Jun 15, 2017 at 12:13:58PM -0400, Vivien Didelot wrote:
> This patch series is the 2/3 step of the register definitions cleanup.
> It brings no functional changes.
>
> It prefixes and documents all Global (1) registers with MV88E6XXX_G1_
> (or a specific model like MV88E6352_G1_STS_PPU_STATE), and prefers a
> 16-bit hexadecimal representation of the Marvell registers layout.
>
> The next and last patchset will prefix the Global 2 registers.
Reviewed-by: Andrew Lunn <[email protected]>
Andrew
From: Andrew Lunn <[email protected]>
Date: Thu, 15 Jun 2017 19:03:11 +0200
> On Thu, Jun 15, 2017 at 12:13:58PM -0400, Vivien Didelot wrote:
>> This patch series is the 2/3 step of the register definitions cleanup.
>> It brings no functional changes.
>>
>> It prefixes and documents all Global (1) registers with MV88E6XXX_G1_
>> (or a specific model like MV88E6352_G1_STS_PPU_STATE), and prefers a
>> 16-bit hexadecimal representation of the Marvell registers layout.
>>
>> The next and last patchset will prefix the Global 2 registers.
>
> Reviewed-by: Andrew Lunn <[email protected]>
Series applied, thanks everyone.