2017-06-20 04:41:31

by Oleksij Rempel

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Subject: [PATCH v6 0/4] nvmem: upstream snvs_lpgpr driver

changes v6:
- check if device is writable by reading GPR_SL and GPR_HL bits
- use regmap_bulk_* functions instead of while() { regmap_read/write }
- add patch for imx6ul

changes v5:
- use dcfg->offset instead of priv->offset.

changes v4:
- change dependencies in Kconfig
- remove unused includes and order them alphabetically
- set MODULE_LICENSE = GPL v2
- remove unused int err variable

changes v3:
- remove regmap and offset properties.

changes v2:
- correct typos: Registe, parrent...

Oleksij Rempel (4):
nvmem: dt: document SNVS LPGPR binding
nvmem: add snvs_lpgpr driver
ARM: dts: imx6qdl.dtsi: add "fsl,imx6q-snvs-lpgpr" node
ARM: imx6ul: add "fsl,imx6ul-snvs-lpgpr" node

.../devicetree/bindings/nvmem/snvs-lpgpr.txt | 20 +++
arch/arm/boot/dts/imx6qdl.dtsi | 4 +
arch/arm/boot/dts/imx6ul.dtsi | 4 +
drivers/nvmem/Kconfig | 10 ++
drivers/nvmem/Makefile | 2 +
drivers/nvmem/snvs_lpgpr.c | 156 +++++++++++++++++++++
6 files changed, 196 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
create mode 100644 drivers/nvmem/snvs_lpgpr.c

--
2.11.0


2017-06-20 04:41:35

by Oleksij Rempel

[permalink] [raw]
Subject: [PATCH v6 1/4] nvmem: dt: document SNVS LPGPR binding

Documentation bindings for the Low Power General Purpose Register
available on i.MX6 SoCs in the Secure Non-Volatile Storage.

Signed-off-by: Oleksij Rempel <[email protected]>
---
.../devicetree/bindings/nvmem/snvs-lpgpr.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt

diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
new file mode 100644
index 000000000000..21910fb3159f
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
@@ -0,0 +1,19 @@
+Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
+Secure Non-Volatile Storage.
+
+This DT node should be represented as a sub-node of a "syscon",
+"simple-mfd" node.
+
+Required properties:
+- compatible: should be:
+ "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
+
+Example:
+snvs: snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x020cc000 0x4000>;
+
+ snvs_lpgpr: snvs-lpgpr {
+ compatible = "fsl,imx6q-snvs-lpgpr";
+ };
+};
--
2.11.0

2017-06-20 04:41:34

by Oleksij Rempel

[permalink] [raw]
Subject: [PATCH v6 2/4] nvmem: add snvs_lpgpr driver

This is a driver for Low Power General Purpose Register (LPGPR)
available on i.MX6 SoCs in Secure Non-Volatile Storage (SNVS)
of this chip.

It is a 32-bit read/write register located in the low power domain.
Since LPGPR is located in the battery-backed power domain, LPGPR can
be used by any application for retaining data during an SoC power-down
mode.

Signed-off-by: Oleksij Rempel <[email protected]>
---
drivers/nvmem/Kconfig | 10 +++
drivers/nvmem/Makefile | 2 +
drivers/nvmem/snvs_lpgpr.c | 155 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 167 insertions(+)
create mode 100644 drivers/nvmem/snvs_lpgpr.c

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 101ced4c84be..ea3044c5d6ee 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -144,4 +144,14 @@ config MESON_EFUSE
This driver can also be built as a module. If so, the module
will be called nvmem_meson_efuse.

+config NVMEM_SNVS_LPGPR
+ tristate "Support for Low Power General Purpose Register"
+ depends on SOC_IMX6 || COMPILE_TEST
+ help
+ This is a driver for Low Power General Purpose Register (LPGPR) available on
+ i.MX6 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called nvmem-snvs-lpgpr.
+
endif
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 173140658693..4c589184acee 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -30,3 +30,5 @@ obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o
nvmem-vf610-ocotp-y := vf610-ocotp.o
obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o
nvmem_meson_efuse-y := meson-efuse.o
+obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o
+nvmem_snvs_lpgpr-y := snvs_lpgpr.o
diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c
new file mode 100644
index 000000000000..eb3369363e44
--- /dev/null
+++ b/drivers/nvmem/snvs_lpgpr.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2015 Pengutronix, Steffen Trumtrar <[email protected]>
+ * Copyright (c) 2017 Pengutronix, Oleksij Rempel <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+#define IMX6Q_SNVS_HPLR 0x00
+#define IMX6Q_GPR_SL BIT(5)
+#define IMX6Q_SNVS_LPLR 0x34
+#define IMX6Q_GPR_HL BIT(5)
+#define IMX6Q_SNVS_LPGPR 0x68
+
+struct snvs_lpgpr_cfg {
+ int offset;
+ int offset_hplr;
+ int offset_lplr;
+};
+
+struct snvs_lpgpr_priv {
+ struct device_d *dev;
+ struct regmap *regmap;
+ struct nvmem_config cfg;
+ const struct snvs_lpgpr_cfg *dcfg;
+};
+
+static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = {
+ .offset = IMX6Q_SNVS_LPGPR,
+ .offset_hplr = IMX6Q_SNVS_HPLR,
+ .offset_lplr = IMX6Q_SNVS_LPLR,
+};
+
+static int snvs_lpgpr_write(void *context, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct snvs_lpgpr_priv *priv = context;
+ const struct snvs_lpgpr_cfg *dcfg = priv->dcfg;
+ unsigned int lock_reg;
+ int ret;
+
+ ret = regmap_read(priv->regmap, dcfg->offset_hplr, &lock_reg);
+ if (ret < 0)
+ return ret;
+
+ if (lock_reg & IMX6Q_GPR_SL)
+ return -EPERM;
+
+ ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg);
+ if (ret < 0)
+ return ret;
+
+ if (lock_reg & IMX6Q_GPR_HL)
+ return -EPERM;
+
+ ret = regmap_bulk_write(priv->regmap, dcfg->offset + offset, val,
+ bytes / 4);
+ return ret;
+}
+
+static int snvs_lpgpr_read(void *context, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct snvs_lpgpr_priv *priv = context;
+ const struct snvs_lpgpr_cfg *dcfg = priv->dcfg;
+
+ return regmap_bulk_read(priv->regmap, dcfg->offset + offset,
+ val, bytes / 4);
+}
+
+static int snvs_lpgpr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ struct device_node *syscon_node;
+ struct snvs_lpgpr_priv *priv;
+ struct nvmem_config *cfg;
+ struct nvmem_device *nvmem;
+ const struct snvs_lpgpr_cfg *dcfg;
+
+ if (!node)
+ return -ENOENT;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ dcfg = of_device_get_match_data(dev);
+ if (!dcfg)
+ return -EINVAL;
+
+ syscon_node = of_get_parent(node);
+ if (!syscon_node)
+ return -ENODEV;
+
+ priv->regmap = syscon_node_to_regmap(syscon_node);
+ of_node_put(syscon_node);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->dcfg = dcfg;
+
+ cfg = &priv->cfg;
+ cfg->priv = priv;
+ cfg->name = dev_name(dev);
+ cfg->dev = dev;
+ cfg->stride = 4,
+ cfg->word_size = 4,
+ cfg->size = 4,
+ cfg->owner = THIS_MODULE,
+ cfg->reg_read = snvs_lpgpr_read,
+ cfg->reg_write = snvs_lpgpr_write,
+
+ nvmem = nvmem_register(cfg);
+ if (IS_ERR(nvmem))
+ return PTR_ERR(nvmem);
+
+ platform_set_drvdata(pdev, nvmem);
+
+ return 0;
+}
+
+static int snvs_lpgpr_remove(struct platform_device *pdev)
+{
+ struct nvmem_device *nvmem = platform_get_drvdata(pdev);
+
+ return nvmem_unregister(nvmem);
+}
+
+static const struct of_device_id snvs_lpgpr_dt_ids[] = {
+ { .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
+ { },
+};
+MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids);
+
+static struct platform_driver snvs_lpgpr_driver = {
+ .probe = snvs_lpgpr_probe,
+ .remove = snvs_lpgpr_remove,
+ .driver = {
+ .name = "snvs_lpgpr",
+ .of_match_table = snvs_lpgpr_dt_ids,
+ },
+};
+module_platform_driver(snvs_lpgpr_driver);
+
+MODULE_AUTHOR("Oleksij Rempel <[email protected]>");
+MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 Secure Non-Volatile Storage");
+MODULE_LICENSE("GPL v2");
--
2.11.0

2017-06-20 04:41:33

by Oleksij Rempel

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Subject: [PATCH v6 4/4] ARM: imx6ul: add "fsl,imx6ul-snvs-lpgpr" node

snvs_lpgpr confirmed to work with imx6ul as well.

Signed-off-by: Oleksij Rempel <[email protected]>
Tested-by: Guy Shapiro <[email protected]>
---
Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt | 3 ++-
arch/arm/boot/dts/imx6ul.dtsi | 4 ++++
drivers/nvmem/snvs_lpgpr.c | 1 +
3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
index 21910fb3159f..d2a811f92d7f 100644
--- a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
+++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
@@ -5,8 +5,9 @@ This DT node should be represented as a sub-node of a "syscon",
"simple-mfd" node.

Required properties:
-- compatible: should be:
+- compatible: should be one of fallowing variants:
"fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
+ "fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL

Example:
snvs: snvs@020cc000 {
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index b9d7d2d09402..df870abc28f5 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -624,6 +624,10 @@
linux,keycode = <KEY_POWER>;
wakeup-source;
};
+
+ snvs_lpgpr: snvs-lpgpr {
+ compatible = "fsl,imx6ul-snvs-lpgpr";
+ };
};

epit1: epit@020d0000 {
diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c
index eb3369363e44..2b20a12918d8 100644
--- a/drivers/nvmem/snvs_lpgpr.c
+++ b/drivers/nvmem/snvs_lpgpr.c
@@ -136,6 +136,7 @@ static int snvs_lpgpr_remove(struct platform_device *pdev)

static const struct of_device_id snvs_lpgpr_dt_ids[] = {
{ .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
+ { .compatible = "fsl,imx6ul-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
{ },
};
MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids);
--
2.11.0

2017-06-20 04:41:32

by Oleksij Rempel

[permalink] [raw]
Subject: [PATCH v6 3/4] ARM: dts: imx6qdl.dtsi: add "fsl,imx6q-snvs-lpgpr" node

This node is for Low Power General Purpose Register which can
be used as Non-Volatile Storage.

Signed-off-by: Oleksij Rempel <[email protected]>
---
arch/arm/boot/dts/imx6qdl.dtsi | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e426faa9c243..94e992558238 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -769,6 +769,10 @@
mask = <0x60>;
status = "disabled";
};
+
+ snvs_lpgpr: snvs-lpgpr {
+ compatible = "fsl,imx6q-snvs-lpgpr";
+ };
};

epit1: epit@020d0000 { /* EPIT1 */
--
2.11.0

2017-06-20 06:34:31

by Stefan Wahren

[permalink] [raw]
Subject: Re: [PATCH v6 4/4] ARM: imx6ul: add "fsl,imx6ul-snvs-lpgpr" node

Am 20.06.2017 um 06:40 schrieb Oleksij Rempel:
> snvs_lpgpr confirmed to work with imx6ul as well.
>
> Signed-off-by: Oleksij Rempel <[email protected]>
> Tested-by: Guy Shapiro <[email protected]>
> ---
> Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt | 3 ++-
> arch/arm/boot/dts/imx6ul.dtsi | 4 ++++
> drivers/nvmem/snvs_lpgpr.c | 1 +
> 3 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> index 21910fb3159f..d2a811f92d7f 100644
> --- a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> @@ -5,8 +5,9 @@ This DT node should be represented as a sub-node of a "syscon",
> "simple-mfd" node.
>
> Required properties:
> -- compatible: should be:
> +- compatible: should be one of fallowing variants:

of the following

> "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
> + "fsl,imx6ul-snvs-lpgpr" for Freescale i.MX6UL

Please fold this change into patch #1. This makes review and merging easier.

>
> Example:
> snvs: snvs@020cc000 {
> diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
> index b9d7d2d09402..df870abc28f5 100644
> --- a/arch/arm/boot/dts/imx6ul.dtsi
> +++ b/arch/arm/boot/dts/imx6ul.dtsi
> @@ -624,6 +624,10 @@
> linux,keycode = <KEY_POWER>;
> wakeup-source;
> };
> +
> + snvs_lpgpr: snvs-lpgpr {
> + compatible = "fsl,imx6ul-snvs-lpgpr";
> + };

AFAIK the imx6ull.dtsi also includes the imx6ul.dtsi. Does this
compatible driver also fit for imx6ull?

If yes, please extend the devicetree binding in patch #1.
If no, this change would have unwanted side effects.

Regards
Stefan

> };
>
> epit1: epit@020d0000 {
> diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c
> index eb3369363e44..2b20a12918d8 100644
> --- a/drivers/nvmem/snvs_lpgpr.c
> +++ b/drivers/nvmem/snvs_lpgpr.c
> @@ -136,6 +136,7 @@ static int snvs_lpgpr_remove(struct platform_device *pdev)
>
> static const struct of_device_id snvs_lpgpr_dt_ids[] = {
> { .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
> + { .compatible = "fsl,imx6ul-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
> { },
> };
> MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids);