> >
> > On Mon, May 29, 2017 at 02:52:39PM +0200, Peter Zijlstra wrote:
> > > On Mon, May 29, 2017 at 02:46:37PM +0200, Jiri Olsa wrote:
> > >
> > > > for some reason I can't get single SMI count generated, is there a
> > > > setup/bench that would provoke that?
> > >
> > > Not having SMIs is a good thing ;-)
> > >
> > > Not sure we can tickle them in a reliable way.
> >
> > yea I saw some counts last time, now just zero so I was wondering if
> > it's working
> >
>
> We have internal test case which can generate SMI, but I cannot publish the
> test case. Sorry about that.
>
APM_CNT (0xB2) could be used to trigger SMI#.
It's documented in PCH datasheet.
https://www.intel.com/content/dam/www/public/us/en/
documents/datasheets/9-series-chipset-pch-datasheet.pdf
APM_CNT-Advanced Power Management Control Port Register
I/O Address: B2h
Attribute: R/W
Default Value: 00h
Size: 8 bits
Lockable: No
Usage: Legacy Only
Power Well: Core
Bit Description
7:0 Used to pass an APM command between the OS and the SMI handler.
Writes to this port not only store data in the APMC register,
but also generates an SMI# when the APMC_EN bit is set.
You can write a byte to port 0xB2 to trigger an SMI#
Thanks,
Kan
Em Fri, Jun 02, 2017 at 03:45:11PM +0000, Liang, Kan escreveu:
> > > On Mon, May 29, 2017 at 02:52:39PM +0200, Peter Zijlstra wrote:
> > > > On Mon, May 29, 2017 at 02:46:37PM +0200, Jiri Olsa wrote:
> > > > > for some reason I can't get single SMI count generated, is there a
> > > > > setup/bench that would provoke that?
> > > > Not having SMIs is a good thing ;-)
> > > > Not sure we can tickle them in a reliable way.
> > > yea I saw some counts last time, now just zero so I was wondering
> > > if it's working
> > We have internal test case which can generate SMI, but I cannot publish the
> > test case. Sorry about that.
> APM_CNT (0xB2) could be used to trigger SMI#.
Here if I run the following 'perf stat' command and press the mute
button (the one sharing F1 in a thinkpad t450s it triggers SMIs, toggle
it in quick sucession and it generates more, etc:
[root@jouet ~]# perf stat -I 1000 -e msr/smi/
# time counts unit events
1.000103173 0 msr/smi/
2.000278816 4 msr/smi/
3.000472630 4 msr/smi/
4.000743916 0 msr/smi/
5.001369358 4 msr/smi/
6.001668033 0 msr/smi/
7.001852603 4 msr/smi/
8.002108269 12 msr/smi/
9.002367312 0 msr/smi/
^C 9.961897866 0 msr/smi/
[root@jouet ~]#
- Arnaldo
> It's documented in PCH datasheet.
> https://www.intel.com/content/dam/www/public/us/en/
> documents/datasheets/9-series-chipset-pch-datasheet.pdf
>
> APM_CNT-Advanced Power Management Control Port Register
> I/O Address: B2h
> Attribute: R/W
> Default Value: 00h
> Size: 8 bits
> Lockable: No
> Usage: Legacy Only
> Power Well: Core
> Bit Description
> 7:0 Used to pass an APM command between the OS and the SMI handler.
> Writes to this port not only store data in the APMC register,
> but also generates an SMI# when the APMC_EN bit is set.
>
> You can write a byte to port 0xB2 to trigger an SMI#
>
> Thanks,
> Kan
Hi Jirka,
Have you got a chance to try the code?
Are you OK with the patch?
Thanks,
Kan
>
> Em Fri, Jun 02, 2017 at 03:45:11PM +0000, Liang, Kan escreveu:
> > > > On Mon, May 29, 2017 at 02:52:39PM +0200, Peter Zijlstra wrote:
> > > > > On Mon, May 29, 2017 at 02:46:37PM +0200, Jiri Olsa wrote:
> > > > > > for some reason I can't get single SMI count generated, is
> > > > > > there a setup/bench that would provoke that?
>
> > > > > Not having SMIs is a good thing ;-) Not sure we can tickle them
> > > > > in a reliable way.
>
> > > > yea I saw some counts last time, now just zero so I was wondering
> > > > if it's working
>
> > > We have internal test case which can generate SMI, but I cannot
> > > publish the test case. Sorry about that.
>
> > APM_CNT (0xB2) could be used to trigger SMI#.
>
> Here if I run the following 'perf stat' command and press the mute button
> (the one sharing F1 in a thinkpad t450s it triggers SMIs, toggle it in quick
> sucession and it generates more, etc:
>
> [root@jouet ~]# perf stat -I 1000 -e msr/smi/
> # time counts unit events
> 1.000103173 0 msr/smi/
> 2.000278816 4 msr/smi/
> 3.000472630 4 msr/smi/
> 4.000743916 0 msr/smi/
> 5.001369358 4 msr/smi/
> 6.001668033 0 msr/smi/
> 7.001852603 4 msr/smi/
> 8.002108269 12 msr/smi/
> 9.002367312 0 msr/smi/
> ^C 9.961897866 0 msr/smi/
>
> [root@jouet ~]#
>
> - Arnaldo
>
> > It's documented in PCH datasheet.
> > https://www.intel.com/content/dam/www/public/us/en/
> > documents/datasheets/9-series-chipset-pch-datasheet.pdf
> >
> > APM_CNT-Advanced Power Management Control Port Register I/O Address:
> > B2h
> > Attribute: R/W
> > Default Value: 00h
> > Size: 8 bits
> > Lockable: No
> > Usage: Legacy Only
> > Power Well: Core
> > Bit Description
> > 7:0 Used to pass an APM command between the OS and the SMI handler.
> > Writes to this port not only store data in the APMC register, but also
> > generates an SMI# when the APMC_EN bit is set.
> >
> > You can write a byte to port 0xB2 to trigger an SMI#
> >
> > Thanks,
> > Kan
Hi Arnaldo and Jirka,
Ping.
Any comments for the patch?
Thanks,
Kan
> Subject: RE: [PATCH V2 0/2] measure SMI cost (user)
>
> Hi Jirka,
>
> Have you got a chance to try the code?
> Are you OK with the patch?
>
> Thanks,
> Kan
>
> >
> > Em Fri, Jun 02, 2017 at 03:45:11PM +0000, Liang, Kan escreveu:
> > > > > On Mon, May 29, 2017 at 02:52:39PM +0200, Peter Zijlstra wrote:
> > > > > > On Mon, May 29, 2017 at 02:46:37PM +0200, Jiri Olsa wrote:
> > > > > > > for some reason I can't get single SMI count generated, is
> > > > > > > there a setup/bench that would provoke that?
> >
> > > > > > Not having SMIs is a good thing ;-) Not sure we can tickle
> > > > > > them in a reliable way.
> >
> > > > > yea I saw some counts last time, now just zero so I was
> > > > > wondering if it's working
> >
> > > > We have internal test case which can generate SMI, but I cannot
> > > > publish the test case. Sorry about that.
> >
> > > APM_CNT (0xB2) could be used to trigger SMI#.
> >
> > Here if I run the following 'perf stat' command and press the mute
> > button (the one sharing F1 in a thinkpad t450s it triggers SMIs,
> > toggle it in quick sucession and it generates more, etc:
> >
> > [root@jouet ~]# perf stat -I 1000 -e msr/smi/
> > # time counts unit events
> > 1.000103173 0 msr/smi/
> > 2.000278816 4 msr/smi/
> > 3.000472630 4 msr/smi/
> > 4.000743916 0 msr/smi/
> > 5.001369358 4 msr/smi/
> > 6.001668033 0 msr/smi/
> > 7.001852603 4 msr/smi/
> > 8.002108269 12 msr/smi/
> > 9.002367312 0 msr/smi/
> > ^C 9.961897866 0 msr/smi/
> >
> > [root@jouet ~]#
> >
> > - Arnaldo
> >
> > > It's documented in PCH datasheet.
> > > https://www.intel.com/content/dam/www/public/us/en/
> > > documents/datasheets/9-series-chipset-pch-datasheet.pdf
> > >
> > > APM_CNT-Advanced Power Management Control Port Register I/O
> Address:
> > > B2h
> > > Attribute: R/W
> > > Default Value: 00h
> > > Size: 8 bits
> > > Lockable: No
> > > Usage: Legacy Only
> > > Power Well: Core
> > > Bit Description
> > > 7:0 Used to pass an APM command between the OS and the SMI handler.
> > > Writes to this port not only store data in the APMC register, but
> > > also generates an SMI# when the APMC_EN bit is set.
> > >
> > > You can write a byte to port 0xB2 to trigger an SMI#
> > >
> > > Thanks,
> > > Kan
Em Tue, Jun 20, 2017 at 01:43:56PM +0000, Liang, Kan escreveu:
> Hi Arnaldo and Jirka,
>
> Ping.
>> Any comments for the patch?
I thought there was a kernel part still outstanding, now I see it was
already merged, will try it and provide comments.
- Arnaldo
> Thanks,
> Kan
>
> > Subject: RE: [PATCH V2 0/2] measure SMI cost (user)
> >
> > Hi Jirka,
> >
> > Have you got a chance to try the code?
> > Are you OK with the patch?
> >
> > Thanks,
> > Kan
> >
> > >
> > > Em Fri, Jun 02, 2017 at 03:45:11PM +0000, Liang, Kan escreveu:
> > > > > > On Mon, May 29, 2017 at 02:52:39PM +0200, Peter Zijlstra wrote:
> > > > > > > On Mon, May 29, 2017 at 02:46:37PM +0200, Jiri Olsa wrote:
> > > > > > > > for some reason I can't get single SMI count generated, is
> > > > > > > > there a setup/bench that would provoke that?
> > >
> > > > > > > Not having SMIs is a good thing ;-) Not sure we can tickle
> > > > > > > them in a reliable way.
> > >
> > > > > > yea I saw some counts last time, now just zero so I was
> > > > > > wondering if it's working
> > >
> > > > > We have internal test case which can generate SMI, but I cannot
> > > > > publish the test case. Sorry about that.
> > >
> > > > APM_CNT (0xB2) could be used to trigger SMI#.
> > >
> > > Here if I run the following 'perf stat' command and press the mute
> > > button (the one sharing F1 in a thinkpad t450s it triggers SMIs,
> > > toggle it in quick sucession and it generates more, etc:
> > >
> > > [root@jouet ~]# perf stat -I 1000 -e msr/smi/
> > > # time counts unit events
> > > 1.000103173 0 msr/smi/
> > > 2.000278816 4 msr/smi/
> > > 3.000472630 4 msr/smi/
> > > 4.000743916 0 msr/smi/
> > > 5.001369358 4 msr/smi/
> > > 6.001668033 0 msr/smi/
> > > 7.001852603 4 msr/smi/
> > > 8.002108269 12 msr/smi/
> > > 9.002367312 0 msr/smi/
> > > ^C 9.961897866 0 msr/smi/
> > >
> > > [root@jouet ~]#
> > >
> > > - Arnaldo
> > >
> > > > It's documented in PCH datasheet.
> > > > https://www.intel.com/content/dam/www/public/us/en/
> > > > documents/datasheets/9-series-chipset-pch-datasheet.pdf
> > > >
> > > > APM_CNT-Advanced Power Management Control Port Register I/O
> > Address:
> > > > B2h
> > > > Attribute: R/W
> > > > Default Value: 00h
> > > > Size: 8 bits
> > > > Lockable: No
> > > > Usage: Legacy Only
> > > > Power Well: Core
> > > > Bit Description
> > > > 7:0 Used to pass an APM command between the OS and the SMI handler.
> > > > Writes to this port not only store data in the APMC register, but
> > > > also generates an SMI# when the APMC_EN bit is set.
> > > >
> > > > You can write a byte to port 0xB2 to trigger an SMI#
> > > >
> > > > Thanks,
> > > > Kan