Userspace shouldn't be able to spam dmesg by passing bad arguments.
This has particularly become an issues since we started using a bad
argument to set_tiling to detect if set_tiling was supported.
Signed-off-by: Eric Anholt <[email protected]>
Fixes: 83753117f1de ("drm/vc4: Add get/set tiling ioctls.")
---
drivers/gpu/drm/vc4/vc4_bo.c | 14 +++---
drivers/gpu/drm/vc4/vc4_gem.c | 10 ++--
drivers/gpu/drm/vc4/vc4_kms.c | 2 +-
drivers/gpu/drm/vc4/vc4_render_cl.c | 40 +++++++--------
drivers/gpu/drm/vc4/vc4_validate.c | 78 +++++++++++++++---------------
drivers/gpu/drm/vc4/vc4_validate_shaders.c | 72 +++++++++++++--------------
6 files changed, 108 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
index 487f96412d35..ede80199001d 100644
--- a/drivers/gpu/drm/vc4/vc4_bo.c
+++ b/drivers/gpu/drm/vc4/vc4_bo.c
@@ -389,7 +389,7 @@ vc4_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags)
struct vc4_bo *bo = to_vc4_bo(obj);
if (bo->validated_shader) {
- DRM_ERROR("Attempting to export shader BO\n");
+ DRM_DEBUG("Attempting to export shader BO\n");
return ERR_PTR(-EINVAL);
}
@@ -410,7 +410,7 @@ int vc4_mmap(struct file *filp, struct vm_area_struct *vma)
bo = to_vc4_bo(gem_obj);
if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
- DRM_ERROR("mmaping of shader BOs for writing not allowed.\n");
+ DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");
return -EINVAL;
}
@@ -435,7 +435,7 @@ int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
struct vc4_bo *bo = to_vc4_bo(obj);
if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
- DRM_ERROR("mmaping of shader BOs for writing not allowed.\n");
+ DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");
return -EINVAL;
}
@@ -447,7 +447,7 @@ void *vc4_prime_vmap(struct drm_gem_object *obj)
struct vc4_bo *bo = to_vc4_bo(obj);
if (bo->validated_shader) {
- DRM_ERROR("mmaping of shader BOs not allowed.\n");
+ DRM_DEBUG("mmaping of shader BOs not allowed.\n");
return ERR_PTR(-EINVAL);
}
@@ -501,7 +501,7 @@ int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
gem_obj = drm_gem_object_lookup(file_priv, args->handle);
if (!gem_obj) {
- DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
+ DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
return -EINVAL;
}
@@ -605,7 +605,7 @@ int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
gem_obj = drm_gem_object_lookup(file_priv, args->handle);
if (!gem_obj) {
- DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
+ DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
return -ENOENT;
}
bo = to_vc4_bo(gem_obj);
@@ -636,7 +636,7 @@ int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
gem_obj = drm_gem_object_lookup(file_priv, args->handle);
if (!gem_obj) {
- DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
+ DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
return -ENOENT;
}
bo = to_vc4_bo(gem_obj);
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
index d5b821ad06af..a3e45e67f417 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -659,7 +659,7 @@ vc4_cl_lookup_bos(struct drm_device *dev,
/* See comment on bo_index for why we have to check
* this.
*/
- DRM_ERROR("Rendering requires BOs to validate\n");
+ DRM_DEBUG("Rendering requires BOs to validate\n");
return -EINVAL;
}
@@ -691,7 +691,7 @@ vc4_cl_lookup_bos(struct drm_device *dev,
struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
handles[i]);
if (!bo) {
- DRM_ERROR("Failed to look up GEM BO %d: %d\n",
+ DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
i, handles[i]);
ret = -EINVAL;
spin_unlock(&file_priv->table_lock);
@@ -729,7 +729,7 @@ vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec)
args->shader_rec_count >= (UINT_MAX /
sizeof(struct vc4_shader_state)) ||
temp_size < exec_size) {
- DRM_ERROR("overflow in exec arguments\n");
+ DRM_DEBUG("overflow in exec arguments\n");
ret = -EINVAL;
goto fail;
}
@@ -974,7 +974,7 @@ vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
gem_obj = drm_gem_object_lookup(file_priv, args->handle);
if (!gem_obj) {
- DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
+ DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
return -EINVAL;
}
bo = to_vc4_bo(gem_obj);
@@ -1009,7 +1009,7 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
int ret = 0;
if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) {
- DRM_ERROR("Unknown flags: 0x%02x\n", args->flags);
+ DRM_DEBUG("Unknown flags: 0x%02x\n", args->flags);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index aeec6e8703d2..9b9aac21dd8c 100644
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -169,7 +169,7 @@ static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
gem_obj = drm_gem_object_lookup(file_priv,
mode_cmd->handles[0]);
if (!gem_obj) {
- DRM_ERROR("Failed to look up GEM BO %d\n",
+ DRM_DEBUG("Failed to look up GEM BO %d\n",
mode_cmd->handles[0]);
return ERR_PTR(-ENOENT);
}
diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c
index 5dc19429d4ae..da3bfd53f0bd 100644
--- a/drivers/gpu/drm/vc4/vc4_render_cl.c
+++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
@@ -378,14 +378,14 @@ static int vc4_full_res_bounds_check(struct vc4_exec_info *exec,
u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32);
if (surf->offset > obj->base.size) {
- DRM_ERROR("surface offset %d > BO size %zd\n",
+ DRM_DEBUG("surface offset %d > BO size %zd\n",
surf->offset, obj->base.size);
return -EINVAL;
}
if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE <
render_tiles_stride * args->max_y_tile + args->max_x_tile) {
- DRM_ERROR("MSAA tile %d, %d out of bounds "
+ DRM_DEBUG("MSAA tile %d, %d out of bounds "
"(bo size %zd, offset %d).\n",
args->max_x_tile, args->max_y_tile,
obj->base.size,
@@ -401,7 +401,7 @@ static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
struct drm_vc4_submit_rcl_surface *surf)
{
if (surf->flags != 0 || surf->bits != 0) {
- DRM_ERROR("MSAA surface had nonzero flags/bits\n");
+ DRM_DEBUG("MSAA surface had nonzero flags/bits\n");
return -EINVAL;
}
@@ -415,7 +415,7 @@ static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
if (surf->offset & 0xf) {
- DRM_ERROR("MSAA write must be 16b aligned.\n");
+ DRM_DEBUG("MSAA write must be 16b aligned.\n");
return -EINVAL;
}
@@ -437,7 +437,7 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
int ret;
if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
- DRM_ERROR("Extra flags set\n");
+ DRM_DEBUG("Extra flags set\n");
return -EINVAL;
}
@@ -453,12 +453,12 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
if (surf == &exec->args->zs_write) {
- DRM_ERROR("general zs write may not be a full-res.\n");
+ DRM_DEBUG("general zs write may not be a full-res.\n");
return -EINVAL;
}
if (surf->bits != 0) {
- DRM_ERROR("load/store general bits set with "
+ DRM_DEBUG("load/store general bits set with "
"full res load/store.\n");
return -EINVAL;
}
@@ -473,19 +473,19 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK |
VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK |
VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) {
- DRM_ERROR("Unknown bits in load/store: 0x%04x\n",
+ DRM_DEBUG("Unknown bits in load/store: 0x%04x\n",
surf->bits);
return -EINVAL;
}
if (tiling > VC4_TILING_FORMAT_LT) {
- DRM_ERROR("Bad tiling format\n");
+ DRM_DEBUG("Bad tiling format\n");
return -EINVAL;
}
if (buffer == VC4_LOADSTORE_TILE_BUFFER_ZS) {
if (format != 0) {
- DRM_ERROR("No color format should be set for ZS\n");
+ DRM_DEBUG("No color format should be set for ZS\n");
return -EINVAL;
}
cpp = 4;
@@ -499,16 +499,16 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
cpp = 4;
break;
default:
- DRM_ERROR("Bad tile buffer format\n");
+ DRM_DEBUG("Bad tile buffer format\n");
return -EINVAL;
}
} else {
- DRM_ERROR("Bad load/store buffer %d.\n", buffer);
+ DRM_DEBUG("Bad load/store buffer %d.\n", buffer);
return -EINVAL;
}
if (surf->offset & 0xf) {
- DRM_ERROR("load/store buffer must be 16b aligned.\n");
+ DRM_DEBUG("load/store buffer must be 16b aligned.\n");
return -EINVAL;
}
@@ -533,7 +533,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
int cpp;
if (surf->flags != 0) {
- DRM_ERROR("No flags supported on render config.\n");
+ DRM_DEBUG("No flags supported on render config.\n");
return -EINVAL;
}
@@ -541,7 +541,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
VC4_RENDER_CONFIG_FORMAT_MASK |
VC4_RENDER_CONFIG_MS_MODE_4X |
VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) {
- DRM_ERROR("Unknown bits in render config: 0x%04x\n",
+ DRM_DEBUG("Unknown bits in render config: 0x%04x\n",
surf->bits);
return -EINVAL;
}
@@ -556,7 +556,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
if (tiling > VC4_TILING_FORMAT_LT) {
- DRM_ERROR("Bad tiling format\n");
+ DRM_DEBUG("Bad tiling format\n");
return -EINVAL;
}
@@ -569,7 +569,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
cpp = 4;
break;
default:
- DRM_ERROR("Bad tile buffer format\n");
+ DRM_DEBUG("Bad tile buffer format\n");
return -EINVAL;
}
@@ -590,7 +590,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
if (args->min_x_tile > args->max_x_tile ||
args->min_y_tile > args->max_y_tile) {
- DRM_ERROR("Bad render tile set (%d,%d)-(%d,%d)\n",
+ DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n",
args->min_x_tile, args->min_y_tile,
args->max_x_tile, args->max_y_tile);
return -EINVAL;
@@ -599,7 +599,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
if (has_bin &&
(args->max_x_tile > exec->bin_tiles_x ||
args->max_y_tile > exec->bin_tiles_y)) {
- DRM_ERROR("Render tiles (%d,%d) outside of bin config "
+ DRM_DEBUG("Render tiles (%d,%d) outside of bin config "
"(%d,%d)\n",
args->max_x_tile, args->max_y_tile,
exec->bin_tiles_x, exec->bin_tiles_y);
@@ -642,7 +642,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
*/
if (!setup.color_write && !setup.zs_write &&
!setup.msaa_color_write && !setup.msaa_zs_write) {
- DRM_ERROR("RCL requires color or Z/S write\n");
+ DRM_DEBUG("RCL requires color or Z/S write\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c
index 814b512c6b9a..2db485abb186 100644
--- a/drivers/gpu/drm/vc4/vc4_validate.c
+++ b/drivers/gpu/drm/vc4/vc4_validate.c
@@ -109,7 +109,7 @@ vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex)
struct vc4_bo *bo;
if (hindex >= exec->bo_count) {
- DRM_ERROR("BO index %d greater than BO count %d\n",
+ DRM_DEBUG("BO index %d greater than BO count %d\n",
hindex, exec->bo_count);
return NULL;
}
@@ -117,7 +117,7 @@ vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex)
bo = to_vc4_bo(&obj->base);
if (bo->validated_shader) {
- DRM_ERROR("Trying to use shader BO as something other than "
+ DRM_DEBUG("Trying to use shader BO as something other than "
"a shader\n");
return NULL;
}
@@ -172,7 +172,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
* our math.
*/
if (width > 4096 || height > 4096) {
- DRM_ERROR("Surface dimensions (%d,%d) too large",
+ DRM_DEBUG("Surface dimensions (%d,%d) too large",
width, height);
return false;
}
@@ -191,7 +191,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
aligned_height = round_up(height, utile_h);
break;
default:
- DRM_ERROR("buffer tiling %d unsupported\n", tiling_format);
+ DRM_DEBUG("buffer tiling %d unsupported\n", tiling_format);
return false;
}
@@ -200,7 +200,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
if (size + offset < size ||
size + offset > fbo->base.size) {
- DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %zd)\n",
+ DRM_DEBUG("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %zd)\n",
width, height,
aligned_width, aligned_height,
size, offset, fbo->base.size);
@@ -214,7 +214,7 @@ static int
validate_flush(VALIDATE_ARGS)
{
if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 1)) {
- DRM_ERROR("Bin CL must end with VC4_PACKET_FLUSH\n");
+ DRM_DEBUG("Bin CL must end with VC4_PACKET_FLUSH\n");
return -EINVAL;
}
exec->found_flush = true;
@@ -226,13 +226,13 @@ static int
validate_start_tile_binning(VALIDATE_ARGS)
{
if (exec->found_start_tile_binning_packet) {
- DRM_ERROR("Duplicate VC4_PACKET_START_TILE_BINNING\n");
+ DRM_DEBUG("Duplicate VC4_PACKET_START_TILE_BINNING\n");
return -EINVAL;
}
exec->found_start_tile_binning_packet = true;
if (!exec->found_tile_binning_mode_config_packet) {
- DRM_ERROR("missing VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
+ DRM_DEBUG("missing VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
return -EINVAL;
}
@@ -243,7 +243,7 @@ static int
validate_increment_semaphore(VALIDATE_ARGS)
{
if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 2)) {
- DRM_ERROR("Bin CL must end with "
+ DRM_DEBUG("Bin CL must end with "
"VC4_PACKET_INCREMENT_SEMAPHORE\n");
return -EINVAL;
}
@@ -264,7 +264,7 @@ validate_indexed_prim_list(VALIDATE_ARGS)
/* Check overflow condition */
if (exec->shader_state_count == 0) {
- DRM_ERROR("shader state must precede primitives\n");
+ DRM_DEBUG("shader state must precede primitives\n");
return -EINVAL;
}
shader_state = &exec->shader_state[exec->shader_state_count - 1];
@@ -281,7 +281,7 @@ validate_indexed_prim_list(VALIDATE_ARGS)
if (offset > ib->base.size ||
(ib->base.size - offset) / index_size < length) {
- DRM_ERROR("IB access overflow (%d + %d*%d > %zd)\n",
+ DRM_DEBUG("IB access overflow (%d + %d*%d > %zd)\n",
offset, length, index_size, ib->base.size);
return -EINVAL;
}
@@ -301,13 +301,13 @@ validate_gl_array_primitive(VALIDATE_ARGS)
/* Check overflow condition */
if (exec->shader_state_count == 0) {
- DRM_ERROR("shader state must precede primitives\n");
+ DRM_DEBUG("shader state must precede primitives\n");
return -EINVAL;
}
shader_state = &exec->shader_state[exec->shader_state_count - 1];
if (length + base_index < length) {
- DRM_ERROR("primitive vertex count overflow\n");
+ DRM_DEBUG("primitive vertex count overflow\n");
return -EINVAL;
}
max_index = length + base_index - 1;
@@ -324,7 +324,7 @@ validate_gl_shader_state(VALIDATE_ARGS)
uint32_t i = exec->shader_state_count++;
if (i >= exec->shader_state_size) {
- DRM_ERROR("More requests for shader states than declared\n");
+ DRM_DEBUG("More requests for shader states than declared\n");
return -EINVAL;
}
@@ -332,7 +332,7 @@ validate_gl_shader_state(VALIDATE_ARGS)
exec->shader_state[i].max_index = 0;
if (exec->shader_state[i].addr & ~0xf) {
- DRM_ERROR("high bits set in GL shader rec reference\n");
+ DRM_DEBUG("high bits set in GL shader rec reference\n");
return -EINVAL;
}
@@ -356,7 +356,7 @@ validate_tile_binning_config(VALIDATE_ARGS)
int bin_slot;
if (exec->found_tile_binning_mode_config_packet) {
- DRM_ERROR("Duplicate VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
+ DRM_DEBUG("Duplicate VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
return -EINVAL;
}
exec->found_tile_binning_mode_config_packet = true;
@@ -368,14 +368,14 @@ validate_tile_binning_config(VALIDATE_ARGS)
if (exec->bin_tiles_x == 0 ||
exec->bin_tiles_y == 0) {
- DRM_ERROR("Tile binning config of %dx%d too small\n",
+ DRM_DEBUG("Tile binning config of %dx%d too small\n",
exec->bin_tiles_x, exec->bin_tiles_y);
return -EINVAL;
}
if (flags & (VC4_BIN_CONFIG_DB_NON_MS |
VC4_BIN_CONFIG_TILE_BUFFER_64BIT)) {
- DRM_ERROR("unsupported binning config flags 0x%02x\n", flags);
+ DRM_DEBUG("unsupported binning config flags 0x%02x\n", flags);
return -EINVAL;
}
@@ -493,20 +493,20 @@ vc4_validate_bin_cl(struct drm_device *dev,
const struct cmd_info *info;
if (cmd >= ARRAY_SIZE(cmd_info)) {
- DRM_ERROR("0x%08x: packet %d out of bounds\n",
+ DRM_DEBUG("0x%08x: packet %d out of bounds\n",
src_offset, cmd);
return -EINVAL;
}
info = &cmd_info[cmd];
if (!info->name) {
- DRM_ERROR("0x%08x: packet %d invalid\n",
+ DRM_DEBUG("0x%08x: packet %d invalid\n",
src_offset, cmd);
return -EINVAL;
}
if (src_offset + info->len > len) {
- DRM_ERROR("0x%08x: packet %d (%s) length 0x%08x "
+ DRM_DEBUG("0x%08x: packet %d (%s) length 0x%08x "
"exceeds bounds (0x%08x)\n",
src_offset, cmd, info->name, info->len,
src_offset + len);
@@ -519,7 +519,7 @@ vc4_validate_bin_cl(struct drm_device *dev,
if (info->func && info->func(exec,
dst_pkt + 1,
src_pkt + 1)) {
- DRM_ERROR("0x%08x: packet %d (%s) failed to validate\n",
+ DRM_DEBUG("0x%08x: packet %d (%s) failed to validate\n",
src_offset, cmd, info->name);
return -EINVAL;
}
@@ -537,7 +537,7 @@ vc4_validate_bin_cl(struct drm_device *dev,
exec->ct0ea = exec->ct0ca + dst_offset;
if (!exec->found_start_tile_binning_packet) {
- DRM_ERROR("Bin CL missing VC4_PACKET_START_TILE_BINNING\n");
+ DRM_DEBUG("Bin CL missing VC4_PACKET_START_TILE_BINNING\n");
return -EINVAL;
}
@@ -549,7 +549,7 @@ vc4_validate_bin_cl(struct drm_device *dev,
* semaphore increment.
*/
if (!exec->found_increment_semaphore_packet || !exec->found_flush) {
- DRM_ERROR("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE + "
+ DRM_DEBUG("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE + "
"VC4_PACKET_FLUSH\n");
return -EINVAL;
}
@@ -588,11 +588,11 @@ reloc_tex(struct vc4_exec_info *exec,
uint32_t remaining_size = tex->base.size - p0;
if (p0 > tex->base.size - 4) {
- DRM_ERROR("UBO offset greater than UBO size\n");
+ DRM_DEBUG("UBO offset greater than UBO size\n");
goto fail;
}
if (p1 > remaining_size - 4) {
- DRM_ERROR("UBO clamp would allow reads "
+ DRM_DEBUG("UBO clamp would allow reads "
"outside of UBO\n");
goto fail;
}
@@ -612,14 +612,14 @@ reloc_tex(struct vc4_exec_info *exec,
if (VC4_GET_FIELD(p3, VC4_TEX_P2_PTYPE) ==
VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE) {
if (cube_map_stride) {
- DRM_ERROR("Cube map stride set twice\n");
+ DRM_DEBUG("Cube map stride set twice\n");
goto fail;
}
cube_map_stride = p3 & VC4_TEX_P2_CMST_MASK;
}
if (!cube_map_stride) {
- DRM_ERROR("Cube map stride not set\n");
+ DRM_DEBUG("Cube map stride not set\n");
goto fail;
}
}
@@ -660,7 +660,7 @@ reloc_tex(struct vc4_exec_info *exec,
case VC4_TEXTURE_TYPE_RGBA64:
case VC4_TEXTURE_TYPE_YUV422R:
default:
- DRM_ERROR("Texture format %d unsupported\n", type);
+ DRM_DEBUG("Texture format %d unsupported\n", type);
goto fail;
}
utile_w = utile_width(cpp);
@@ -713,7 +713,7 @@ reloc_tex(struct vc4_exec_info *exec,
level_size = aligned_width * cpp * aligned_height;
if (offset < level_size) {
- DRM_ERROR("Level %d (%dx%d -> %dx%d) size %db "
+ DRM_DEBUG("Level %d (%dx%d -> %dx%d) size %db "
"overflowed buffer bounds (offset %d)\n",
i, level_width, level_height,
aligned_width, aligned_height,
@@ -764,7 +764,7 @@ validate_gl_shader_rec(struct drm_device *dev,
nr_relocs = ARRAY_SIZE(shader_reloc_offsets) + nr_attributes;
if (nr_relocs * 4 > exec->shader_rec_size) {
- DRM_ERROR("overflowed shader recs reading %d handles "
+ DRM_DEBUG("overflowed shader recs reading %d handles "
"from %d bytes left\n",
nr_relocs, exec->shader_rec_size);
return -EINVAL;
@@ -774,7 +774,7 @@ validate_gl_shader_rec(struct drm_device *dev,
exec->shader_rec_size -= nr_relocs * 4;
if (packet_size > exec->shader_rec_size) {
- DRM_ERROR("overflowed shader recs copying %db packet "
+ DRM_DEBUG("overflowed shader recs copying %db packet "
"from %d bytes left\n",
packet_size, exec->shader_rec_size);
return -EINVAL;
@@ -794,7 +794,7 @@ validate_gl_shader_rec(struct drm_device *dev,
for (i = 0; i < shader_reloc_count; i++) {
if (src_handles[i] > exec->bo_count) {
- DRM_ERROR("Shader handle %d too big\n", src_handles[i]);
+ DRM_DEBUG("Shader handle %d too big\n", src_handles[i]);
return -EINVAL;
}
@@ -810,13 +810,13 @@ validate_gl_shader_rec(struct drm_device *dev,
if (((*(uint16_t *)pkt_u & VC4_SHADER_FLAG_FS_SINGLE_THREAD) == 0) !=
to_vc4_bo(&bo[0]->base)->validated_shader->is_threaded) {
- DRM_ERROR("Thread mode of CL and FS do not match\n");
+ DRM_DEBUG("Thread mode of CL and FS do not match\n");
return -EINVAL;
}
if (to_vc4_bo(&bo[1]->base)->validated_shader->is_threaded ||
to_vc4_bo(&bo[2]->base)->validated_shader->is_threaded) {
- DRM_ERROR("cs and vs cannot be threaded\n");
+ DRM_DEBUG("cs and vs cannot be threaded\n");
return -EINVAL;
}
@@ -831,7 +831,7 @@ validate_gl_shader_rec(struct drm_device *dev,
*(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset;
if (src_offset != 0) {
- DRM_ERROR("Shaders must be at offset 0 of "
+ DRM_DEBUG("Shaders must be at offset 0 of "
"the BO.\n");
return -EINVAL;
}
@@ -842,7 +842,7 @@ validate_gl_shader_rec(struct drm_device *dev,
if (validated_shader->uniforms_src_size >
exec->uniforms_size) {
- DRM_ERROR("Uniforms src buffer overflow\n");
+ DRM_DEBUG("Uniforms src buffer overflow\n");
return -EINVAL;
}
@@ -900,7 +900,7 @@ validate_gl_shader_rec(struct drm_device *dev,
if (vbo->base.size < offset ||
vbo->base.size - offset < attr_size) {
- DRM_ERROR("BO offset overflow (%d + %d > %zu)\n",
+ DRM_DEBUG("BO offset overflow (%d + %d > %zu)\n",
offset, attr_size, vbo->base.size);
return -EINVAL;
}
@@ -909,7 +909,7 @@ validate_gl_shader_rec(struct drm_device *dev,
max_index = ((vbo->base.size - offset - attr_size) /
stride);
if (state->max_index > max_index) {
- DRM_ERROR("primitives use index %d out of "
+ DRM_DEBUG("primitives use index %d out of "
"supplied %d\n",
state->max_index, max_index);
return -EINVAL;
diff --git a/drivers/gpu/drm/vc4/vc4_validate_shaders.c b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
index 0b2df5c6efb4..d3f15bf60900 100644
--- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c
+++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
@@ -200,7 +200,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
uint32_t clamp_reg, clamp_offset;
if (sig == QPU_SIG_SMALL_IMM) {
- DRM_ERROR("direct TMU read used small immediate\n");
+ DRM_DEBUG("direct TMU read used small immediate\n");
return false;
}
@@ -209,7 +209,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
*/
if (is_mul ||
QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
- DRM_ERROR("direct TMU load wasn't an add\n");
+ DRM_DEBUG("direct TMU load wasn't an add\n");
return false;
}
@@ -220,13 +220,13 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
*/
clamp_reg = raddr_add_a_to_live_reg_index(inst);
if (clamp_reg == ~0) {
- DRM_ERROR("direct TMU load wasn't clamped\n");
+ DRM_DEBUG("direct TMU load wasn't clamped\n");
return false;
}
clamp_offset = validation_state->live_min_clamp_offsets[clamp_reg];
if (clamp_offset == ~0) {
- DRM_ERROR("direct TMU load wasn't clamped\n");
+ DRM_DEBUG("direct TMU load wasn't clamped\n");
return false;
}
@@ -238,7 +238,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
!(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
- DRM_ERROR("direct TMU load didn't add to a uniform\n");
+ DRM_DEBUG("direct TMU load didn't add to a uniform\n");
return false;
}
@@ -246,14 +246,14 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
} else {
if (raddr_a == QPU_R_UNIF || (sig != QPU_SIG_SMALL_IMM &&
raddr_b == QPU_R_UNIF)) {
- DRM_ERROR("uniform read in the same instruction as "
+ DRM_DEBUG("uniform read in the same instruction as "
"texture setup.\n");
return false;
}
}
if (validation_state->tmu_write_count[tmu] >= 4) {
- DRM_ERROR("TMU%d got too many parameters before dispatch\n",
+ DRM_DEBUG("TMU%d got too many parameters before dispatch\n",
tmu);
return false;
}
@@ -265,7 +265,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
*/
if (!is_direct) {
if (validation_state->needs_uniform_address_update) {
- DRM_ERROR("Texturing with undefined uniform address\n");
+ DRM_DEBUG("Texturing with undefined uniform address\n");
return false;
}
@@ -336,35 +336,35 @@ validate_uniform_address_write(struct vc4_validated_shader_info *validated_shade
case QPU_SIG_LOAD_TMU1:
break;
default:
- DRM_ERROR("uniforms address change must be "
+ DRM_DEBUG("uniforms address change must be "
"normal math\n");
return false;
}
if (is_mul || QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
- DRM_ERROR("Uniform address reset must be an ADD.\n");
+ DRM_DEBUG("Uniform address reset must be an ADD.\n");
return false;
}
if (QPU_GET_FIELD(inst, QPU_COND_ADD) != QPU_COND_ALWAYS) {
- DRM_ERROR("Uniform address reset must be unconditional.\n");
+ DRM_DEBUG("Uniform address reset must be unconditional.\n");
return false;
}
if (QPU_GET_FIELD(inst, QPU_PACK) != QPU_PACK_A_NOP &&
!(inst & QPU_PM)) {
- DRM_ERROR("No packing allowed on uniforms reset\n");
+ DRM_DEBUG("No packing allowed on uniforms reset\n");
return false;
}
if (add_lri == -1) {
- DRM_ERROR("First argument of uniform address write must be "
+ DRM_DEBUG("First argument of uniform address write must be "
"an immediate value.\n");
return false;
}
if (validation_state->live_immediates[add_lri] != expected_offset) {
- DRM_ERROR("Resetting uniforms with offset %db instead of %db\n",
+ DRM_DEBUG("Resetting uniforms with offset %db instead of %db\n",
validation_state->live_immediates[add_lri],
expected_offset);
return false;
@@ -372,7 +372,7 @@ validate_uniform_address_write(struct vc4_validated_shader_info *validated_shade
if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
!(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
- DRM_ERROR("Second argument of uniform address write must be "
+ DRM_DEBUG("Second argument of uniform address write must be "
"a uniform.\n");
return false;
}
@@ -417,7 +417,7 @@ check_reg_write(struct vc4_validated_shader_info *validated_shader,
switch (waddr) {
case QPU_W_UNIFORMS_ADDRESS:
if (is_b) {
- DRM_ERROR("relative uniforms address change "
+ DRM_DEBUG("relative uniforms address change "
"unsupported\n");
return false;
}
@@ -452,11 +452,11 @@ check_reg_write(struct vc4_validated_shader_info *validated_shader,
/* XXX: I haven't thought about these, so don't support them
* for now.
*/
- DRM_ERROR("Unsupported waddr %d\n", waddr);
+ DRM_DEBUG("Unsupported waddr %d\n", waddr);
return false;
case QPU_W_VPM_ADDR:
- DRM_ERROR("General VPM DMA unsupported\n");
+ DRM_DEBUG("General VPM DMA unsupported\n");
return false;
case QPU_W_VPM:
@@ -559,7 +559,7 @@ check_instruction_writes(struct vc4_validated_shader_info *validated_shader,
bool ok;
if (is_tmu_write(waddr_add) && is_tmu_write(waddr_mul)) {
- DRM_ERROR("ADD and MUL both set up textures\n");
+ DRM_DEBUG("ADD and MUL both set up textures\n");
return false;
}
@@ -588,7 +588,7 @@ check_branch(uint64_t inst,
* there's no need for it.
*/
if (waddr_add != QPU_W_NOP || waddr_mul != QPU_W_NOP) {
- DRM_ERROR("branch instruction at %d wrote a register.\n",
+ DRM_DEBUG("branch instruction at %d wrote a register.\n",
validation_state->ip);
return false;
}
@@ -614,7 +614,7 @@ check_instruction_reads(struct vc4_validated_shader_info *validated_shader,
validated_shader->uniforms_size += 4;
if (validation_state->needs_uniform_address_update) {
- DRM_ERROR("Uniform read with undefined uniform "
+ DRM_DEBUG("Uniform read with undefined uniform "
"address\n");
return false;
}
@@ -660,19 +660,19 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state)
continue;
if (ip - last_branch < 4) {
- DRM_ERROR("Branch at %d during delay slots\n", ip);
+ DRM_DEBUG("Branch at %d during delay slots\n", ip);
return false;
}
last_branch = ip;
if (inst & QPU_BRANCH_REG) {
- DRM_ERROR("branching from register relative "
+ DRM_DEBUG("branching from register relative "
"not supported\n");
return false;
}
if (!(inst & QPU_BRANCH_REL)) {
- DRM_ERROR("relative branching required\n");
+ DRM_DEBUG("relative branching required\n");
return false;
}
@@ -682,13 +682,13 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state)
* end of the shader object.
*/
if (branch_imm % sizeof(inst) != 0) {
- DRM_ERROR("branch target not aligned\n");
+ DRM_DEBUG("branch target not aligned\n");
return false;
}
branch_target_ip = after_delay_ip + (branch_imm >> 3);
if (branch_target_ip >= validation_state->max_ip) {
- DRM_ERROR("Branch at %d outside of shader (ip %d/%d)\n",
+ DRM_DEBUG("Branch at %d outside of shader (ip %d/%d)\n",
ip, branch_target_ip,
validation_state->max_ip);
return false;
@@ -699,7 +699,7 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state)
* the shader.
*/
if (after_delay_ip >= validation_state->max_ip) {
- DRM_ERROR("Branch at %d continues past shader end "
+ DRM_DEBUG("Branch at %d continues past shader end "
"(%d/%d)\n",
ip, after_delay_ip, validation_state->max_ip);
return false;
@@ -709,7 +709,7 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state)
}
if (max_branch_target > validation_state->max_ip - 3) {
- DRM_ERROR("Branch landed after QPU_SIG_PROG_END");
+ DRM_DEBUG("Branch landed after QPU_SIG_PROG_END");
return false;
}
@@ -750,7 +750,7 @@ vc4_handle_branch_target(struct vc4_shader_validation_state *validation_state)
return true;
if (texturing_in_progress(validation_state)) {
- DRM_ERROR("Branch target landed during TMU setup\n");
+ DRM_DEBUG("Branch target landed during TMU setup\n");
return false;
}
@@ -837,7 +837,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
case QPU_SIG_LAST_THREAD_SWITCH:
if (!check_instruction_writes(validated_shader,
&validation_state)) {
- DRM_ERROR("Bad write at ip %d\n", ip);
+ DRM_DEBUG("Bad write at ip %d\n", ip);
goto fail;
}
@@ -855,7 +855,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
validated_shader->is_threaded = true;
if (ip < last_thread_switch_ip + 3) {
- DRM_ERROR("Thread switch too soon after "
+ DRM_DEBUG("Thread switch too soon after "
"last switch at ip %d\n", ip);
goto fail;
}
@@ -867,7 +867,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
case QPU_SIG_LOAD_IMM:
if (!check_instruction_writes(validated_shader,
&validation_state)) {
- DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
+ DRM_DEBUG("Bad LOAD_IMM write at ip %d\n", ip);
goto fail;
}
break;
@@ -878,14 +878,14 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
goto fail;
if (ip < last_thread_switch_ip + 3) {
- DRM_ERROR("Branch in thread switch at ip %d",
+ DRM_DEBUG("Branch in thread switch at ip %d",
ip);
goto fail;
}
break;
default:
- DRM_ERROR("Unsupported QPU signal %d at "
+ DRM_DEBUG("Unsupported QPU signal %d at "
"instruction %d\n", sig, ip);
goto fail;
}
@@ -898,7 +898,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
}
if (ip == validation_state.max_ip) {
- DRM_ERROR("shader failed to terminate before "
+ DRM_DEBUG("shader failed to terminate before "
"shader BO end at %zd\n",
shader_obj->base.size);
goto fail;
@@ -907,7 +907,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
/* Might corrupt other thread */
if (validated_shader->is_threaded &&
validation_state.all_registers_used) {
- DRM_ERROR("Shader uses threading, but uses the upper "
+ DRM_DEBUG("Shader uses threading, but uses the upper "
"half of the registers, too\n");
goto fail;
}
--
2.11.0
This is useful to allow GL to provide defined results for overlapping
glBlitFramebuffer, which X11 in turn uses to accelerate uncomposited
window movement without first blitting to a temporary. x11perf
-copywinwin100 goes from 1850/sec to 4850/sec.
Signed-off-by: Eric Anholt <[email protected]>
---
The work-in-progress userspace is at:
https://github.com/anholt/xserver/commits/glamor-draw-bounds-overlap
https://github.com/anholt/mesa/commits/vc4-overlapping-blit
and the next step is to build the GL extension spec and piglit tests
for it.
drivers/gpu/drm/vc4/vc4_drv.c | 1 +
drivers/gpu/drm/vc4/vc4_gem.c | 5 ++++-
drivers/gpu/drm/vc4/vc4_render_cl.c | 21 ++++++++++++++++-----
include/uapi/drm/vc4_drm.h | 11 +++++++++++
4 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
index c6b487c3d2b7..b5c2c28289ed 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.c
+++ b/drivers/gpu/drm/vc4/vc4_drv.c
@@ -99,6 +99,7 @@ static int vc4_get_param_ioctl(struct drm_device *dev, void *data,
case DRM_VC4_PARAM_SUPPORTS_BRANCHES:
case DRM_VC4_PARAM_SUPPORTS_ETC1:
case DRM_VC4_PARAM_SUPPORTS_THREADED_FS:
+ case DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER:
args->value = true;
break;
default:
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
index a3e45e67f417..ba0782ebda34 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -1008,7 +1008,10 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
struct ww_acquire_ctx acquire_ctx;
int ret = 0;
- if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) {
+ if ((args->flags & ~(VC4_SUBMIT_CL_USE_CLEAR_COLOR |
+ VC4_SUBMIT_CL_FIXED_RCL_ORDER |
+ VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X |
+ VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y)) != 0) {
DRM_DEBUG("Unknown flags: 0x%02x\n", args->flags);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c
index da3bfd53f0bd..c3b064052147 100644
--- a/drivers/gpu/drm/vc4/vc4_render_cl.c
+++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
@@ -261,8 +261,17 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
uint8_t max_y_tile = args->max_y_tile;
uint8_t xtiles = max_x_tile - min_x_tile + 1;
uint8_t ytiles = max_y_tile - min_y_tile + 1;
- uint8_t x, y;
+ uint8_t xi, yi;
uint32_t size, loop_body_size;
+ bool positive_x = false;
+ bool positive_y = false;
+
+ if (args->flags & VC4_SUBMIT_CL_FIXED_RCL_ORDER) {
+ if (args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X)
+ positive_x = true;
+ if (args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y)
+ positive_y = true;
+ }
size = VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE;
loop_body_size = VC4_PACKET_TILE_COORDINATES_SIZE;
@@ -354,10 +363,12 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
rcl_u16(setup, args->height);
rcl_u16(setup, args->color_write.bits);
- for (y = min_y_tile; y <= max_y_tile; y++) {
- for (x = min_x_tile; x <= max_x_tile; x++) {
- bool first = (x == min_x_tile && y == min_y_tile);
- bool last = (x == max_x_tile && y == max_y_tile);
+ for (yi = 0; yi < ytiles; yi++) {
+ int y = positive_y ? min_y_tile + yi : max_y_tile - yi;
+ for (xi = 0; xi < xtiles; xi++) {
+ int x = positive_x ? min_x_tile + xi : max_x_tile - xi;
+ bool first = (xi == 0 && yi == 0);
+ bool last = (xi == xtiles - 1 && yi == ytiles - 1);
emit_tile(exec, setup, x, y, first, last);
}
diff --git a/include/uapi/drm/vc4_drm.h b/include/uapi/drm/vc4_drm.h
index 6ac4c5c014cb..a8bf9a76d5b6 100644
--- a/include/uapi/drm/vc4_drm.h
+++ b/include/uapi/drm/vc4_drm.h
@@ -153,6 +153,16 @@ struct drm_vc4_submit_cl {
__u32 pad:24;
#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
+/* By default, the kernel gets to choose the order that the tiles are
+ * rendered in. If this is set, then the tiles will be rendered in a
+ * raster order, with the right-to-left vs left-to-right and
+ * top-to-bottom vs bottom-to-top dictated by
+ * VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping
+ * blits to be implemented using the 3D engine.
+ */
+#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
+#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
+#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
__u32 flags;
/* Returned value of the seqno of this render job (for the
@@ -292,6 +302,7 @@ struct drm_vc4_get_hang_state {
#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
+#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
struct drm_vc4_get_param {
__u32 param;
--
2.11.0
On Tue, 25 Jul 2017 09:27:32 -0700
Eric Anholt <[email protected]> wrote:
> Userspace shouldn't be able to spam dmesg by passing bad arguments.
> This has particularly become an issues since we started using a bad
> argument to set_tiling to detect if set_tiling was supported.
>
> Signed-off-by: Eric Anholt <[email protected]>
> Fixes: 83753117f1de ("drm/vc4: Add get/set tiling ioctls.")
Reviewed-by: Boris Brezillon <[email protected]>
> ---
> drivers/gpu/drm/vc4/vc4_bo.c | 14 +++---
> drivers/gpu/drm/vc4/vc4_gem.c | 10 ++--
> drivers/gpu/drm/vc4/vc4_kms.c | 2 +-
> drivers/gpu/drm/vc4/vc4_render_cl.c | 40 +++++++--------
> drivers/gpu/drm/vc4/vc4_validate.c | 78 +++++++++++++++---------------
> drivers/gpu/drm/vc4/vc4_validate_shaders.c | 72 +++++++++++++--------------
> 6 files changed, 108 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c
> index 487f96412d35..ede80199001d 100644
> --- a/drivers/gpu/drm/vc4/vc4_bo.c
> +++ b/drivers/gpu/drm/vc4/vc4_bo.c
> @@ -389,7 +389,7 @@ vc4_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags)
> struct vc4_bo *bo = to_vc4_bo(obj);
>
> if (bo->validated_shader) {
> - DRM_ERROR("Attempting to export shader BO\n");
> + DRM_DEBUG("Attempting to export shader BO\n");
> return ERR_PTR(-EINVAL);
> }
>
> @@ -410,7 +410,7 @@ int vc4_mmap(struct file *filp, struct vm_area_struct *vma)
> bo = to_vc4_bo(gem_obj);
>
> if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
> - DRM_ERROR("mmaping of shader BOs for writing not allowed.\n");
> + DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");
> return -EINVAL;
> }
>
> @@ -435,7 +435,7 @@ int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
> struct vc4_bo *bo = to_vc4_bo(obj);
>
> if (bo->validated_shader && (vma->vm_flags & VM_WRITE)) {
> - DRM_ERROR("mmaping of shader BOs for writing not allowed.\n");
> + DRM_DEBUG("mmaping of shader BOs for writing not allowed.\n");
> return -EINVAL;
> }
>
> @@ -447,7 +447,7 @@ void *vc4_prime_vmap(struct drm_gem_object *obj)
> struct vc4_bo *bo = to_vc4_bo(obj);
>
> if (bo->validated_shader) {
> - DRM_ERROR("mmaping of shader BOs not allowed.\n");
> + DRM_DEBUG("mmaping of shader BOs not allowed.\n");
> return ERR_PTR(-EINVAL);
> }
>
> @@ -501,7 +501,7 @@ int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
>
> gem_obj = drm_gem_object_lookup(file_priv, args->handle);
> if (!gem_obj) {
> - DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
> + DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
> return -EINVAL;
> }
>
> @@ -605,7 +605,7 @@ int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
>
> gem_obj = drm_gem_object_lookup(file_priv, args->handle);
> if (!gem_obj) {
> - DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
> + DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
> return -ENOENT;
> }
> bo = to_vc4_bo(gem_obj);
> @@ -636,7 +636,7 @@ int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
>
> gem_obj = drm_gem_object_lookup(file_priv, args->handle);
> if (!gem_obj) {
> - DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
> + DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
> return -ENOENT;
> }
> bo = to_vc4_bo(gem_obj);
> diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
> index d5b821ad06af..a3e45e67f417 100644
> --- a/drivers/gpu/drm/vc4/vc4_gem.c
> +++ b/drivers/gpu/drm/vc4/vc4_gem.c
> @@ -659,7 +659,7 @@ vc4_cl_lookup_bos(struct drm_device *dev,
> /* See comment on bo_index for why we have to check
> * this.
> */
> - DRM_ERROR("Rendering requires BOs to validate\n");
> + DRM_DEBUG("Rendering requires BOs to validate\n");
> return -EINVAL;
> }
>
> @@ -691,7 +691,7 @@ vc4_cl_lookup_bos(struct drm_device *dev,
> struct drm_gem_object *bo = idr_find(&file_priv->object_idr,
> handles[i]);
> if (!bo) {
> - DRM_ERROR("Failed to look up GEM BO %d: %d\n",
> + DRM_DEBUG("Failed to look up GEM BO %d: %d\n",
> i, handles[i]);
> ret = -EINVAL;
> spin_unlock(&file_priv->table_lock);
> @@ -729,7 +729,7 @@ vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info *exec)
> args->shader_rec_count >= (UINT_MAX /
> sizeof(struct vc4_shader_state)) ||
> temp_size < exec_size) {
> - DRM_ERROR("overflow in exec arguments\n");
> + DRM_DEBUG("overflow in exec arguments\n");
> ret = -EINVAL;
> goto fail;
> }
> @@ -974,7 +974,7 @@ vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
>
> gem_obj = drm_gem_object_lookup(file_priv, args->handle);
> if (!gem_obj) {
> - DRM_ERROR("Failed to look up GEM BO %d\n", args->handle);
> + DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
> return -EINVAL;
> }
> bo = to_vc4_bo(gem_obj);
> @@ -1009,7 +1009,7 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
> int ret = 0;
>
> if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) {
> - DRM_ERROR("Unknown flags: 0x%02x\n", args->flags);
> + DRM_DEBUG("Unknown flags: 0x%02x\n", args->flags);
> return -EINVAL;
> }
>
> diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
> index aeec6e8703d2..9b9aac21dd8c 100644
> --- a/drivers/gpu/drm/vc4/vc4_kms.c
> +++ b/drivers/gpu/drm/vc4/vc4_kms.c
> @@ -169,7 +169,7 @@ static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
> gem_obj = drm_gem_object_lookup(file_priv,
> mode_cmd->handles[0]);
> if (!gem_obj) {
> - DRM_ERROR("Failed to look up GEM BO %d\n",
> + DRM_DEBUG("Failed to look up GEM BO %d\n",
> mode_cmd->handles[0]);
> return ERR_PTR(-ENOENT);
> }
> diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c
> index 5dc19429d4ae..da3bfd53f0bd 100644
> --- a/drivers/gpu/drm/vc4/vc4_render_cl.c
> +++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
> @@ -378,14 +378,14 @@ static int vc4_full_res_bounds_check(struct vc4_exec_info *exec,
> u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32);
>
> if (surf->offset > obj->base.size) {
> - DRM_ERROR("surface offset %d > BO size %zd\n",
> + DRM_DEBUG("surface offset %d > BO size %zd\n",
> surf->offset, obj->base.size);
> return -EINVAL;
> }
>
> if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE <
> render_tiles_stride * args->max_y_tile + args->max_x_tile) {
> - DRM_ERROR("MSAA tile %d, %d out of bounds "
> + DRM_DEBUG("MSAA tile %d, %d out of bounds "
> "(bo size %zd, offset %d).\n",
> args->max_x_tile, args->max_y_tile,
> obj->base.size,
> @@ -401,7 +401,7 @@ static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
> struct drm_vc4_submit_rcl_surface *surf)
> {
> if (surf->flags != 0 || surf->bits != 0) {
> - DRM_ERROR("MSAA surface had nonzero flags/bits\n");
> + DRM_DEBUG("MSAA surface had nonzero flags/bits\n");
> return -EINVAL;
> }
>
> @@ -415,7 +415,7 @@ static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
> exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
>
> if (surf->offset & 0xf) {
> - DRM_ERROR("MSAA write must be 16b aligned.\n");
> + DRM_DEBUG("MSAA write must be 16b aligned.\n");
> return -EINVAL;
> }
>
> @@ -437,7 +437,7 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
> int ret;
>
> if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
> - DRM_ERROR("Extra flags set\n");
> + DRM_DEBUG("Extra flags set\n");
> return -EINVAL;
> }
>
> @@ -453,12 +453,12 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
>
> if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
> if (surf == &exec->args->zs_write) {
> - DRM_ERROR("general zs write may not be a full-res.\n");
> + DRM_DEBUG("general zs write may not be a full-res.\n");
> return -EINVAL;
> }
>
> if (surf->bits != 0) {
> - DRM_ERROR("load/store general bits set with "
> + DRM_DEBUG("load/store general bits set with "
> "full res load/store.\n");
> return -EINVAL;
> }
> @@ -473,19 +473,19 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
> if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK |
> VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK |
> VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) {
> - DRM_ERROR("Unknown bits in load/store: 0x%04x\n",
> + DRM_DEBUG("Unknown bits in load/store: 0x%04x\n",
> surf->bits);
> return -EINVAL;
> }
>
> if (tiling > VC4_TILING_FORMAT_LT) {
> - DRM_ERROR("Bad tiling format\n");
> + DRM_DEBUG("Bad tiling format\n");
> return -EINVAL;
> }
>
> if (buffer == VC4_LOADSTORE_TILE_BUFFER_ZS) {
> if (format != 0) {
> - DRM_ERROR("No color format should be set for ZS\n");
> + DRM_DEBUG("No color format should be set for ZS\n");
> return -EINVAL;
> }
> cpp = 4;
> @@ -499,16 +499,16 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
> cpp = 4;
> break;
> default:
> - DRM_ERROR("Bad tile buffer format\n");
> + DRM_DEBUG("Bad tile buffer format\n");
> return -EINVAL;
> }
> } else {
> - DRM_ERROR("Bad load/store buffer %d.\n", buffer);
> + DRM_DEBUG("Bad load/store buffer %d.\n", buffer);
> return -EINVAL;
> }
>
> if (surf->offset & 0xf) {
> - DRM_ERROR("load/store buffer must be 16b aligned.\n");
> + DRM_DEBUG("load/store buffer must be 16b aligned.\n");
> return -EINVAL;
> }
>
> @@ -533,7 +533,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
> int cpp;
>
> if (surf->flags != 0) {
> - DRM_ERROR("No flags supported on render config.\n");
> + DRM_DEBUG("No flags supported on render config.\n");
> return -EINVAL;
> }
>
> @@ -541,7 +541,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
> VC4_RENDER_CONFIG_FORMAT_MASK |
> VC4_RENDER_CONFIG_MS_MODE_4X |
> VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) {
> - DRM_ERROR("Unknown bits in render config: 0x%04x\n",
> + DRM_DEBUG("Unknown bits in render config: 0x%04x\n",
> surf->bits);
> return -EINVAL;
> }
> @@ -556,7 +556,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
> exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
>
> if (tiling > VC4_TILING_FORMAT_LT) {
> - DRM_ERROR("Bad tiling format\n");
> + DRM_DEBUG("Bad tiling format\n");
> return -EINVAL;
> }
>
> @@ -569,7 +569,7 @@ vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
> cpp = 4;
> break;
> default:
> - DRM_ERROR("Bad tile buffer format\n");
> + DRM_DEBUG("Bad tile buffer format\n");
> return -EINVAL;
> }
>
> @@ -590,7 +590,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
>
> if (args->min_x_tile > args->max_x_tile ||
> args->min_y_tile > args->max_y_tile) {
> - DRM_ERROR("Bad render tile set (%d,%d)-(%d,%d)\n",
> + DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n",
> args->min_x_tile, args->min_y_tile,
> args->max_x_tile, args->max_y_tile);
> return -EINVAL;
> @@ -599,7 +599,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
> if (has_bin &&
> (args->max_x_tile > exec->bin_tiles_x ||
> args->max_y_tile > exec->bin_tiles_y)) {
> - DRM_ERROR("Render tiles (%d,%d) outside of bin config "
> + DRM_DEBUG("Render tiles (%d,%d) outside of bin config "
> "(%d,%d)\n",
> args->max_x_tile, args->max_y_tile,
> exec->bin_tiles_x, exec->bin_tiles_y);
> @@ -642,7 +642,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
> */
> if (!setup.color_write && !setup.zs_write &&
> !setup.msaa_color_write && !setup.msaa_zs_write) {
> - DRM_ERROR("RCL requires color or Z/S write\n");
> + DRM_DEBUG("RCL requires color or Z/S write\n");
> return -EINVAL;
> }
>
> diff --git a/drivers/gpu/drm/vc4/vc4_validate.c b/drivers/gpu/drm/vc4/vc4_validate.c
> index 814b512c6b9a..2db485abb186 100644
> --- a/drivers/gpu/drm/vc4/vc4_validate.c
> +++ b/drivers/gpu/drm/vc4/vc4_validate.c
> @@ -109,7 +109,7 @@ vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex)
> struct vc4_bo *bo;
>
> if (hindex >= exec->bo_count) {
> - DRM_ERROR("BO index %d greater than BO count %d\n",
> + DRM_DEBUG("BO index %d greater than BO count %d\n",
> hindex, exec->bo_count);
> return NULL;
> }
> @@ -117,7 +117,7 @@ vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex)
> bo = to_vc4_bo(&obj->base);
>
> if (bo->validated_shader) {
> - DRM_ERROR("Trying to use shader BO as something other than "
> + DRM_DEBUG("Trying to use shader BO as something other than "
> "a shader\n");
> return NULL;
> }
> @@ -172,7 +172,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
> * our math.
> */
> if (width > 4096 || height > 4096) {
> - DRM_ERROR("Surface dimensions (%d,%d) too large",
> + DRM_DEBUG("Surface dimensions (%d,%d) too large",
> width, height);
> return false;
> }
> @@ -191,7 +191,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
> aligned_height = round_up(height, utile_h);
> break;
> default:
> - DRM_ERROR("buffer tiling %d unsupported\n", tiling_format);
> + DRM_DEBUG("buffer tiling %d unsupported\n", tiling_format);
> return false;
> }
>
> @@ -200,7 +200,7 @@ vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
>
> if (size + offset < size ||
> size + offset > fbo->base.size) {
> - DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %zd)\n",
> + DRM_DEBUG("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %zd)\n",
> width, height,
> aligned_width, aligned_height,
> size, offset, fbo->base.size);
> @@ -214,7 +214,7 @@ static int
> validate_flush(VALIDATE_ARGS)
> {
> if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 1)) {
> - DRM_ERROR("Bin CL must end with VC4_PACKET_FLUSH\n");
> + DRM_DEBUG("Bin CL must end with VC4_PACKET_FLUSH\n");
> return -EINVAL;
> }
> exec->found_flush = true;
> @@ -226,13 +226,13 @@ static int
> validate_start_tile_binning(VALIDATE_ARGS)
> {
> if (exec->found_start_tile_binning_packet) {
> - DRM_ERROR("Duplicate VC4_PACKET_START_TILE_BINNING\n");
> + DRM_DEBUG("Duplicate VC4_PACKET_START_TILE_BINNING\n");
> return -EINVAL;
> }
> exec->found_start_tile_binning_packet = true;
>
> if (!exec->found_tile_binning_mode_config_packet) {
> - DRM_ERROR("missing VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
> + DRM_DEBUG("missing VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
> return -EINVAL;
> }
>
> @@ -243,7 +243,7 @@ static int
> validate_increment_semaphore(VALIDATE_ARGS)
> {
> if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 2)) {
> - DRM_ERROR("Bin CL must end with "
> + DRM_DEBUG("Bin CL must end with "
> "VC4_PACKET_INCREMENT_SEMAPHORE\n");
> return -EINVAL;
> }
> @@ -264,7 +264,7 @@ validate_indexed_prim_list(VALIDATE_ARGS)
>
> /* Check overflow condition */
> if (exec->shader_state_count == 0) {
> - DRM_ERROR("shader state must precede primitives\n");
> + DRM_DEBUG("shader state must precede primitives\n");
> return -EINVAL;
> }
> shader_state = &exec->shader_state[exec->shader_state_count - 1];
> @@ -281,7 +281,7 @@ validate_indexed_prim_list(VALIDATE_ARGS)
>
> if (offset > ib->base.size ||
> (ib->base.size - offset) / index_size < length) {
> - DRM_ERROR("IB access overflow (%d + %d*%d > %zd)\n",
> + DRM_DEBUG("IB access overflow (%d + %d*%d > %zd)\n",
> offset, length, index_size, ib->base.size);
> return -EINVAL;
> }
> @@ -301,13 +301,13 @@ validate_gl_array_primitive(VALIDATE_ARGS)
>
> /* Check overflow condition */
> if (exec->shader_state_count == 0) {
> - DRM_ERROR("shader state must precede primitives\n");
> + DRM_DEBUG("shader state must precede primitives\n");
> return -EINVAL;
> }
> shader_state = &exec->shader_state[exec->shader_state_count - 1];
>
> if (length + base_index < length) {
> - DRM_ERROR("primitive vertex count overflow\n");
> + DRM_DEBUG("primitive vertex count overflow\n");
> return -EINVAL;
> }
> max_index = length + base_index - 1;
> @@ -324,7 +324,7 @@ validate_gl_shader_state(VALIDATE_ARGS)
> uint32_t i = exec->shader_state_count++;
>
> if (i >= exec->shader_state_size) {
> - DRM_ERROR("More requests for shader states than declared\n");
> + DRM_DEBUG("More requests for shader states than declared\n");
> return -EINVAL;
> }
>
> @@ -332,7 +332,7 @@ validate_gl_shader_state(VALIDATE_ARGS)
> exec->shader_state[i].max_index = 0;
>
> if (exec->shader_state[i].addr & ~0xf) {
> - DRM_ERROR("high bits set in GL shader rec reference\n");
> + DRM_DEBUG("high bits set in GL shader rec reference\n");
> return -EINVAL;
> }
>
> @@ -356,7 +356,7 @@ validate_tile_binning_config(VALIDATE_ARGS)
> int bin_slot;
>
> if (exec->found_tile_binning_mode_config_packet) {
> - DRM_ERROR("Duplicate VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
> + DRM_DEBUG("Duplicate VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
> return -EINVAL;
> }
> exec->found_tile_binning_mode_config_packet = true;
> @@ -368,14 +368,14 @@ validate_tile_binning_config(VALIDATE_ARGS)
>
> if (exec->bin_tiles_x == 0 ||
> exec->bin_tiles_y == 0) {
> - DRM_ERROR("Tile binning config of %dx%d too small\n",
> + DRM_DEBUG("Tile binning config of %dx%d too small\n",
> exec->bin_tiles_x, exec->bin_tiles_y);
> return -EINVAL;
> }
>
> if (flags & (VC4_BIN_CONFIG_DB_NON_MS |
> VC4_BIN_CONFIG_TILE_BUFFER_64BIT)) {
> - DRM_ERROR("unsupported binning config flags 0x%02x\n", flags);
> + DRM_DEBUG("unsupported binning config flags 0x%02x\n", flags);
> return -EINVAL;
> }
>
> @@ -493,20 +493,20 @@ vc4_validate_bin_cl(struct drm_device *dev,
> const struct cmd_info *info;
>
> if (cmd >= ARRAY_SIZE(cmd_info)) {
> - DRM_ERROR("0x%08x: packet %d out of bounds\n",
> + DRM_DEBUG("0x%08x: packet %d out of bounds\n",
> src_offset, cmd);
> return -EINVAL;
> }
>
> info = &cmd_info[cmd];
> if (!info->name) {
> - DRM_ERROR("0x%08x: packet %d invalid\n",
> + DRM_DEBUG("0x%08x: packet %d invalid\n",
> src_offset, cmd);
> return -EINVAL;
> }
>
> if (src_offset + info->len > len) {
> - DRM_ERROR("0x%08x: packet %d (%s) length 0x%08x "
> + DRM_DEBUG("0x%08x: packet %d (%s) length 0x%08x "
> "exceeds bounds (0x%08x)\n",
> src_offset, cmd, info->name, info->len,
> src_offset + len);
> @@ -519,7 +519,7 @@ vc4_validate_bin_cl(struct drm_device *dev,
> if (info->func && info->func(exec,
> dst_pkt + 1,
> src_pkt + 1)) {
> - DRM_ERROR("0x%08x: packet %d (%s) failed to validate\n",
> + DRM_DEBUG("0x%08x: packet %d (%s) failed to validate\n",
> src_offset, cmd, info->name);
> return -EINVAL;
> }
> @@ -537,7 +537,7 @@ vc4_validate_bin_cl(struct drm_device *dev,
> exec->ct0ea = exec->ct0ca + dst_offset;
>
> if (!exec->found_start_tile_binning_packet) {
> - DRM_ERROR("Bin CL missing VC4_PACKET_START_TILE_BINNING\n");
> + DRM_DEBUG("Bin CL missing VC4_PACKET_START_TILE_BINNING\n");
> return -EINVAL;
> }
>
> @@ -549,7 +549,7 @@ vc4_validate_bin_cl(struct drm_device *dev,
> * semaphore increment.
> */
> if (!exec->found_increment_semaphore_packet || !exec->found_flush) {
> - DRM_ERROR("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE + "
> + DRM_DEBUG("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE + "
> "VC4_PACKET_FLUSH\n");
> return -EINVAL;
> }
> @@ -588,11 +588,11 @@ reloc_tex(struct vc4_exec_info *exec,
> uint32_t remaining_size = tex->base.size - p0;
>
> if (p0 > tex->base.size - 4) {
> - DRM_ERROR("UBO offset greater than UBO size\n");
> + DRM_DEBUG("UBO offset greater than UBO size\n");
> goto fail;
> }
> if (p1 > remaining_size - 4) {
> - DRM_ERROR("UBO clamp would allow reads "
> + DRM_DEBUG("UBO clamp would allow reads "
> "outside of UBO\n");
> goto fail;
> }
> @@ -612,14 +612,14 @@ reloc_tex(struct vc4_exec_info *exec,
> if (VC4_GET_FIELD(p3, VC4_TEX_P2_PTYPE) ==
> VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE) {
> if (cube_map_stride) {
> - DRM_ERROR("Cube map stride set twice\n");
> + DRM_DEBUG("Cube map stride set twice\n");
> goto fail;
> }
>
> cube_map_stride = p3 & VC4_TEX_P2_CMST_MASK;
> }
> if (!cube_map_stride) {
> - DRM_ERROR("Cube map stride not set\n");
> + DRM_DEBUG("Cube map stride not set\n");
> goto fail;
> }
> }
> @@ -660,7 +660,7 @@ reloc_tex(struct vc4_exec_info *exec,
> case VC4_TEXTURE_TYPE_RGBA64:
> case VC4_TEXTURE_TYPE_YUV422R:
> default:
> - DRM_ERROR("Texture format %d unsupported\n", type);
> + DRM_DEBUG("Texture format %d unsupported\n", type);
> goto fail;
> }
> utile_w = utile_width(cpp);
> @@ -713,7 +713,7 @@ reloc_tex(struct vc4_exec_info *exec,
> level_size = aligned_width * cpp * aligned_height;
>
> if (offset < level_size) {
> - DRM_ERROR("Level %d (%dx%d -> %dx%d) size %db "
> + DRM_DEBUG("Level %d (%dx%d -> %dx%d) size %db "
> "overflowed buffer bounds (offset %d)\n",
> i, level_width, level_height,
> aligned_width, aligned_height,
> @@ -764,7 +764,7 @@ validate_gl_shader_rec(struct drm_device *dev,
>
> nr_relocs = ARRAY_SIZE(shader_reloc_offsets) + nr_attributes;
> if (nr_relocs * 4 > exec->shader_rec_size) {
> - DRM_ERROR("overflowed shader recs reading %d handles "
> + DRM_DEBUG("overflowed shader recs reading %d handles "
> "from %d bytes left\n",
> nr_relocs, exec->shader_rec_size);
> return -EINVAL;
> @@ -774,7 +774,7 @@ validate_gl_shader_rec(struct drm_device *dev,
> exec->shader_rec_size -= nr_relocs * 4;
>
> if (packet_size > exec->shader_rec_size) {
> - DRM_ERROR("overflowed shader recs copying %db packet "
> + DRM_DEBUG("overflowed shader recs copying %db packet "
> "from %d bytes left\n",
> packet_size, exec->shader_rec_size);
> return -EINVAL;
> @@ -794,7 +794,7 @@ validate_gl_shader_rec(struct drm_device *dev,
>
> for (i = 0; i < shader_reloc_count; i++) {
> if (src_handles[i] > exec->bo_count) {
> - DRM_ERROR("Shader handle %d too big\n", src_handles[i]);
> + DRM_DEBUG("Shader handle %d too big\n", src_handles[i]);
> return -EINVAL;
> }
>
> @@ -810,13 +810,13 @@ validate_gl_shader_rec(struct drm_device *dev,
>
> if (((*(uint16_t *)pkt_u & VC4_SHADER_FLAG_FS_SINGLE_THREAD) == 0) !=
> to_vc4_bo(&bo[0]->base)->validated_shader->is_threaded) {
> - DRM_ERROR("Thread mode of CL and FS do not match\n");
> + DRM_DEBUG("Thread mode of CL and FS do not match\n");
> return -EINVAL;
> }
>
> if (to_vc4_bo(&bo[1]->base)->validated_shader->is_threaded ||
> to_vc4_bo(&bo[2]->base)->validated_shader->is_threaded) {
> - DRM_ERROR("cs and vs cannot be threaded\n");
> + DRM_DEBUG("cs and vs cannot be threaded\n");
> return -EINVAL;
> }
>
> @@ -831,7 +831,7 @@ validate_gl_shader_rec(struct drm_device *dev,
> *(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset;
>
> if (src_offset != 0) {
> - DRM_ERROR("Shaders must be at offset 0 of "
> + DRM_DEBUG("Shaders must be at offset 0 of "
> "the BO.\n");
> return -EINVAL;
> }
> @@ -842,7 +842,7 @@ validate_gl_shader_rec(struct drm_device *dev,
>
> if (validated_shader->uniforms_src_size >
> exec->uniforms_size) {
> - DRM_ERROR("Uniforms src buffer overflow\n");
> + DRM_DEBUG("Uniforms src buffer overflow\n");
> return -EINVAL;
> }
>
> @@ -900,7 +900,7 @@ validate_gl_shader_rec(struct drm_device *dev,
>
> if (vbo->base.size < offset ||
> vbo->base.size - offset < attr_size) {
> - DRM_ERROR("BO offset overflow (%d + %d > %zu)\n",
> + DRM_DEBUG("BO offset overflow (%d + %d > %zu)\n",
> offset, attr_size, vbo->base.size);
> return -EINVAL;
> }
> @@ -909,7 +909,7 @@ validate_gl_shader_rec(struct drm_device *dev,
> max_index = ((vbo->base.size - offset - attr_size) /
> stride);
> if (state->max_index > max_index) {
> - DRM_ERROR("primitives use index %d out of "
> + DRM_DEBUG("primitives use index %d out of "
> "supplied %d\n",
> state->max_index, max_index);
> return -EINVAL;
> diff --git a/drivers/gpu/drm/vc4/vc4_validate_shaders.c b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
> index 0b2df5c6efb4..d3f15bf60900 100644
> --- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c
> +++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
> @@ -200,7 +200,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
> uint32_t clamp_reg, clamp_offset;
>
> if (sig == QPU_SIG_SMALL_IMM) {
> - DRM_ERROR("direct TMU read used small immediate\n");
> + DRM_DEBUG("direct TMU read used small immediate\n");
> return false;
> }
>
> @@ -209,7 +209,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
> */
> if (is_mul ||
> QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
> - DRM_ERROR("direct TMU load wasn't an add\n");
> + DRM_DEBUG("direct TMU load wasn't an add\n");
> return false;
> }
>
> @@ -220,13 +220,13 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
> */
> clamp_reg = raddr_add_a_to_live_reg_index(inst);
> if (clamp_reg == ~0) {
> - DRM_ERROR("direct TMU load wasn't clamped\n");
> + DRM_DEBUG("direct TMU load wasn't clamped\n");
> return false;
> }
>
> clamp_offset = validation_state->live_min_clamp_offsets[clamp_reg];
> if (clamp_offset == ~0) {
> - DRM_ERROR("direct TMU load wasn't clamped\n");
> + DRM_DEBUG("direct TMU load wasn't clamped\n");
> return false;
> }
>
> @@ -238,7 +238,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
>
> if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
> !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
> - DRM_ERROR("direct TMU load didn't add to a uniform\n");
> + DRM_DEBUG("direct TMU load didn't add to a uniform\n");
> return false;
> }
>
> @@ -246,14 +246,14 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
> } else {
> if (raddr_a == QPU_R_UNIF || (sig != QPU_SIG_SMALL_IMM &&
> raddr_b == QPU_R_UNIF)) {
> - DRM_ERROR("uniform read in the same instruction as "
> + DRM_DEBUG("uniform read in the same instruction as "
> "texture setup.\n");
> return false;
> }
> }
>
> if (validation_state->tmu_write_count[tmu] >= 4) {
> - DRM_ERROR("TMU%d got too many parameters before dispatch\n",
> + DRM_DEBUG("TMU%d got too many parameters before dispatch\n",
> tmu);
> return false;
> }
> @@ -265,7 +265,7 @@ check_tmu_write(struct vc4_validated_shader_info *validated_shader,
> */
> if (!is_direct) {
> if (validation_state->needs_uniform_address_update) {
> - DRM_ERROR("Texturing with undefined uniform address\n");
> + DRM_DEBUG("Texturing with undefined uniform address\n");
> return false;
> }
>
> @@ -336,35 +336,35 @@ validate_uniform_address_write(struct vc4_validated_shader_info *validated_shade
> case QPU_SIG_LOAD_TMU1:
> break;
> default:
> - DRM_ERROR("uniforms address change must be "
> + DRM_DEBUG("uniforms address change must be "
> "normal math\n");
> return false;
> }
>
> if (is_mul || QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
> - DRM_ERROR("Uniform address reset must be an ADD.\n");
> + DRM_DEBUG("Uniform address reset must be an ADD.\n");
> return false;
> }
>
> if (QPU_GET_FIELD(inst, QPU_COND_ADD) != QPU_COND_ALWAYS) {
> - DRM_ERROR("Uniform address reset must be unconditional.\n");
> + DRM_DEBUG("Uniform address reset must be unconditional.\n");
> return false;
> }
>
> if (QPU_GET_FIELD(inst, QPU_PACK) != QPU_PACK_A_NOP &&
> !(inst & QPU_PM)) {
> - DRM_ERROR("No packing allowed on uniforms reset\n");
> + DRM_DEBUG("No packing allowed on uniforms reset\n");
> return false;
> }
>
> if (add_lri == -1) {
> - DRM_ERROR("First argument of uniform address write must be "
> + DRM_DEBUG("First argument of uniform address write must be "
> "an immediate value.\n");
> return false;
> }
>
> if (validation_state->live_immediates[add_lri] != expected_offset) {
> - DRM_ERROR("Resetting uniforms with offset %db instead of %db\n",
> + DRM_DEBUG("Resetting uniforms with offset %db instead of %db\n",
> validation_state->live_immediates[add_lri],
> expected_offset);
> return false;
> @@ -372,7 +372,7 @@ validate_uniform_address_write(struct vc4_validated_shader_info *validated_shade
>
> if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
> !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
> - DRM_ERROR("Second argument of uniform address write must be "
> + DRM_DEBUG("Second argument of uniform address write must be "
> "a uniform.\n");
> return false;
> }
> @@ -417,7 +417,7 @@ check_reg_write(struct vc4_validated_shader_info *validated_shader,
> switch (waddr) {
> case QPU_W_UNIFORMS_ADDRESS:
> if (is_b) {
> - DRM_ERROR("relative uniforms address change "
> + DRM_DEBUG("relative uniforms address change "
> "unsupported\n");
> return false;
> }
> @@ -452,11 +452,11 @@ check_reg_write(struct vc4_validated_shader_info *validated_shader,
> /* XXX: I haven't thought about these, so don't support them
> * for now.
> */
> - DRM_ERROR("Unsupported waddr %d\n", waddr);
> + DRM_DEBUG("Unsupported waddr %d\n", waddr);
> return false;
>
> case QPU_W_VPM_ADDR:
> - DRM_ERROR("General VPM DMA unsupported\n");
> + DRM_DEBUG("General VPM DMA unsupported\n");
> return false;
>
> case QPU_W_VPM:
> @@ -559,7 +559,7 @@ check_instruction_writes(struct vc4_validated_shader_info *validated_shader,
> bool ok;
>
> if (is_tmu_write(waddr_add) && is_tmu_write(waddr_mul)) {
> - DRM_ERROR("ADD and MUL both set up textures\n");
> + DRM_DEBUG("ADD and MUL both set up textures\n");
> return false;
> }
>
> @@ -588,7 +588,7 @@ check_branch(uint64_t inst,
> * there's no need for it.
> */
> if (waddr_add != QPU_W_NOP || waddr_mul != QPU_W_NOP) {
> - DRM_ERROR("branch instruction at %d wrote a register.\n",
> + DRM_DEBUG("branch instruction at %d wrote a register.\n",
> validation_state->ip);
> return false;
> }
> @@ -614,7 +614,7 @@ check_instruction_reads(struct vc4_validated_shader_info *validated_shader,
> validated_shader->uniforms_size += 4;
>
> if (validation_state->needs_uniform_address_update) {
> - DRM_ERROR("Uniform read with undefined uniform "
> + DRM_DEBUG("Uniform read with undefined uniform "
> "address\n");
> return false;
> }
> @@ -660,19 +660,19 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state)
> continue;
>
> if (ip - last_branch < 4) {
> - DRM_ERROR("Branch at %d during delay slots\n", ip);
> + DRM_DEBUG("Branch at %d during delay slots\n", ip);
> return false;
> }
> last_branch = ip;
>
> if (inst & QPU_BRANCH_REG) {
> - DRM_ERROR("branching from register relative "
> + DRM_DEBUG("branching from register relative "
> "not supported\n");
> return false;
> }
>
> if (!(inst & QPU_BRANCH_REL)) {
> - DRM_ERROR("relative branching required\n");
> + DRM_DEBUG("relative branching required\n");
> return false;
> }
>
> @@ -682,13 +682,13 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state)
> * end of the shader object.
> */
> if (branch_imm % sizeof(inst) != 0) {
> - DRM_ERROR("branch target not aligned\n");
> + DRM_DEBUG("branch target not aligned\n");
> return false;
> }
>
> branch_target_ip = after_delay_ip + (branch_imm >> 3);
> if (branch_target_ip >= validation_state->max_ip) {
> - DRM_ERROR("Branch at %d outside of shader (ip %d/%d)\n",
> + DRM_DEBUG("Branch at %d outside of shader (ip %d/%d)\n",
> ip, branch_target_ip,
> validation_state->max_ip);
> return false;
> @@ -699,7 +699,7 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state)
> * the shader.
> */
> if (after_delay_ip >= validation_state->max_ip) {
> - DRM_ERROR("Branch at %d continues past shader end "
> + DRM_DEBUG("Branch at %d continues past shader end "
> "(%d/%d)\n",
> ip, after_delay_ip, validation_state->max_ip);
> return false;
> @@ -709,7 +709,7 @@ vc4_validate_branches(struct vc4_shader_validation_state *validation_state)
> }
>
> if (max_branch_target > validation_state->max_ip - 3) {
> - DRM_ERROR("Branch landed after QPU_SIG_PROG_END");
> + DRM_DEBUG("Branch landed after QPU_SIG_PROG_END");
> return false;
> }
>
> @@ -750,7 +750,7 @@ vc4_handle_branch_target(struct vc4_shader_validation_state *validation_state)
> return true;
>
> if (texturing_in_progress(validation_state)) {
> - DRM_ERROR("Branch target landed during TMU setup\n");
> + DRM_DEBUG("Branch target landed during TMU setup\n");
> return false;
> }
>
> @@ -837,7 +837,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
> case QPU_SIG_LAST_THREAD_SWITCH:
> if (!check_instruction_writes(validated_shader,
> &validation_state)) {
> - DRM_ERROR("Bad write at ip %d\n", ip);
> + DRM_DEBUG("Bad write at ip %d\n", ip);
> goto fail;
> }
>
> @@ -855,7 +855,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
> validated_shader->is_threaded = true;
>
> if (ip < last_thread_switch_ip + 3) {
> - DRM_ERROR("Thread switch too soon after "
> + DRM_DEBUG("Thread switch too soon after "
> "last switch at ip %d\n", ip);
> goto fail;
> }
> @@ -867,7 +867,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
> case QPU_SIG_LOAD_IMM:
> if (!check_instruction_writes(validated_shader,
> &validation_state)) {
> - DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
> + DRM_DEBUG("Bad LOAD_IMM write at ip %d\n", ip);
> goto fail;
> }
> break;
> @@ -878,14 +878,14 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
> goto fail;
>
> if (ip < last_thread_switch_ip + 3) {
> - DRM_ERROR("Branch in thread switch at ip %d",
> + DRM_DEBUG("Branch in thread switch at ip %d",
> ip);
> goto fail;
> }
>
> break;
> default:
> - DRM_ERROR("Unsupported QPU signal %d at "
> + DRM_DEBUG("Unsupported QPU signal %d at "
> "instruction %d\n", sig, ip);
> goto fail;
> }
> @@ -898,7 +898,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
> }
>
> if (ip == validation_state.max_ip) {
> - DRM_ERROR("shader failed to terminate before "
> + DRM_DEBUG("shader failed to terminate before "
> "shader BO end at %zd\n",
> shader_obj->base.size);
> goto fail;
> @@ -907,7 +907,7 @@ vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
> /* Might corrupt other thread */
> if (validated_shader->is_threaded &&
> validation_state.all_registers_used) {
> - DRM_ERROR("Shader uses threading, but uses the upper "
> + DRM_DEBUG("Shader uses threading, but uses the upper "
> "half of the registers, too\n");
> goto fail;
> }
On Tue, 25 Jul 2017 09:27:33 -0700
Eric Anholt <[email protected]> wrote:
> This is useful to allow GL to provide defined results for overlapping
> glBlitFramebuffer, which X11 in turn uses to accelerate uncomposited
> window movement without first blitting to a temporary. x11perf
> -copywinwin100 goes from 1850/sec to 4850/sec.
>
> Signed-off-by: Eric Anholt <[email protected]>
> ---
>
> The work-in-progress userspace is at:
>
> https://github.com/anholt/xserver/commits/glamor-draw-bounds-overlap
> https://github.com/anholt/mesa/commits/vc4-overlapping-blit
>
> and the next step is to build the GL extension spec and piglit tests
> for it.
>
> drivers/gpu/drm/vc4/vc4_drv.c | 1 +
> drivers/gpu/drm/vc4/vc4_gem.c | 5 ++++-
> drivers/gpu/drm/vc4/vc4_render_cl.c | 21 ++++++++++++++++-----
> include/uapi/drm/vc4_drm.h | 11 +++++++++++
> 4 files changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
> index c6b487c3d2b7..b5c2c28289ed 100644
> --- a/drivers/gpu/drm/vc4/vc4_drv.c
> +++ b/drivers/gpu/drm/vc4/vc4_drv.c
> @@ -99,6 +99,7 @@ static int vc4_get_param_ioctl(struct drm_device *dev, void *data,
> case DRM_VC4_PARAM_SUPPORTS_BRANCHES:
> case DRM_VC4_PARAM_SUPPORTS_ETC1:
> case DRM_VC4_PARAM_SUPPORTS_THREADED_FS:
> + case DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER:
> args->value = true;
> break;
> default:
> diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
> index a3e45e67f417..ba0782ebda34 100644
> --- a/drivers/gpu/drm/vc4/vc4_gem.c
> +++ b/drivers/gpu/drm/vc4/vc4_gem.c
> @@ -1008,7 +1008,10 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
> struct ww_acquire_ctx acquire_ctx;
> int ret = 0;
>
> - if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) {
> + if ((args->flags & ~(VC4_SUBMIT_CL_USE_CLEAR_COLOR |
> + VC4_SUBMIT_CL_FIXED_RCL_ORDER |
> + VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X |
> + VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y)) != 0) {
> DRM_DEBUG("Unknown flags: 0x%02x\n", args->flags);
> return -EINVAL;
> }
> diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c
> index da3bfd53f0bd..c3b064052147 100644
> --- a/drivers/gpu/drm/vc4/vc4_render_cl.c
> +++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
> @@ -261,8 +261,17 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
> uint8_t max_y_tile = args->max_y_tile;
> uint8_t xtiles = max_x_tile - min_x_tile + 1;
> uint8_t ytiles = max_y_tile - min_y_tile + 1;
> - uint8_t x, y;
> + uint8_t xi, yi;
> uint32_t size, loop_body_size;
> + bool positive_x = false;
> + bool positive_y = false;
> +
> + if (args->flags & VC4_SUBMIT_CL_FIXED_RCL_ORDER) {
> + if (args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X)
> + positive_x = true;
> + if (args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y)
> + positive_y = true;
> + }
Are you sure you want the default value of positive_x/y to be false? It
seems to me that before this patch you were always iterating in
ascending order, but now, when VC4_SUBMIT_CL_FIXED_RCL_ORDER is not
set you do the opposite. Maybe you really want to change the default
behavior, just wanted to point this out.
Otherwise,
Reviewed-by: Boris Brezillon <[email protected]>
>
> size = VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE;
> loop_body_size = VC4_PACKET_TILE_COORDINATES_SIZE;
> @@ -354,10 +363,12 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
> rcl_u16(setup, args->height);
> rcl_u16(setup, args->color_write.bits);
>
> - for (y = min_y_tile; y <= max_y_tile; y++) {
> - for (x = min_x_tile; x <= max_x_tile; x++) {
> - bool first = (x == min_x_tile && y == min_y_tile);
> - bool last = (x == max_x_tile && y == max_y_tile);
> + for (yi = 0; yi < ytiles; yi++) {
> + int y = positive_y ? min_y_tile + yi : max_y_tile - yi;
> + for (xi = 0; xi < xtiles; xi++) {
> + int x = positive_x ? min_x_tile + xi : max_x_tile - xi;
> + bool first = (xi == 0 && yi == 0);
> + bool last = (xi == xtiles - 1 && yi == ytiles - 1);
>
> emit_tile(exec, setup, x, y, first, last);
> }
> diff --git a/include/uapi/drm/vc4_drm.h b/include/uapi/drm/vc4_drm.h
> index 6ac4c5c014cb..a8bf9a76d5b6 100644
> --- a/include/uapi/drm/vc4_drm.h
> +++ b/include/uapi/drm/vc4_drm.h
> @@ -153,6 +153,16 @@ struct drm_vc4_submit_cl {
> __u32 pad:24;
>
> #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
> +/* By default, the kernel gets to choose the order that the tiles are
> + * rendered in. If this is set, then the tiles will be rendered in a
> + * raster order, with the right-to-left vs left-to-right and
> + * top-to-bottom vs bottom-to-top dictated by
> + * VC4_SUBMIT_CL_RCL_ORDER_INCREASING_*. This allows overlapping
> + * blits to be implemented using the 3D engine.
> + */
> +#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)
> +#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)
> +#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)
> __u32 flags;
>
> /* Returned value of the seqno of this render job (for the
> @@ -292,6 +302,7 @@ struct drm_vc4_get_hang_state {
> #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
> #define DRM_VC4_PARAM_SUPPORTS_ETC1 4
> #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
> +#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6
>
> struct drm_vc4_get_param {
> __u32 param;
Boris Brezillon <[email protected]> writes:
> On Tue, 25 Jul 2017 09:27:33 -0700
> Eric Anholt <[email protected]> wrote:
>
>> This is useful to allow GL to provide defined results for overlapping
>> glBlitFramebuffer, which X11 in turn uses to accelerate uncomposited
>> window movement without first blitting to a temporary. x11perf
>> -copywinwin100 goes from 1850/sec to 4850/sec.
>>
>> Signed-off-by: Eric Anholt <[email protected]>
>> ---
>>
>> The work-in-progress userspace is at:
>>
>> https://github.com/anholt/xserver/commits/glamor-draw-bounds-overlap
>> https://github.com/anholt/mesa/commits/vc4-overlapping-blit
>>
>> and the next step is to build the GL extension spec and piglit tests
>> for it.
>>
>> drivers/gpu/drm/vc4/vc4_drv.c | 1 +
>> drivers/gpu/drm/vc4/vc4_gem.c | 5 ++++-
>> drivers/gpu/drm/vc4/vc4_render_cl.c | 21 ++++++++++++++++-----
>> include/uapi/drm/vc4_drm.h | 11 +++++++++++
>> 4 files changed, 32 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
>> index c6b487c3d2b7..b5c2c28289ed 100644
>> --- a/drivers/gpu/drm/vc4/vc4_drv.c
>> +++ b/drivers/gpu/drm/vc4/vc4_drv.c
>> @@ -99,6 +99,7 @@ static int vc4_get_param_ioctl(struct drm_device *dev, void *data,
>> case DRM_VC4_PARAM_SUPPORTS_BRANCHES:
>> case DRM_VC4_PARAM_SUPPORTS_ETC1:
>> case DRM_VC4_PARAM_SUPPORTS_THREADED_FS:
>> + case DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER:
>> args->value = true;
>> break;
>> default:
>> diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
>> index a3e45e67f417..ba0782ebda34 100644
>> --- a/drivers/gpu/drm/vc4/vc4_gem.c
>> +++ b/drivers/gpu/drm/vc4/vc4_gem.c
>> @@ -1008,7 +1008,10 @@ vc4_submit_cl_ioctl(struct drm_device *dev, void *data,
>> struct ww_acquire_ctx acquire_ctx;
>> int ret = 0;
>>
>> - if ((args->flags & ~VC4_SUBMIT_CL_USE_CLEAR_COLOR) != 0) {
>> + if ((args->flags & ~(VC4_SUBMIT_CL_USE_CLEAR_COLOR |
>> + VC4_SUBMIT_CL_FIXED_RCL_ORDER |
>> + VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X |
>> + VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y)) != 0) {
>> DRM_DEBUG("Unknown flags: 0x%02x\n", args->flags);
>> return -EINVAL;
>> }
>> diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c b/drivers/gpu/drm/vc4/vc4_render_cl.c
>> index da3bfd53f0bd..c3b064052147 100644
>> --- a/drivers/gpu/drm/vc4/vc4_render_cl.c
>> +++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
>> @@ -261,8 +261,17 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
>> uint8_t max_y_tile = args->max_y_tile;
>> uint8_t xtiles = max_x_tile - min_x_tile + 1;
>> uint8_t ytiles = max_y_tile - min_y_tile + 1;
>> - uint8_t x, y;
>> + uint8_t xi, yi;
>> uint32_t size, loop_body_size;
>> + bool positive_x = false;
>> + bool positive_y = false;
>> +
>> + if (args->flags & VC4_SUBMIT_CL_FIXED_RCL_ORDER) {
>> + if (args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X)
>> + positive_x = true;
>> + if (args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y)
>> + positive_y = true;
>> + }
>
> Are you sure you want the default value of positive_x/y to be false? It
> seems to me that before this patch you were always iterating in
> ascending order, but now, when VC4_SUBMIT_CL_FIXED_RCL_ORDER is not
> set you do the opposite. Maybe you really want to change the default
> behavior, just wanted to point this out.
>
> Otherwise,
>
> Reviewed-by: Boris Brezillon <[email protected]>
I was undecided as well, but if you also thought it was funny to change
the default, that's convinced me to keep it the same.
Thanks!