We are adding the Cavium OCTEON-III network driver. But since
interacting with the input and output queues is done via special CPU
local memory, we also need to add support to the MIPS/Octeon
architecture code. Aren't SoCs nice in this way?
The first five patches add the SoC support needed by the driver, the
last two add the driver and an entry in MAINTAINERS.
Since these touch several subsystems, I would propose merging via
netdev, but defer to the maintainers if they think something else
would work better.
A separate pull request was recently done by Steven Hill for the
firmware required by the driver.
Carlos Munoz (5):
dt-bindings: Add Cavium Octeon Common Ethernet Interface.
MIPS: Octeon: Enable LMTDMA/LMTST operations.
MIPS: Octeon: Add a global resource manager.
MIPS: Octeon: Add Free Pointer Unit (FPA) support.
netdev: octeon-ethernet: Add Cavium Octeon III support.
David Daney (2):
MIPS: Octeon: Automatically provision CVMSEG space.
MAINTAINERS: Add entry for
drivers/net/ethernet/cavium/octeon/octeon3-*
.../devicetree/bindings/net/cavium-bgx.txt | 59 +
MAINTAINERS | 6 +
arch/mips/cavium-octeon/Kconfig | 37 +-
arch/mips/cavium-octeon/Makefile | 4 +-
arch/mips/cavium-octeon/octeon-fpa3.c | 363 ++++
arch/mips/cavium-octeon/resource-mgr.c | 362 ++++
arch/mips/cavium-octeon/setup.c | 22 +-
.../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +-
arch/mips/include/asm/mipsregs.h | 2 +
arch/mips/include/asm/octeon/octeon.h | 47 +-
arch/mips/include/asm/processor.h | 2 +-
arch/mips/kernel/octeon_switch.S | 2 -
arch/mips/kernel/unaligned.c | 3 +
arch/mips/mm/tlbex.c | 29 +-
drivers/net/ethernet/cavium/Kconfig | 28 +-
drivers/net/ethernet/cavium/octeon/Makefile | 6 +
.../net/ethernet/cavium/octeon/octeon3-bgx-nexus.c | 698 +++++++
.../net/ethernet/cavium/octeon/octeon3-bgx-port.c | 2023 +++++++++++++++++++
drivers/net/ethernet/cavium/octeon/octeon3-core.c | 2075 ++++++++++++++++++++
drivers/net/ethernet/cavium/octeon/octeon3-pki.c | 833 ++++++++
drivers/net/ethernet/cavium/octeon/octeon3-pko.c | 1719 ++++++++++++++++
drivers/net/ethernet/cavium/octeon/octeon3-sso.c | 309 +++
drivers/net/ethernet/cavium/octeon/octeon3.h | 411 ++++
23 files changed, 9005 insertions(+), 55 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/cavium-bgx.txt
create mode 100644 arch/mips/cavium-octeon/octeon-fpa3.c
create mode 100644 arch/mips/cavium-octeon/resource-mgr.c
create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-nexus.c
create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-bgx-port.c
create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-core.c
create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pki.c
create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-pko.c
create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3-sso.c
create mode 100644 drivers/net/ethernet/cavium/octeon/octeon3.h
--
2.13.6
From 1582904213620436729@xxx Wed Nov 01 22:24:53 +0000 2017
X-GM-THRID: 1582904213620436729
X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread
Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate
the amount of CVMSEG space needed.
1st 128-bytes: Use by IOBDMA
2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.
3rd 128-bytes: OCTEON-III LMTLINE
New config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions
additional lines, defaults to zero.
Signed-off-by: David Daney <[email protected]>
Signed-off-by: Carlos Munoz <[email protected]>
---
arch/mips/cavium-octeon/Kconfig | 27 ++++++++++++--------
arch/mips/cavium-octeon/setup.c | 16 ++++++------
.../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +++++++++------
arch/mips/include/asm/mipsregs.h | 2 ++
arch/mips/include/asm/octeon/octeon.h | 2 ++
arch/mips/include/asm/processor.h | 2 +-
arch/mips/kernel/octeon_switch.S | 2 --
arch/mips/kernel/unaligned.c | 3 +++
arch/mips/mm/tlbex.c | 29 ++++++----------------
9 files changed, 52 insertions(+), 51 deletions(-)
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index 211ef5b57214..fc6a1b44605b 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -10,21 +10,26 @@ config CAVIUM_CN63XXP1
non-CN63XXP1 hardware, so it is recommended to select "n"
unless it is known the workarounds are needed.
-config CAVIUM_OCTEON_CVMSEG_SIZE
- int "Number of L1 cache lines reserved for CVMSEG memory"
- range 0 54
- default 1
- help
- CVMSEG LM is a segment that accesses portions of the dcache as a
- local memory; the larger CVMSEG is, the smaller the cache is.
- This selects the size of CVMSEG LM, which is in cache blocks. The
- legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
- between zero and 6192 bytes).
-
endif # CPU_CAVIUM_OCTEON
if CAVIUM_OCTEON_SOC
+config CAVIUM_OCTEON_EXTRA_CVMSEG
+ int "Number of extra L1 cache lines reserved for CVMSEG memory"
+ range 0 50
+ default 0
+ help
+ CVMSEG LM is a segment that accesses portions of the dcache
+ as a local memory; the larger CVMSEG is, the smaller the
+ cache is. The kernel uses two or three blocks (one for TLB
+ exception handlers, one for driver IOBDMA operations, and on
+ models that need it, one for LMTDMA operations). This
+ selects an optional extra number of CVMSEG lines for use by
+ other software.
+
+ Normally no extra lines are required, and this parameter
+ should be set to zero.
+
config CAVIUM_OCTEON_LOCK_L2
bool "Lock often used kernel code in the L2"
default "y"
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 99e6a68bc652..51c4d3c3cada 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);
static unsigned long long max_memory = ULLONG_MAX;
static unsigned long long reserve_low_mem;
+/*
+ * modified in hernel-entry-init.h, must have an initial value to keep
+ * it from being clobbered when bss is zeroed.
+ */
+u32 octeon_cvmseg_lines = 2;
+
DEFINE_SEMAPHORE(octeon_bootbus_sem);
EXPORT_SYMBOL(octeon_bootbus_sem);
@@ -604,11 +610,7 @@ void octeon_user_io_init(void)
/* R/W If set, CVMSEG is available for loads/stores in
* kernel/debug mode. */
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
cvmmemctl.s.cvmsegenak = 1;
-#else
- cvmmemctl.s.cvmsegenak = 0;
-#endif
if (OCTEON_IS_OCTEON3()) {
/* Enable LMTDMA */
cvmmemctl.s.lmtena = 1;
@@ -626,9 +628,9 @@ void octeon_user_io_init(void)
/* Setup of CVMSEG is done in kernel-entry-init.h */
if (smp_processor_id() == 0)
- pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
+ pr_notice("CVMSEG size: %u cache lines (%u bytes)\n",
+ octeon_cvmseg_lines,
+ octeon_cvmseg_lines * 128);
if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
union cvmx_iob_fau_timeout fau_timeout;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index c38b38ce5a3d..cdcca60978a2 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -26,11 +26,18 @@
# a3 = address of boot descriptor block
.set push
.set arch=octeon
+ mfc0 v1, CP0_PRID_REG
+ andi v1, 0xff00
+ li v0, 0x9500 # cn78XX or later
+ subu v1, v1, v0
+ li t2, 2 + CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG
+ bltz v1, 1f
+ addiu t2, 1 # t2 has cvmseg_size
+1:
# Read the cavium mem control register
dmfc0 v0, CP0_CVMMEMCTL_REG
# Clear the lower 6 bits, the CVMSEG size
- dins v0, $0, 0, 6
- ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
+ dins v0, t2, 0, 6
dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
# Disable unaligned load/store support but leave HW fixup enabled
@@ -70,7 +77,7 @@
# Flush dcache after config change
cache 9, 0($0)
# Zero all of CVMSEG to make sure parity is correct
- dli v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
+ move v0, t2
dsll v0, 7
beqz v0, 2f
1: dsubu v0, 8
@@ -126,12 +133,7 @@
LONG_L sp, (t0)
# Set the SP global variable to zero so the master knows we've started
LONG_S zero, (t0)
-#ifdef __OCTEON__
- syncw
- syncw
-#else
sync
-#endif
# Jump to the normal Linux SMP entry point
j smp_bootstrap
nop
@@ -148,6 +150,8 @@
#endif /* CONFIG_SMP */
octeon_main_processor:
+ dla v0, octeon_cvmseg_lines
+ sw t2, 0(v0)
.set pop
.endm
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index a6810923b3f0..df7654d7333d 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1126,6 +1126,8 @@
#define FPU_CSR_RD 0x3 /* towards -Infinity */
+#define CAVIUM_OCTEON_SCRATCH_OFFSET (2 * 128 - 16 - 32768)
+
#ifndef __ASSEMBLY__
/*
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index d184592e6515..02eb194b2cdc 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -392,6 +392,8 @@ static inline uint32_t octeon_npi_read32(uint64_t address)
extern struct cvmx_bootinfo *octeon_bootinfo;
+extern u32 octeon_cvmseg_lines;
+
extern uint64_t octeon_bootloader_entry_addr;
extern void (*octeon_irq_setup_secondary)(void);
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 95b8c471f572..3d264008afcb 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -216,7 +216,7 @@ struct octeon_cop2_state {
.cp2 = {0,},
struct octeon_cvmseg_state {
- unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
+ unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG + 3]
[cpu_dcache_line_size() / sizeof(unsigned long)];
};
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index e42113fe2762..4f56902d5ee7 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -29,7 +29,6 @@
cpu_save_nonscratch a0
LONG_S ra, THREAD_REG31(a0)
-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
/* Check if we need to store CVMSEG state */
dmfc0 t0, $11,7 /* CvmMemCtl */
bbit0 t0, 6, 3f /* Is user access enabled? */
@@ -58,7 +57,6 @@
dmfc0 t0, $11,7 /* CvmMemCtl */
xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
dmtc0 t0, $11,7 /* CvmMemCtl */
-#endif
3:
#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 2d0b912f9e3e..610f9b4ccdae 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -2281,6 +2281,9 @@ static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
force_sig(SIGILL, current);
}
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#include <asm/octeon/octeon.h>
+#endif
asmlinkage void do_ade(struct pt_regs *regs)
{
enum ctx_state prev_state;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 79b9f2ad3ff5..3d3dfba465ae 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -115,33 +115,17 @@ static int use_lwx_insns(void)
return 0;
}
}
-#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \
- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
-static bool scratchpad_available(void)
-{
- return true;
-}
-static int scratchpad_offset(int i)
-{
- /*
- * CVMSEG starts at address -32768 and extends for
- * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.
- */
- i += 1; /* Kernel use starts at the top and works down. */
- return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;
-}
-#else
-static bool scratchpad_available(void)
-{
- return false;
-}
+
static int scratchpad_offset(int i)
{
+ if (IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON))
+ return (CAVIUM_OCTEON_SCRATCH_OFFSET - (8 * i));
+
BUG();
/* Really unreachable, but evidently some GCC want this. */
return 0;
}
-#endif
+
/*
* Found by experiment: At least some revisions of the 4kc throw under
* some circumstances a machine check exception, triggered by invalid
@@ -1302,7 +1286,8 @@ static void build_r4000_tlb_refill_handler(void)
memset(relocs, 0, sizeof(relocs));
memset(final_handler, 0, sizeof(final_handler));
- if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
+ if (IS_ENABLED(CONFIG_64BIT) && use_bbit_insns() &&
+ (scratch_reg >= 0 || IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON))) {
htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
scratch_reg);
vmalloc_mode = refill_scratch;
--
2.13.6
From 1582902942701786194@xxx Wed Nov 01 22:04:41 +0000 2017
X-GM-THRID: 1582902942701786194
X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread
Signed-off-by: David Daney <[email protected]>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 9a24f56e0451..142af33adc35 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3212,6 +3212,12 @@ W: http://www.cavium.com
S: Supported
F: drivers/mmc/host/cavium*
+CAVIUM OCTEON-III NETWORK DRIVER
+M: David Daney <[email protected]>
+L: [email protected]
+S: Supported
+F: drivers/net/ethernet/cavium/octeon/octeon3-*
+
CAVIUM OCTEON-TX CRYPTO DRIVER
M: George Cherian <[email protected]>
L: [email protected]
--
2.13.6
From 1582989230311287859@xxx Thu Nov 02 20:56:12 +0000 2017
X-GM-THRID: 1582989230311287859
X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread
From: Carlos Munoz <[email protected]>
LMTDMA/LMTST operations move data between cores and I/O devices:
* LMTST operations can send an address and a variable length
(up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
(up to 128) of data to the I/O device and then return a
variable length (up to 128 bytes) response from the IOI device.
Signed-off-by: Carlos Munoz <[email protected]>
Signed-off-by: Steven J. Hill <[email protected]>
Signed-off-by: David Daney <[email protected]>
---
arch/mips/cavium-octeon/setup.c | 6 ++++++
arch/mips/include/asm/octeon/octeon.h | 12 ++++++++++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
#else
cvmmemctl.s.cvmsegenak = 0;
#endif
+ if (OCTEON_IS_OCTEON3()) {
+ /* Enable LMTDMA */
+ cvmmemctl.s.lmtena = 1;
+ /* Scratch line to use for LMT operation */
+ cvmmemctl.s.lmtline = 2;
+ }
/* R/W If set, CVMSEG is available for loads/stores in
* supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
- __BITFIELD_FIELD(uint64_t reserved:17,
+ __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+ /* When set, LMTDMA/LMTST operations are permitted */
+ __BITFIELD_FIELD(uint64_t lmtena:1,
+ /* Selects the CVMSEG LM cacheline used by LMTDMA
+ * LMTST and wide atomic store operations.
+ */
+ __BITFIELD_FIELD(uint64_t lmtline:6,
+ /* Reserved */
+ __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
* This field selects between the TLB replacement policies:
* bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
* bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
- ;)))))))))))))))))))))))))))))))))
+ ;))))))))))))))))))))))))))))))))))))
} s;
};
--
2.13.6
From 1586423014667467931@xxx Sun Dec 10 18:34:44 +0000 2017
X-GM-THRID: 1586423014667467931
X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread