On 10/05, [email protected] wrote:
> From: Chen Zhong <[email protected]>
>
> Since the previous setup always sets the PLL using crystal 26MHz, this
> doesn't always happen in every MediaTek platform. So the patch added
> flexibility for assigning extra member for determining the PLL source
> clock.
>
> Signed-off-by: Chen Zhong <[email protected]>
> Signed-off-by: Sean Wang <[email protected]>
> ---
Applied to clk-next
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