2017-11-09 05:57:20

by Luc Van Oostenryck

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Subject: [PATCH 0/2] riscv: pass endianness and machine size to sparse

The goal of these two patches is to ass endianness and machine
size info to sparse so that sparse can emit correct diagnostics
even when the endianness and machine size doesn't correspond to
sparse's defaults.

Luc Van Oostenryck (2):
riscv: pass endianness info to sparse
riscv: pass machine size to sparse

arch/riscv/Makefile | 4 ++++
1 file changed, 4 insertions(+)

--

To: Palmer Dabbelt <[email protected]>
CC: Albert Ou <[email protected]>
CC: [email protected]
CC: [email protected]

From 1583622187639450904@xxx Thu Nov 09 20:36:47 +0000 2017
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2017-11-09 05:57:14

by Luc Van Oostenryck

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Subject: [PATCH 2/2] riscv: pass machine size to sparse

By default, sparse assumes a 64bit machine when compiled on x86-64
and 32bit when compiled on anything else.

This can of course create all sort of problems when this doesn't
correspond to the target's machine size, like issuing false
warnings like: 'constant ... is so big it is unsigned long long'
or 'shift too big (32) for type unsigned long' when the architecture
is 64bit while sparse was compiled on a 32bit machine, or worse,
to not emit legitimate warnings in the reverse situation.

Fix this by passing the appropriate -m32/-m64 flag to sparse.

Signed-off-by: Luc Van Oostenryck <[email protected]>
---
arch/riscv/Makefile | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 206484dde..a0ea7a71d 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -27,6 +27,7 @@ ifeq ($(CONFIG_ARCH_RV64I),y)
KBUILD_AFLAGS += -mabi=lp64
KBUILD_MARCH = rv64im
LDFLAGS += -melf64lriscv
+ CHECKFLAGS += -m64
else
BITS := 32
UTS_MACHINE := riscv32
@@ -35,6 +36,7 @@ else
KBUILD_AFLAGS += -mabi=ilp32
KBUILD_MARCH = rv32im
LDFLAGS += -melf32lriscv
+ CHECKFLAGS += -m32
endif

KBUILD_CFLAGS += -Wall
--
2.14.0


From 1583491044662866706@xxx Wed Nov 08 09:52:19 +0000 2017
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2017-11-09 05:57:00

by Luc Van Oostenryck

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Subject: [PATCH 1/2] riscv: pass endianness info to sparse

RISC-V is little-endian only but sparse assumes the same
endianness as the building machine.
This is problematic for code which expect __BYTE_ORDER__ being
correctly predefined by the compiler which sparse can then
pre-process differently from what gcc would, depending on the
building machine endianness.

To avoid any possible problem, fix this by letting sparse know
about the architecture endianness.

Signed-off-by: Luc Van Oostenryck <[email protected]>
---
arch/riscv/Makefile | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 6719dd30e..206484dde 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -16,6 +16,8 @@ KBUILD_CFLAGS_MODULE += -fPIC

KBUILD_DEFCONFIG = defconfig

+CHECKFLAGS += -mlittle-endian
+
export BITS
ifeq ($(CONFIG_ARCH_RV64I),y)
BITS := 64
--
2.14.0


From 1583442318136708471@xxx Tue Nov 07 20:57:50 +0000 2017
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