Add missing pin group uart5nocts (all pins except cts), which has been
supported by the artpec6 pinctrl driver since its initial submission.
Fixes: 00df0582eab1 ("pinctrl: Add pincontrol driver for ARTPEC-6 SoC")
Signed-off-by: Niklas Cassel <[email protected]>
---
Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
index 47284f85ec80..c3f9826692bc 100644
--- a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
@@ -20,7 +20,8 @@ Required subnode-properties:
gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
- uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0
+ uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0,
+ uart5nocts
cpuclkout: cpuclkoutgrp0
udlclkout: udlclkoutgrp0
i2c1: i2c1grp0
@@ -37,7 +38,7 @@ Required subnode-properties:
uart2: uart2grp0, uart2grp1
uart3: uart3grp0
uart4: uart4grp0
- uart5: uart5grp0
+ uart5: uart5grp0, uart5nocts
nand: nandgrp0
sdio0: sdio0grp0
sdio1: sdio1grp0
--
2.14.2
Add group configuration for uarts that are cut down
variants, the standard being full, i.e. all signals,
flow control, i.e. rx/tx and cts/rts, and rx/tx only.
This allows us to be more precise in which pins we're
actually using.
Unfortunately the existing naming scheme leaves things
to be desired, e.g. uart3grp0 means RX/TX and CTS/RTS,
yet uart0grp0 means all pins.
Since the exising suffixes have different meaning for
different uarts, and the fact that we cannot change
the name of existing groups, makes it hard to use a
descriptive name for the newly added groups.
Signed-off-by: Niklas Cassel <[email protected]>
---
.../devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
index c3f9826692bc..678f5097058e 100644
--- a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt
@@ -19,8 +19,9 @@ Required subnode-properties:
Available functions and groups (function: group0, group1...):
gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
- spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
- uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0,
+ spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2,
+ uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2,
+ uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1,
uart5nocts
cpuclkout: cpuclkoutgrp0
udlclkout: udlclkoutgrp0
@@ -33,12 +34,12 @@ Required subnode-properties:
spi0: spi0grp0
spi1: spi1grp0
pciedebug: pciedebuggrp0
- uart0: uart0grp0, uart0grp1
- uart1: uart1grp0
- uart2: uart2grp0, uart2grp1
+ uart0: uart0grp0, uart0grp1, uart0grp2
+ uart1: uart1grp0, uart1grp1
+ uart2: uart2grp0, uart2grp1, uart2grp2
uart3: uart3grp0
- uart4: uart4grp0
- uart5: uart5grp0, uart5nocts
+ uart4: uart4grp0, uart4grp1
+ uart5: uart5grp0, uart5grp1, uart5nocts
nand: nandgrp0
sdio0: sdio0grp0
sdio1: sdio1grp0
--
2.14.2
On Thu, Feb 22, 2018 at 4:22 PM, Niklas Cassel <[email protected]> wrote:
> Add missing pin group uart5nocts (all pins except cts), which has been
> supported by the artpec6 pinctrl driver since its initial submission.
>
> Fixes: 00df0582eab1 ("pinctrl: Add pincontrol driver for ARTPEC-6 SoC")
> Signed-off-by: Niklas Cassel <[email protected]>
Patch applied.
Yours,
Linus Walleij
On Thu, Feb 22, 2018 at 4:22 PM, Niklas Cassel <[email protected]> wrote:
> Add group configuration for uarts that are cut down
> variants, the standard being full, i.e. all signals,
> flow control, i.e. rx/tx and cts/rts, and rx/tx only.
>
> This allows us to be more precise in which pins we're
> actually using.
>
> Unfortunately the existing naming scheme leaves things
> to be desired, e.g. uart3grp0 means RX/TX and CTS/RTS,
> yet uart0grp0 means all pins.
> Since the exising suffixes have different meaning for
> different uarts, and the fact that we cannot change
> the name of existing groups, makes it hard to use a
> descriptive name for the newly added groups.
>
> Signed-off-by: Niklas Cassel <[email protected]>
Patch applied.
Yours,
Linus Walleij
On Thu, Feb 22, 2018 at 04:22:46PM +0100, Niklas Cassel wrote:
> Add missing pin group uart5nocts (all pins except cts), which has been
> supported by the artpec6 pinctrl driver since its initial submission.
>
> Fixes: 00df0582eab1 ("pinctrl: Add pincontrol driver for ARTPEC-6 SoC")
> Signed-off-by: Niklas Cassel <[email protected]>
> ---
> Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Rob Herring <[email protected]>