2018-04-17 15:54:10

by Eugeniy Paltsev

Subject: [PATCH] clocksource: arc_timer: add comments about locking while read GFRC

This came to light in some internal discussions and it is nice to have
this documented rather than digging up the PRM (Prog Ref Manual) again.

Signed-off-by: Eugeniy Paltsev <[email protected]>
---
drivers/clocksource/arc_timer.c | 13 +++++++++++++
1 file changed, 13 insertions(+)

diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c
index 4927355f9cbe..b594c373debc 100644
--- a/drivers/clocksource/arc_timer.c
+++ b/drivers/clocksource/arc_timer.c
@@ -61,6 +61,19 @@ static u64 arc_read_gfrc(struct clocksource *cs)
unsigned long flags;
u32 l, h;

+ /*
+ * MCIP_CMD/MCIP_READBACK registers are allocated
+ * PER ARC CORE (not per cluster), and there are dedicated hardware
+ * decode logic (per core) inside ARConnect to handle simultaneous
+ * read/write accesses from cores via those two registers.
+ * So several concurrent commands to ARConnect are OK if they are
+ * trying to access two different sub-components (like GFRC,
+ * inter-core interrupt, etc...). HW also support simultaneously
+ * accessing GFRC by multiple cores.
+ * That's why it is safe to disable hard interrupts on the local CPU
+ * before access to GFRC instead of taking global MCIP spinlock
+ * defined in arch/arc/kernel/mcip.c
+ */
local_irq_save(flags);

__mcip_cmd(CMD_GFRC_READ_LO, 0);
--
2.14.3

2018-04-17 17:00:50

by Vineet Gupta

Subject: Re: [PATCH] clocksource: arc_timer: add comments about locking while read GFRC

On 04/17/2018 08:52 AM, Eugeniy Paltsev wrote:
> This came to light in some internal discussions and it is nice to have
> this documented rather than digging up the PRM (Prog Ref Manual) again.
>
> Signed-off-by: Eugeniy Paltsev <[email protected]>

Minor nits below, otherwise LGTM !
Acked-by: Vineet Gupta <[email protected]>

> ---
> drivers/clocksource/arc_timer.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c
> index 4927355f9cbe..b594c373debc 100644
> --- a/drivers/clocksource/arc_timer.c
> +++ b/drivers/clocksource/arc_timer.c
> @@ -61,6 +61,19 @@ static u64 arc_read_gfrc(struct clocksource *cs)
> unsigned long flags;
> u32 l, h;
>
> + /*
> + * MCIP_CMD/MCIP_READBACK registers are allocated

From a programming model pov, there seems to be just one instance of
MCIP_CMD/MCIP_READBACK however micro-architecturally there's an instance PER ARC
CORE.....
> + * PER ARC CORE (not per cluster), and there are dedicated hardware
> + * decode logic (per core) inside ARConnect to handle simultaneous
> + * read/write accesses from cores via those two registers.
> + * So several concurrent commands to ARConnect are OK if they are
> + * trying to access two different sub-components (like GFRC,
> + * inter-core interrupt, etc...). HW also support simultaneously

s/support/supports/

> + * accessing GFRC by multiple cores.
> + * That's why it is safe to disable hard interrupts on the local CPU
> + * before access to GFRC instead of taking global MCIP spinlock
> + * defined in arch/arc/kernel/mcip.c
> + */
> local_irq_save(flags);
>
> __mcip_cmd(CMD_GFRC_READ_LO, 0);