2018-04-24 18:52:40

by Maxime Jourdan

Subject: [PATCH v2 0/2] clk: meson: gxbb: add the video decoder clocks

This adds the necessary clocks for VDEC_1 and VDEC_HEVC.

On Amlogic SoCs, VDEC1 is responsible for the decoding of:
MPEG 1/2/4, H.263, H.264, MJPEG, VC1, Real Video

VDEC_HEVC is responsible for the decoding of:
HEVC, VP9

Changes since v1:
- Drop CLK_IGNORE_UNUSED flags
- Change CLK_SET_RATE_NO_REPARENT to CLK_SET_RATE_PARENT for muxes
- Add CLK_MUX_ROUND_CLOSEST for muxes

Maxime Jourdan (2):
clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
clk: meson: gxbb: add the video decoder clocks

drivers/clk/meson/gxbb.c | 114 ++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 6 +-
include/dt-bindings/clock/gxbb-clkc.h | 2 +
3 files changed, 121 insertions(+), 1 deletion(-)

--
2.17.0

2018-04-24 18:52:00

by Maxime Jourdan

Subject: [PATCH v2 1/2] clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks

Signed-off-by: Maxime Jourdan <[email protected]>
---
include/dt-bindings/clock/gxbb-clkc.h | 2 ++
1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 8ba99a5e3fd3..7a892be90549 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -125,5 +125,7 @@
#define CLKID_VAPB_1 138
#define CLKID_VAPB_SEL 139
#define CLKID_VAPB 140
+#define CLKID_VDEC_1 153
+#define CLKID_VDEC_HEVC 156

#endif /* __GXBB_CLKC_H */
--
2.17.0

2018-04-24 18:53:00

by Maxime Jourdan

Subject: [PATCH v2 2/2] clk: meson: gxbb: add the video decoder clocks

Add the SEL/DIV/GATE for VDEC_1 and VDEC_HEVC.

Signed-off-by: Maxime Jourdan <[email protected]>
---
drivers/clk/meson/gxbb.c | 114 +++++++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 6 ++-
2 files changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index b1e4d9557610..a893b1edda22 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1543,6 +1543,102 @@ static struct clk_regmap gxbb_vapb = {
},
};

+/* VDEC clocks */
+
+static const char * const gxbb_vdec_parent_names[] = {
+ "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
+};
+
+static struct clk_regmap gxbb_vdec_1_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_VDEC_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 9,
+ .flags = CLK_MUX_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "vdec_1_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_names = gxbb_vdec_parent_names,
+ .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap gxbb_vdec_1_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_VDEC_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "vdec_1_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_names = (const char *[]){ "vdec_1_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap gxbb_vdec_1 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_VDEC_CLK_CNTL,
+ .bit_idx = 8,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdec_1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "vdec_1_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap gxbb_vdec_hevc_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_VDEC2_CLK_CNTL,
+ .mask = 0x3,
+ .shift = 25,
+ .flags = CLK_MUX_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "vdec_hevc_sel",
+ .ops = &clk_regmap_mux_ops,
+ .parent_names = gxbb_vdec_parent_names,
+ .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap gxbb_vdec_hevc_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_VDEC2_CLK_CNTL,
+ .shift = 16,
+ .width = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "vdec_hevc_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_names = (const char *[]){ "vdec_hevc_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap gxbb_vdec_hevc = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_VDEC2_CLK_CNTL,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data) {
+ .name = "vdec_hevc",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "vdec_hevc_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1786,6 +1882,12 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
[CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
[CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
+ [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -1942,6 +2044,12 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
[CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
[CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
[CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
+ [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
+ [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
+ [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
+ [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
+ [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
+ [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -2100,6 +2208,12 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
&gxbb_fclk_div4,
&gxbb_fclk_div5,
&gxbb_fclk_div7,
+ &gxbb_vdec_1_sel,
+ &gxbb_vdec_1_div,
+ &gxbb_vdec_1,
+ &gxbb_vdec_hevc_sel,
+ &gxbb_vdec_hevc_div,
+ &gxbb_vdec_hevc,
};

struct clkc_data {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 9febf3f03739..b3ef54f65a9d 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -204,8 +204,12 @@
#define CLKID_FCLK_DIV4_DIV 148
#define CLKID_FCLK_DIV5_DIV 149
#define CLKID_FCLK_DIV7_DIV 150
+#define CLKID_VDEC_1_SEL 151
+#define CLKID_VDEC_1_DIV 152
+#define CLKID_VDEC_HEVC_SEL 154
+#define CLKID_VDEC_HEVC_DIV 155

-#define NR_CLKS 151
+#define NR_CLKS 157

/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
--
2.17.0

2018-04-25 11:38:54

by Jerome Brunet

Subject: Re: [PATCH v2 1/2] clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks

On Tue, 2018-04-24 at 20:48 +0200, Maxime Jourdan wrote:
> Signed-off-by: Maxime Jourdan <[email protected]>

Even if the change is trivial, please add commit description.
I'll do it for you this time.

Applied to next/headers
Thx

> ---
> include/dt-bindings/clock/gxbb-clkc.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
> index 8ba99a5e3fd3..7a892be90549 100644
> --- a/include/dt-bindings/clock/gxbb-clkc.h
> +++ b/include/dt-bindings/clock/gxbb-clkc.h
> @@ -125,5 +125,7 @@
> #define CLKID_VAPB_1 138
> #define CLKID_VAPB_SEL 139
> #define CLKID_VAPB 140
> +#define CLKID_VDEC_1 153
> +#define CLKID_VDEC_HEVC 156
>
> #endif /* __GXBB_CLKC_H */

2018-04-25 12:04:33

by Jerome Brunet

Subject: Re: [PATCH v2 2/2] clk: meson: gxbb: add the video decoder clocks

On Tue, 2018-04-24 at 20:48 +0200, Maxime Jourdan wrote:
> Add the SEL/DIV/GATE for VDEC_1 and VDEC_HEVC.
>
> Signed-off-by: Maxime Jourdan <[email protected]>

Applied to next/drivers
Thx