by kernel test robot

[permalink] [raw]

Subject: Re: [PATCH v5 06/11] soc: mediatek: add new flow for mtcmos power.

Hi Owen,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.18-rc5 next-20180717]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url: https://github.com/0day-ci/linux/commits/Mars-Cheng/Add-basic-SoC-support-for-mt6765/20180717-205540
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=powerpc

All error/warnings (new ones prefixed by >>):

In file included from include/linux/kernel.h:14:0,
from include/linux/clk.h:16,
from drivers/soc/mediatek/mtk-scpsys-ext.c:6:
drivers/soc/mediatek/mtk-scpsys-ext.c: In function 'bus_clk_enable_disable':
>> drivers/soc/mediatek/mtk-scpsys-ext.c:141:12: error: implicit declaration of function '__clk_get_name'; did you mean 'clk_get_rate'? [-Werror=implicit-function-declaration]
__clk_get_name(cc->clk));
^
include/linux/printk.h:304:33: note: in definition of macro 'pr_err'
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~~~~
In file included from include/linux/printk.h:7:0,
from include/linux/kernel.h:14,
from include/linux/clk.h:16,
from drivers/soc/mediatek/mtk-scpsys-ext.c:6:
>> include/linux/kern_levels.h:5:18: warning: format '%s' expects argument of type 'char *', but argument 3 has type 'int' [-Wformat=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH'
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~~~~~
include/linux/printk.h:304:9: note: in expansion of macro 'KERN_ERR'
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~
>> drivers/soc/mediatek/mtk-scpsys-ext.c:139:5: note: in expansion of macro 'pr_err'
pr_err("Failed to %s %s\n",
^~~~~~
drivers/soc/mediatek/mtk-scpsys-ext.c:139:28: note: format string is defined here
pr_err("Failed to %s %s\n",
~^
%d
cc1: some warnings being treated as errors
--
In file included from include/linux/kernel.h:14:0,
from include/linux/clk.h:16,
from drivers/soc//mediatek/mtk-scpsys-ext.c:6:
drivers/soc//mediatek/mtk-scpsys-ext.c: In function 'bus_clk_enable_disable':
drivers/soc//mediatek/mtk-scpsys-ext.c:141:12: error: implicit declaration of function '__clk_get_name'; did you mean 'clk_get_rate'? [-Werror=implicit-function-declaration]
__clk_get_name(cc->clk));
^
include/linux/printk.h:304:33: note: in definition of macro 'pr_err'
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~~~~
In file included from include/linux/printk.h:7:0,
from include/linux/kernel.h:14,
from include/linux/clk.h:16,
from drivers/soc//mediatek/mtk-scpsys-ext.c:6:
>> include/linux/kern_levels.h:5:18: warning: format '%s' expects argument of type 'char *', but argument 3 has type 'int' [-Wformat=]
#define KERN_SOH "\001" /* ASCII Start Of Header */
^
include/linux/kern_levels.h:11:18: note: in expansion of macro 'KERN_SOH'
#define KERN_ERR KERN_SOH "3" /* error conditions */
^~~~~~~~
include/linux/printk.h:304:9: note: in expansion of macro 'KERN_ERR'
printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~
drivers/soc//mediatek/mtk-scpsys-ext.c:139:5: note: in expansion of macro 'pr_err'
pr_err("Failed to %s %s\n",
^~~~~~
drivers/soc//mediatek/mtk-scpsys-ext.c:139:28: note: format string is defined here
pr_err("Failed to %s %s\n",
~^
%d
cc1: some warnings being treated as errors

vim +141 drivers/soc/mediatek/mtk-scpsys-ext.c

> 6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/soc/mediatek/infracfg.h>
15 #include <linux/soc/mediatek/scpsys-ext.h>
16
17
18 #define MAX_CLKS 10
19 #define INFRA "infracfg"
20 #define SMIC "smi_comm"
21
22 static LIST_HEAD(ext_clk_map_list);
23 static LIST_HEAD(ext_attr_map_list);
24
25 static struct regmap *infracfg;
26 static struct regmap *smi_comm;
27
28 enum regmap_type {
29 IFR_TYPE,
30 SMI_TYPE,
31 MAX_REGMAP_TYPE,
32 };
33
34 /**
35 * struct ext_reg_ctrl - set multiple register for bus protect
36 * @regmap: The bus protect regmap, 1: infracfg, 2: other master regmap
37 * such as SMI.
38 * @set_ofs: The set register offset to set corresponding bit to 1.
39 * @clr_ofs: The clr register offset to clear corresponding bit to 0.
40 * @sta_ofs: The status register offset to show bus protect enable/disable.
41 */
42 struct ext_reg_ctrl {
43 enum regmap_type type;
44 u32 set_ofs;
45 u32 clr_ofs;
46 u32 sta_ofs;
47 };
48
49 /**
50 * struct ext_clk_ctrl - enable multiple clks for bus protect
51 * @clk: The clk need to enable before pwr on/bus protect.
52 * @scpd_n: The name present the scpsys domain where the clks belongs to.
53 * @clk_list: The list node linked to ext_clk_map_list.
54 */
55 struct ext_clk_ctrl {
56 struct clk *clk;
57 const char *scpd_n;
58 struct list_head clk_list;
59 };
60
61 struct bus_mask_ops {
62 int (*set)(struct regmap *regmap, u32 set_ofs,
63 u32 sta_ofs, u32 mask);
64 int (*release)(struct regmap *regmap, u32 clr_ofs,
65 u32 sta_ofs, u32 mask);
66 };
67
68 static struct scpsys_ext_attr *__get_attr_parent(const char *parent_n)
69 {
70 struct scpsys_ext_attr *attr;
71
72 if (!parent_n)
73 return ERR_PTR(-EINVAL);
74
75 list_for_each_entry(attr, &ext_attr_map_list, attr_list) {
76 if (attr->scpd_n && !strcmp(parent_n, attr->scpd_n))
77 return attr;
78 }
79
80 return ERR_PTR(-EINVAL);
81 }
82
83 int bus_ctrl_set_release(struct scpsys_ext_attr *attr, bool set)
84 {
85 int i;
86 int ret = 0;
87
88 for (i = 0; i < MAX_STEP_NUM && attr->mask[i].mask; i++) {
89 struct ext_reg_ctrl *rc = attr->mask[i].regs;
90 struct regmap *regmap;
91
92 if (rc->type == IFR_TYPE)
93 regmap = infracfg;
94 else if (rc->type == SMI_TYPE)
95 regmap = smi_comm;
96 else
97 return -EINVAL;
98
99 if (set)
100 ret = attr->mask[i].ops->set(regmap,
101 rc->set_ofs,
102 rc->sta_ofs,
103 attr->mask[i].mask);
104 else
105 ret = attr->mask[i].ops->release(regmap,
106 rc->clr_ofs,
107 rc->sta_ofs,
108 attr->mask[i].mask);
109 }
110
111 return ret;
112 }
113
114 int bus_ctrl_set(struct scpsys_ext_attr *attr)
115 {
116 return bus_ctrl_set_release(attr, CMD_ENABLE);
117 }
118
119 int bus_ctrl_release(struct scpsys_ext_attr *attr)
120 {
121 return bus_ctrl_set_release(attr, CMD_DISABLE);
122 }
123
124 int bus_clk_enable_disable(struct scpsys_ext_attr *attr, bool enable)
125 {
126 int i = 0;
127 int ret = 0;
128 struct ext_clk_ctrl *cc;
129 struct clk *clk[MAX_CLKS];
130
131 list_for_each_entry(cc, &ext_clk_map_list, clk_list) {
132 if (!strcmp(cc->scpd_n, attr->scpd_n)) {
133 if (enable)
134 ret = clk_prepare_enable(cc->clk);
135 else
136 clk_disable_unprepare(cc->clk);
137
138 if (ret) {
> 139 pr_err("Failed to %s %s\n",
140 enable ? "enable" : "disable",
> 141 __clk_get_name(cc->clk));
142 goto err;
143 } else {
144 clk[i] = cc->clk;
145 i++;
146 }
147 }
148 }
149
150 return ret;
151
152 err:
153 for (--i; i >= 0; i--)
154 if (enable)
155 clk_disable_unprepare(clk[i]);
156 else
157 clk_prepare_enable(clk[i]);
158 return ret;
159 }
160

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation

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Subject: Re: [PATCH v5 01/11] dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC

On Fri, 2018-07-20 at 11:43 -0600, Rob Herring wrote:
> On Tue, Jul 17, 2018 at 04:52:22PM +0800, Mars Cheng wrote:
> > This patch adds the binding documentation for apmixedsys, audsys, camsys,
> > imgsys, infracfg, mipi0a, topckgen, vcodecsys
> >
> > Signed-off-by: Mars Cheng <[email protected]>
> > Signed-off-by: Owen Chen <[email protected]>
> > ---
> > .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,audsys.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,camsys.txt | 27 ++++++++++++++++++++
> > .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,mipi0a.txt | 23 +++++++++++++++++
> > .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,pericfg.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 +
> > .../bindings/arm/mediatek/mediatek,vcodecsys.txt | 22 ++++++++++++++++
> > 10 files changed, 79 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
> > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt
> > create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> > index b404d59..44eaeac 100644
> > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
> > @@ -8,6 +8,7 @@ Required Properties:
> > - compatible: Should be one of:
> > - "mediatek,mt2701-apmixedsys"
> > - "mediatek,mt2712-apmixedsys", "syscon"
> > + - "mediatek,mt6765-apmixedsys", "syscon"
> > - "mediatek,mt6797-apmixedsys"
> > - "mediatek,mt7622-apmixedsys"
> > - "mediatek,mt8135-apmixedsys"
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> > index 34a69ba..9a8672a 100644
> > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
> > @@ -7,6 +7,7 @@ Required Properties:
> >
> > - compatible: Should be one of:
> > - "mediatek,mt2701-audsys", "syscon"
> > + - "mediatek,mt6765-audsys", "syscon"
> > - "mediatek,mt7622-audsys", "syscon"
> > - #clock-cells: Must be 1
> >
> > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
> > new file mode 100644
> > index 0000000..dc75783
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
> > @@ -0,0 +1,27 @@
> > +MediaTek CAMSYS controller
> > +============================
> > +
> > +The MediaTek CAMSYS controller provides various clocks to the system.
>
> Only clocks? If so, then this should be moved to bindings/clocks/.
>

camsys conclude not only clks but also mtcmos, so it's better to put
this node in this path.

> > +
> > +Required Properties:
> > +
> > +- compatible: Should be one of:
> > + - "mediatek,mt6765-camsys", "syscon"
> > +- #clock-cells: Must be 1
> > +
> > +The AUDSYS controller uses the common clk binding from
> > +Documentation/devicetree/bindings/clock/clock-bindings.txt
> > +The available clocks are defined in dt-bindings/clock/mt*-clk.h.
> > +
> > +Required sub-nodes:
> > +-------
> > +For common binding part and usage, refer to
> > +../sonud/mt2701-afe-pcm.txt.
> > +
> > +Example:
> > +
> > +camsys: camsys@1a000000 {
>
> clock-controller@...
>
> if the above answer is yes.
>
> Same comments on the other docs.

2018-08-13 10:27:31

by Owen Chen

[permalink] [raw]

Subject: Re: [PATCH v5 09/11] clk: mediatek: add new clkmux register API

On Thu, 2018-07-19 at 14:57 +0800, Sean Wang wrote:
> On Tue, 2018-07-17 at 16:52 +0800, Mars Cheng wrote:
> > From: Owen Chen <[email protected]>
> >
> > MT6765 add "set/clr" register for each clkmux setting, and
> > one update register to trigger value change. It is designed
> > to prevent read-modify-write racing issue. The sw design
> > need to add a new API to handle this hw change with a new
> > mtk_clk_mux/mtk_clk_upd struct in new file "clk-mux"and
> > clk-upd".
> >
>
> I don't see any word mtk_clk_upd or clk-upd in the patch
>
> and the patch needs to be split into more patches
>

clk-upd is old description, no more clk-upd for handling update bit.

I will remove it next version.

> > Signed-off-by: Owen Chen <[email protected]>
> > ---
> > drivers/clk/mediatek/Makefile | 2 +-
> > drivers/clk/mediatek/clk-mtk.c | 41 +++++++
> > drivers/clk/mediatek/clk-mtk.h | 85 ++++++++++++---
> > drivers/clk/mediatek/clk-mux.c | 236 ++++++++++++++++++++++++++++++++++++++++
> > drivers/clk/mediatek/clk-mux.h | 38 +++++++
> > 5 files changed, 388 insertions(+), 14 deletions(-)
> > create mode 100644 drivers/clk/mediatek/clk-mux.c
> > create mode 100644 drivers/clk/mediatek/clk-mux.h
> >
> > diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> > index 844b55d..b97980d 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -1,5 +1,5 @@
> > # SPDX-License-Identifier: GPL-2.0
> > -obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o
> > +obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
> > obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
> > obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
> > obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
> > diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> > index 9c0ae42..50becd0 100644
> > --- a/drivers/clk/mediatek/clk-mtk.c
> > +++ b/drivers/clk/mediatek/clk-mtk.c
> > @@ -22,6 +22,7 @@
> > #include <linux/mfd/syscon.h>
> >
> > #include "clk-mtk.h"
> > +#include "clk-mux.h"
> > #include "clk-gate.h"
> >
> > struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
> > @@ -144,6 +145,46 @@ int mtk_clk_register_gates(struct device_node *node,
> > return 0;
> > }
> >
> > +int mtk_clk_register_muxes(const struct mtk_mux *muxes,
> > + int num, struct device_node *node,
> > + spinlock_t *lock,
> > + struct clk_onecell_data *clk_data)
> > +{
> > + struct regmap *regmap;
> > + struct clk *clk;
> > + int i;
> > +
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
>
> general register function is able to handle that there is no clk_data.
> It looks like a optional, not a mandatory
>

clk_data is reused in topcksys clk registration, because of the
registration include muxes/gates/dividers/fixed_clks, so we need to make
sure clk_data is not NULL pointer so we can use to store the clk
structure we allocated.

> > + regmap = syscon_node_to_regmap(node);
> > + if (IS_ERR(regmap)) {
> > + pr_err("Cannot find regmap for %pOF: %ld\n", node,
> > + PTR_ERR(regmap));
> > + return PTR_ERR(regmap);
> > + }
> > +
> > + for (i = 0; i < num; i++) {
> > + const struct mtk_mux *mux = &muxes[i];
> > +
> > + if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mux->id]))
> > + continue;
> > +
>
> it seems not necessary to check clk data every time
>
> and always use positive check is good to read
>

Yes, we will remove clk_data check at this point since not necessary.
the if condition check would alter next version.

> > + clk = mtk_clk_register_mux(mux, regmap, lock);
> > +
> > + if (IS_ERR(clk)) {
> > + pr_err("Failed to register clk %s: %ld\n",
> > + mux->name, PTR_ERR(clk));
> > + continue;
> > + }
> > +
> > + if (clk_data)
> > + clk_data->clks[mux->id] = clk;
>
> don't alter any data from input, that is a surprise for users
>

As I mentioned on previous question, clk_data need to be alterd because
of after registration done, we need to offer clk_data as input of
of_clk_add_provider(...,clk_data)

> > + }
> > +
> > + return 0;
> > +}
> > +
> > struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
> > void __iomem *base, spinlock_t *lock)
> > {
> > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> > index 1882221..61693f6 100644
> > --- a/drivers/clk/mediatek/clk-mtk.h
> > +++ b/drivers/clk/mediatek/clk-mtk.h
> > @@ -24,7 +24,9 @@
> >
> > #define MAX_MUX_GATE_BIT 31
> > #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
> > -
> > +#define INVALID_OFS -1
> > +#define INVALID_SHFT -1
> > +#define INVALID_WIDTH -1
> > #define MHZ (1000 * 1000)
> >
> > struct mtk_fixed_clk {
> > @@ -84,10 +86,72 @@ struct mtk_composite {
> > signed char num_parents;
> > };
> >
> > +struct mtk_mux {
> > + int id;
> > + const char *name;
> > + const char * const *parent_names;
> > + unsigned int flags;
> > +
> > + u32 mux_ofs;
> > + u32 set_ofs;
> > + u32 clr_ofs;
> > + u32 upd_ofs;
> > +
> > + signed char mux_shift;
> > + signed char mux_width;
> > + signed char gate_shift;
> > + signed char upd_shift;
> > +
> > + const struct clk_ops *ops;
> > +
> > + signed char num_parents;
> > +};
> > +
>
> you have created a mtk-mux.h, why is you don't move the newly create
> struct in?
>

Okay, I would remove mtk_mux structure and only preserve mtk_clk_mux in
clk_mux.h.

> > /*
> > * In case the rate change propagation to parent clocks is undesirable,
> > * this macro allows to specify the clock flags manually.
> > */
> > +#define CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, _mux_set_ofs,\
> > + _mux_clr_ofs, _shift, _width, _gate, \
> > + _upd_ofs, _upd, _flags, _ops) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .mux_ofs = _mux_ofs, \
> > + .set_ofs = _mux_set_ofs, \
> > + .clr_ofs = _mux_clr_ofs, \
> > + .upd_ofs = _upd_ofs, \
> > + .mux_shift = _shift, \
> > + .mux_width = _width, \
> > + .gate_shift = _gate, \
> > + .upd_shift = _upd, \
> > + .parent_names = _parents, \
> > + .num_parents = ARRAY_SIZE(_parents), \
> > + .flags = _flags, \
> > + .ops = &_ops, \
> > + }
> > +
> > +#define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, _mux_set_ofs,\
> > + _mux_clr_ofs, _shift, _width, _gate, \
> > + _upd_ofs, _upd, _flags) \
> > + CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> > + _gate, _upd_ofs, _upd, _flags, \
> > + mtk_mux_clr_set_upd_ops)
> > +
> > +#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, _mux_set_ofs, \
> > + _mux_clr_ofs, _shift, _width, _gate, \
> > + _upd_ofs, _upd) \
> > + MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> > + _gate, _upd_ofs, _upd, CLK_SET_RATE_PARENT)
> > +
> > +#define MUX_UPD(_id, _name, _parents, _mux_ofs, _shift, _width, _gate, \
> > + _upd_ofs, _upd) \
> > + CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> > + INVALID_OFS, INVALID_OFS, _shift, _width, \
> > + _gate, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
> > + mtk_mux_upd_ops)
> > +
> > #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
> > _gate, _flags) { \
> > .id = _id, \
> > @@ -111,18 +175,8 @@ struct mtk_composite {
> > MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
> > _gate, CLK_SET_RATE_PARENT)
> >
> > -#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
> > - .id = _id, \
> > - .name = _name, \
> > - .mux_reg = _reg, \
> > - .mux_shift = _shift, \
> > - .mux_width = _width, \
> > - .gate_shift = -1, \
> > - .divider_shift = -1, \
> > - .parent_names = _parents, \
> > - .num_parents = ARRAY_SIZE(_parents), \
> > - .flags = CLK_SET_RATE_PARENT, \
> > - }
>
> As Matthias always said that, you alter the common thing that is already
> used by a lot of SoC.
>
> You should have a dedicate patch to state why you need it, provide the
> way you propose. and use another patches for migrating old SoC, finally
> then add the patch for your own SoC.
>
> Don't mix everything in a single patch. The patch can't become reusable
> hard to read it, even hard to backport to the other SoC picking up
> patches they are really wanting.
>

Okay, I will restore it to original version.

> > +#define MUX(_id, _name, _parents, _reg, _shift, _width) \
> > + MUX_GATE(_id, _name, _parents, _reg, _shift, _width, INVALID_SHFT)
> >
> > #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
> > _div_width, _div_shift) { \
> > @@ -138,6 +192,11 @@ struct mtk_composite {
> > .flags = 0, \
> > }
> >
> > +int mtk_clk_register_muxes(const struct mtk_mux *muxes,
> > + int num, struct device_node *node,
> > + spinlock_t *lock,
> > + struct clk_onecell_data *clk_data);
> > +
>
> move to mtk-mux.h
>

Again, we can observe that other(gate/divider/fixed_clk) registration
functions all gather together in clk_mtk.h, if we want to move mtk_mux
to clk_mux.h, I think we may start a new patch to move all other three
registration functions and distribute it to their own driver code such
as clk_gate.h/clk_divider.h...etc.

> > struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
> > void __iomem *base, spinlock_t *lock);
> >
> > diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c
> > new file mode 100644
> > index 0000000..219181b
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mux.c
> > @@ -0,0 +1,236 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2018 MediaTek Inc.
> > + * Author: Owen Chen <[email protected]>
> > + */
> > +
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/slab.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-mux.h"
> > +
> > +static inline struct mtk_clk_mux
> > + *to_mtk_clk_mux(struct clk_hw *hw)
> > +{
> > + return container_of(hw, struct mtk_clk_mux, hw);
> > +}
> > +
> > +static int mtk_mux_enable(struct clk_hw *hw)
> > +{
> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + u32 mask = BIT(mux->gate_shift);
> > + unsigned long flags = 0;
> > +
> > + if (mux->lock)
> > + spin_lock_irqsave(mux->lock, flags);
> > +
>
> we can see many functions in kernel, similar to your need, they always
> be defined as two versions. for example.
>
> mtk_mux_enable refer to lock version
>
> mtk_mux_enable_nolock for lock-free version
>
> that makes less condition, more readable, and users don't care much
> about what stuff is put inside
>

clk.c already provides spin_lock at entrance of clk_enable/clk_disalbe
API, so the lock version seems redundant here, I would remove the lock
version and keep this API lock-free as my next modification.

> > + regmap_update_bits(mux->regmap, mux->mux_ofs, mask, 0);
> > +
> > + if (mux->lock)
> > + spin_unlock_irqrestore(mux->lock, flags);
> > + return 0;
> > +}
> > +
> > +static void mtk_mux_disable(struct clk_hw *hw)
> > +{
> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + u32 mask = BIT(mux->gate_shift);
> > + unsigned long flags = 0;
> > +
> > + if (mux->lock)
> > + spin_lock_irqsave(mux->lock, flags);
> > +
>
> ditto
>

I would remove lock next modification.

> > + regmap_update_bits(mux->regmap, mux->mux_ofs, mask, mask);
> > +
> > + if (mux->lock)
> > + spin_unlock_irqrestore(mux->lock, flags);
> > +}
> > +
> > +static int mtk_mux_enable_setclr(struct clk_hw *hw)
> > +{
> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + u32 val;
> > + unsigned long flags = 0;
> > +
> > + if (mux->lock)
> > + spin_lock_irqsave(mux->lock, flags);
> > +
>
> ditto
>

I would remove lock next modification.

> > + val = BIT(mux->gate_shift);
> > + regmap_write(mux->regmap, mux->mux_clr_ofs, val);
> > +
> > + if (mux->lock)
> > + spin_unlock_irqrestore(mux->lock, flags);
> > + return 0;
> > +}
> > +
> > +static void mtk_mux_disable_setclr(struct clk_hw *hw)
> > +{
> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + u32 val;
> > + unsigned long flags = 0;
> > +
> > + if (mux->lock)
> > + spin_lock_irqsave(mux->lock, flags);
> > +
>
> ditto
>

I would remove lock next modification.

> > + val = BIT(mux->gate_shift);
> > + regmap_write(mux->regmap, mux->mux_set_ofs, val);
> > +
> > + if (mux->lock)
> > + spin_unlock_irqrestore(mux->lock, flags);
> > +}
> > +
> > +static int mtk_mux_is_enabled(struct clk_hw *hw)
> > +{
> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + u32 val = 0;
> > +
> > + if (mux->gate_shift < 0)
> > + return true;
> > +
>
> return value should be bool
>

due to the proto type of is_enabled function is defined to return
integer. I will alter the return value to 1 or 0.

> > + regmap_read(mux->regmap, mux->mux_ofs, &val);
> > +
> > + return (val & BIT(mux->gate_shift)) == 0;
> > +}
> > +
> > +static u8 mtk_mux_get_parent(struct clk_hw *hw)
> > +{
>
>
> return value should be int

Okay, I would alter it next version.

> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + int num_parents = clk_hw_get_num_parents(hw);
> > + u32 mask = GENMASK(mux->mux_width - 1, 0);
> > + u32 val;
> > +
> > + regmap_read(mux->regmap, mux->mux_ofs, &val);
> > + val = (val >> mux->mux_shift) & mask;
> > +
> > + if (val >= num_parents)
> > + return -EINVAL;
> > +
> > + return val;
> > +}
> > +
> > +static int mtk_mux_set_parent(struct clk_hw *hw, u8 index)
> > +{
> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + u32 mask = GENMASK(mux->mux_width - 1, 0);
> > + u32 val, orig;
> > + unsigned long flags = 0;
> > +
> > + if (mux->lock)
> > + spin_lock_irqsave(mux->lock, flags);
> > +
>
> use lock-free-or-not funciton
>

I would remove lock next modification.

> > + regmap_read(mux->regmap, mux->mux_ofs, &val);
> > + orig = val;
> > + val &= ~(mask << mux->mux_shift);
> > + val |= index << mux->mux_shift;
> > +
> > + if (val != orig) {
> > + regmap_write(mux->regmap, mux->mux_ofs, val);
> > +
> > + if (mux->upd_shift >= 0)
> > + regmap_write(mux->regmap, mux->upd_ofs,
> > + BIT(mux->upd_shift));
>
>
> why not use regmap_update_bits like function ?
>

Okay, I would alter it next version..

> > + }
> > +
> > + if (mux->lock)
> > + spin_unlock_irqrestore(mux->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_mux_set_parent_setclr(struct clk_hw *hw, u8 index)
> > +{
> > + struct mtk_clk_mux *mux = to_mtk_clk_mux(hw);
> > + u32 mask = GENMASK(mux->mux_width - 1, 0);
> > + u32 val, orig;
> > + unsigned long flags = 0;
> > +
> > + if (mux->lock)
> > + spin_lock_irqsave(mux->lock, flags);
> > +
>
> use lock-free-or-not funciton
>

I would remove lock next modification.

> > + regmap_read(mux->regmap, mux->mux_ofs, &val);
> > + orig = val;
> > + val &= ~(mask << mux->mux_shift);
> > + val |= index << mux->mux_shift;
> > +
> > + if (val != orig) {
> > + val = (mask << mux->mux_shift);
> > + regmap_write(mux->regmap, mux->mux_clr_ofs, val);
> > + val = (index << mux->mux_shift);
> > + regmap_write(mux->regmap, mux->mux_set_ofs, val);
> > +
>
> why not use regmap_update_bits like function ?

This function specified that mux use set/clr register to update, so it
would be better to use regmap_write to write the whole register instead
of regmap_update_bit.

> > + if (mux->upd_shift >= 0)
> > + regmap_write(mux->regmap, mux->upd_ofs,
> > + BIT(mux->upd_shift));
> > + }
> > +
> > + if (mux->lock)
> > + spin_unlock_irqrestore(mux->lock, flags);
> > +
> > + return 0;
> > +}
> > +
> > +const struct clk_ops mtk_mux_upd_ops = {
> > + .enable = mtk_mux_enable,
> > + .disable = mtk_mux_disable,
> > + .is_enabled = mtk_mux_is_enabled,
> > + .get_parent = mtk_mux_get_parent,
> > + .set_parent = mtk_mux_set_parent,
> > + .determine_rate = NULL,
>
> explicitly set as NULL can be removed

Okay, I would remove it next version.

> > +};
> > +
> > +const struct clk_ops mtk_mux_clr_set_upd_ops = {
> > + .enable = mtk_mux_enable_setclr,
> > + .disable = mtk_mux_disable_setclr,
> > + .is_enabled = mtk_mux_is_enabled,
> > + .get_parent = mtk_mux_get_parent,
> > + .set_parent = mtk_mux_set_parent_setclr,
> > + .determine_rate = NULL,
>
> explicitly set as NULL can be removed

Okay, I would remove it next version.

> > +};
> > +
> > +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> > + struct regmap *regmap,
> > + spinlock_t *lock)
> > +{
> > + struct clk *clk;
> > + struct clk_init_data init;
> > + struct mtk_clk_mux *mtk_mux = NULL;
> > + int ret;
> > +
> make declaration as reverse xmas tree
>

Okay, I would alter it next version.

> > + mtk_mux = kzalloc(sizeof(*mtk_mux), GFP_KERNEL);
> > + if (!mtk_mux)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + init.name = mux->name;
> > + init.flags = (mux->flags) | CLK_SET_RATE_PARENT;
> > + init.parent_names = mux->parent_names;
> > + init.num_parents = mux->num_parents;
> > + init.ops = mux->ops;
> > +
> > + mtk_mux->regmap = regmap;
> > + mtk_mux->name = mux->name;
> > + mtk_mux->mux_ofs = mux->mux_ofs;
> > + mtk_mux->mux_set_ofs = mux->set_ofs;
> > + mtk_mux->mux_clr_ofs = mux->clr_ofs;
> > + mtk_mux->upd_ofs = mux->upd_ofs;
> > + mtk_mux->mux_shift = mux->mux_shift;
> > + mtk_mux->mux_width = mux->mux_width;
> > + mtk_mux->gate_shift = mux->gate_shift;
> > + mtk_mux->upd_shift = mux->upd_shift;
> > +
> > + mtk_mux->lock = lock;
> > + mtk_mux->hw.init = &init;
> > +
> > + clk = clk_register(NULL, &mtk_mux->hw);
> > + if (IS_ERR(clk)) {
> > + ret = PTR_ERR(clk);
>
>
> ret is superfluous
>

Okay, I would remove it next version.

> > + goto err_out;
> > + }
> > +
> > + return clk;
> > +err_out:
> > + kfree(mtk_mux);
> > +
>
> I felt err path can be optimized
>

Okay, I would remove it next version.

> > + return ERR_PTR(ret);
> > +}
> > diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
> > new file mode 100644
> > index 0000000..64f8e7c
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mux.h
> > @@ -0,0 +1,38 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (c) 2018 MediaTek Inc.
> > + * Author: Owen Chen <[email protected]>
> > + */
> > +
> > +#ifndef __DRV_CLK_MUX_H
> > +#define __DRV_CLK_MUX_H
> > +
> > +#include <linux/clk-provider.h>
> > +
> > +struct mtk_clk_mux {
> > + struct clk_hw hw;
> > + struct regmap *regmap;
> > +
> > + const char *name;
> > +
> > + int mux_set_ofs;
> > + int mux_clr_ofs;
> > + int mux_ofs;
> > + int upd_ofs;
> > +
> > + s8 mux_shift;
> > + s8 mux_width;
> > + s8 gate_shift;
> > + s8 upd_shift;
> > +
> > + spinlock_t *lock;
> > +};
> > +
> > +extern const struct clk_ops mtk_mux_upd_ops;
> > +extern const struct clk_ops mtk_mux_clr_set_upd_ops;
> > +
>
>
> extern is superfluous
>

Okay, I would remove it next version.

> > +struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> > + struct regmap *regmap,
> > + spinlock_t *lock);
> > +
> > +#endif /* __DRV_CLK_MUX_H */
>
>