As for today we don't setup SMP_CACHE_BYTESi and cache_line_size for
ARC, so they are set to L1_CACHE_BYTES by default. L1 line length
(L1_CACHE_BYTES) might be easily smaller than L2 line (which is
usually the case BTW). This breaks code.
For example this breaks ethernet infrastructure on HSDK/AXS103 boards
with IOC disabled:
Functions which alloc and manage sk_buff packet data area rely on
SMP_CACHE_BYTES define. In the result we can share last L2 cache
line in sk_buff linear packet data area between DMA buffer and
some useful data in other structure. So we can lose this data when
we invalidate DMA buffer.
sk_buff linear packet data area
|
|
| skb->end skb->tail
V | |
V V
----------------------------------------------.
packet data | <tail padding> | <useful data in other struct>
----------------------------------------------.
---------------------.--------------------------------------------------.
SLC line | SLC (L2 cache) line (128B) |
---------------------.--------------------------------------------------.
^ ^
| |
These cache lines will be invalidated when we invalidate skb
linear packet data area before DMA transaction starting.
This leads to issues painful to debug as it reproduces only if
(sk_buff->end - sk_buff->tail) < SLC_LINE_SIZE and
if we have some useful data right after sk_buff->end.
Fix that by hardcode SMP_CACHE_BYTES to max line length we may have.
Signed-off-by: Eugeniy Paltsev <[email protected]>
---
Changes v1->v2:
* Fix ARCH_HAS_CACHE_LINE_SIZE selection in ARC Kconfig
arch/arc/Kconfig | 3 +++
arch/arc/include/asm/cache.h | 4 +++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 9cf59fc60eab..5151d81476a1 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -50,6 +50,9 @@ config ARC
select HAVE_KERNEL_LZMA
select ARCH_HAS_PTE_SPECIAL
+config ARCH_HAS_CACHE_LINE_SIZE
+ def_bool y
+
config MIGHT_HAVE_PCI
bool
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 8486f328cc5d..ff7d3232764a 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -48,7 +48,9 @@
})
/* Largest line length for either L1 or L2 is 128 bytes */
-#define ARCH_DMA_MINALIGN 128
+#define SMP_CACHE_BYTES 128
+#define cache_line_size() SMP_CACHE_BYTES
+#define ARCH_DMA_MINALIGN SMP_CACHE_BYTES
extern void arc_cache_init(void);
extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
--
2.14.4
Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger
or equal to any cache line length by comparing it with values
previously read from ARC cache BCR registers.
Signed-off-by: Eugeniy Paltsev <[email protected]>
---
Changes v1->v2:
* None.
arch/arc/mm/cache.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 9dbe645ee127..b95365e1253a 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1246,6 +1246,16 @@ void __init arc_cache_init_master(void)
}
}
+ /*
+ * Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger
+ * or equal to any cache line length.
+ */
+ BUILD_BUG_ON_MSG(L1_CACHE_BYTES > SMP_CACHE_BYTES,
+ "SMP_CACHE_BYTES must be >= any cache line length");
+ if (is_isa_arcv2() && (l2_line_sz > SMP_CACHE_BYTES))
+ panic("L2 Cache line [%d] > kernel Config [%d]\n",
+ l2_line_sz, SMP_CACHE_BYTES);
+
/* Note that SLC disable not formally supported till HS 3.0 */
if (is_isa_arcv2() && l2_line_sz && !slc_enable)
arc_slc_disable();
--
2.14.4
On 07/26/2018 06:15 AM, Eugeniy Paltsev wrote:
> Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger
> or equal to any cache line length by comparing it with values
> previously read from ARC cache BCR registers.
>
> Signed-off-by: Eugeniy Paltsev <[email protected]>
> ---
> Changes v1->v2:
> * None.
>
> arch/arc/mm/cache.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
> index 9dbe645ee127..b95365e1253a 100644
> --- a/arch/arc/mm/cache.c
> +++ b/arch/arc/mm/cache.c
> @@ -1246,6 +1246,16 @@ void __init arc_cache_init_master(void)
> }
> }
>
> + /*
> + * Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger
> + * or equal to any cache line length.
> + */
> + BUILD_BUG_ON_MSG(L1_CACHE_BYTES > SMP_CACHE_BYTES,
> + "SMP_CACHE_BYTES must be >= any cache line length");
> + if (is_isa_arcv2() && (l2_line_sz > SMP_CACHE_BYTES))
> + panic("L2 Cache line [%d] > kernel Config [%d]\n",
> + l2_line_sz, SMP_CACHE_BYTES);
> +
> /* Note that SLC disable not formally supported till HS 3.0 */
> if (is_isa_arcv2() && l2_line_sz && !slc_enable)
> arc_slc_disable();
LGTM. Both applied.
Thx,
-Vineet