According to Reference Manual Rev.0, 06/2017,
there are GPIO LPCGs defined in CCM CCGRs,
add them into clock tree.
Signed-off-by: Anson Huang <[email protected]>
---
drivers/clk/imx/clk-imx6sll.c | 6 ++++++
include/dt-bindings/clock/imx6sll-clock.h | 9 ++++++++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c
index 3651c77..6270645 100644
--- a/drivers/clk/imx/clk-imx6sll.c
+++ b/drivers/clk/imx/clk-imx6sll.c
@@ -253,6 +253,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
clks[IMX6SLL_CLK_DCP] = imx_clk_gate2("dcp", "ahb", base + 0x68, 10);
clks[IMX6SLL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
clks[IMX6SLL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
+ clks[IMX6SLL_CLK_GPIO2] = imx_clk_gate2("gpio2", "ipg", base + 0x68, 30);
/* CCGR1 */
clks[IMX6SLL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
@@ -267,13 +268,17 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
clks[IMX6SLL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
clks[IMX6SLL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24);
+ clks[IMX6SLL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26);
+ clks[IMX6SLL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30);
/* CCGR2 */
+ clks[IMX6SLL_CLK_GPIO6] = imx_clk_gate2("gpio6", "ipg", base + 0x70, 0);
clks[IMX6SLL_CLK_CSI] = imx_clk_gate2("csi", "axi", base + 0x70, 2);
clks[IMX6SLL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
clks[IMX6SLL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
clks[IMX6SLL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
clks[IMX6SLL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
+ clks[IMX6SLL_CLK_GPIO3] = imx_clk_gate2("gpio3", "ipg", base + 0x70, 26);
clks[IMX6SLL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28);
clks[IMX6SLL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30);
@@ -283,6 +288,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
clks[IMX6SLL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_aclk", "axi", base + 0x74, 4);
clks[IMX6SLL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_podf", base + 0x74, 4);
clks[IMX6SLL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10);
+ clks[IMX6SLL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12);
clks[IMX6SLL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16);
clks[IMX6SLL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL);
clks[IMX6SLL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
index 151111e..1036475 100644
--- a/include/dt-bindings/clock/imx6sll-clock.h
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -197,6 +197,13 @@
#define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171
#define IMX6SLL_CLK_EXTERN_AUDIO 172
-#define IMX6SLL_CLK_END 173
+#define IMX6SLL_CLK_GPIO1 173
+#define IMX6SLL_CLK_GPIO2 174
+#define IMX6SLL_CLK_GPIO3 175
+#define IMX6SLL_CLK_GPIO4 176
+#define IMX6SLL_CLK_GPIO5 177
+#define IMX6SLL_CLK_GPIO6 178
+
+#define IMX6SLL_CLK_END 179
#endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
--
2.7.4
i.MX6SLL has GPIO clock gates in CCM CCGR, add
clock property for GPIO driver to make sure all
GPIO banks work as expected.
Signed-off-by: Anson Huang <[email protected]>
---
arch/arm/boot/dts/imx6sll.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index c9b0ccc..116f561 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -375,6 +375,7 @@
reg = <0x0209c000 0x4000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -386,6 +387,7 @@
reg = <0x020a0000 0x4000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -397,6 +399,7 @@
reg = <0x020a4000 0x4000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -408,6 +411,7 @@
reg = <0x020a8000 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -419,6 +423,7 @@
reg = <0x020ac000 0x4000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO5>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
@@ -430,6 +435,7 @@
reg = <0x020b0000 0x4000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SLL_CLK_GPIO6>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
--
2.7.4
On Fri, Jun 22, 2018 at 3:32 AM, Anson Huang <[email protected]> wrote:
> According to Reference Manual Rev.0, 06/2017,
> there are GPIO LPCGs defined in CCM CCGRs,
> add them into clock tree.
>
> Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
On Fri, Jun 22, 2018 at 3:32 AM, Anson Huang <[email protected]> wrote:
> i.MX6SLL has GPIO clock gates in CCM CCGR, add
> clock property for GPIO driver to make sure all
> GPIO banks work as expected.
>
> Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
On Fri, Jun 22, 2018 at 02:32:33PM +0800, Anson Huang wrote:
> According to Reference Manual Rev.0, 06/2017,
> there are GPIO LPCGs defined in CCM CCGRs,
> add them into clock tree.
>
> Signed-off-by: Anson Huang <[email protected]>
> ---
> drivers/clk/imx/clk-imx6sll.c | 6 ++++++
> include/dt-bindings/clock/imx6sll-clock.h | 9 ++++++++-
Acked-by: Rob Herring <[email protected]>
> 2 files changed, 14 insertions(+), 1 deletion(-)
Quoting Anson Huang (2018-06-21 23:32:33)
> According to Reference Manual Rev.0, 06/2017,
> there are GPIO LPCGs defined in CCM CCGRs,
> add them into clock tree.
>
> Signed-off-by: Anson Huang <[email protected]>
> ---
Applied to clk-next
On Fri, Jul 06, 2018 at 01:58:46PM -0700, Stephen Boyd wrote:
> Quoting Anson Huang (2018-06-21 23:32:33)
> > According to Reference Manual Rev.0, 06/2017,
> > there are GPIO LPCGs defined in CCM CCGRs,
> > add them into clock tree.
> >
> > Signed-off-by: Anson Huang <[email protected]>
> > ---
>
> Applied to clk-next
Stephen,
If you can apply this patch to topic branch 'clk-imx-gpio-gates', I will
be able to pick up patch #2 for this cycle.
For future cycles, I think the topic branch can be named more generic,
so that any clk patches that DT ones have a dependency on can go there.
And then I can apply all those DT patches by pulling in this topic
branch.
Shawn
Quoting Shawn Guo (2018-07-11 01:43:03)
> On Fri, Jul 06, 2018 at 01:58:46PM -0700, Stephen Boyd wrote:
> > Quoting Anson Huang (2018-06-21 23:32:33)
> > > According to Reference Manual Rev.0, 06/2017,
> > > there are GPIO LPCGs defined in CCM CCGRs,
> > > add them into clock tree.
> > >
> > > Signed-off-by: Anson Huang <[email protected]>
> > > ---
> >
> > Applied to clk-next
>
> Stephen,
>
> If you can apply this patch to topic branch 'clk-imx-gpio-gates', I will
> be able to pick up patch #2 for this cycle.
Can you merge in clk-imx6sll-gpio topic branch to your tree? I'm making
topics for all patch series, so that's why this got stuck into a
different topic branch.
On Wed, Jul 11, 2018 at 09:33:45AM -0700, Stephen Boyd wrote:
> Quoting Shawn Guo (2018-07-11 01:43:03)
> > On Fri, Jul 06, 2018 at 01:58:46PM -0700, Stephen Boyd wrote:
> > > Quoting Anson Huang (2018-06-21 23:32:33)
> > > > According to Reference Manual Rev.0, 06/2017,
> > > > there are GPIO LPCGs defined in CCM CCGRs,
> > > > add them into clock tree.
> > > >
> > > > Signed-off-by: Anson Huang <[email protected]>
> > > > ---
> > >
> > > Applied to clk-next
> >
> > Stephen,
> >
> > If you can apply this patch to topic branch 'clk-imx-gpio-gates', I will
> > be able to pick up patch #2 for this cycle.
>
> Can you merge in clk-imx6sll-gpio topic branch to your tree? I'm making
> topics for all patch series, so that's why this got stuck into a
> different topic branch.
Ah, okay. I thought you apply patches directly to clk-next, and make
topic branches only for those having dependencies involved.
For future DT patches depending on clk ones, I will check clk tree and
merge corresponding topic branch to resolve dependency.
Thanks for clarifying.
Shawn
On Fri, Jun 22, 2018 at 02:32:34PM +0800, Anson Huang wrote:
> i.MX6SLL has GPIO clock gates in CCM CCGR, add
> clock property for GPIO driver to make sure all
> GPIO banks work as expected.
>
> Signed-off-by: Anson Huang <[email protected]>
I tried to create a topic branch for this patch with dependent clk
branch merged in. But it turns out to be difficult and not worth the
effort, because too many imx6sll patches need to be moved out from
imx/dt branch, and some imx6sll changes are mixed with other SoCs.
Let's apply this in next cycle. Ping me when 4.19-rc1 is available.
Shawn
Hi, Shawn
I saw v4.19-rc1 is created, can you please apply this patch?
Anson Huang
Best Regards!
> -----Original Message-----
> From: Shawn Guo <[email protected]>
> Sent: Thursday, July 12, 2018 10:52 AM
> To: Anson Huang <[email protected]>
> Cc: [email protected]; [email protected]; Fabio Estevam
> <[email protected]>; [email protected]; [email protected];
> [email protected]; [email protected]; A.s. Dong
> <[email protected]>; Jacky Bai <[email protected]>; dl-linux-imx
> <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]
> Subject: Re: [PATCH 2/2] ARM: dts: imx6sll: add gpio clocks
>
> On Fri, Jun 22, 2018 at 02:32:34PM +0800, Anson Huang wrote:
> > i.MX6SLL has GPIO clock gates in CCM CCGR, add clock property for GPIO
> > driver to make sure all GPIO banks work as expected.
> >
> > Signed-off-by: Anson Huang <[email protected]>
>
> I tried to create a topic branch for this patch with dependent clk branch merged
> in. But it turns out to be difficult and not worth the effort, because too many
> imx6sll patches need to be moved out from imx/dt branch, and some imx6sll
> changes are mixed with other SoCs.
> Let's apply this in next cycle. Ping me when 4.19-rc1 is available.
>
> Shawn
On Wed, Aug 29, 2018 at 01:12:04AM +0000, Anson Huang wrote:
> Hi, Shawn
> I saw v4.19-rc1 is created, can you please apply this patch?
>
Applied. Thanks for reminding.
Shawn