This is series v3 since my previous patches we incomplete with driver
changes missing.
These changes add UHS-I tuning for dw_mmc-exynos driver.
Some new patches are added to enhance the performace.
Anand Moon (7):
ARM: dts: exynos5422: Added UHS-I bus speed support
ARM: dts: exynos5422: fix regulator min values of LDO13 for Odroid
XU3/XU4
ARM: dts: exynos5422: update maximum frequency for sdcard to 200MHz
ARM: dts: exynos5422: use cd-gpio method to detect sd-card
ARM: dts: exynos5422: use wp-gpio method to detect sd-card
ARM: dts: exynos5422: update maximum frequency for emmc to 200MHz
mmc: dw_mmc-exynos: Add tuning for sdr and ddr timing for USH-I mode
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 8 +++++++-
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 +
drivers/mmc/host/dw_mmc-exynos.c | 11 +++++++++++
3 files changed, 19 insertions(+), 1 deletion(-)
--
2.17.1
looking at the schematic sd_2 min/max range from 1.8V/2.8V so fix the
regulator min value to 1.8V. Without these changes sdcard will failed
to detect on booting when UHS-I tuning is enabled.
Signed-off-by: Anand Moon <[email protected]>
---
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/376262.html
Fixed the commit message.
drop the ramp-delay changes.
drop the vmmc-supply/vqmmc-supply changes.
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 3a58c935c52a..01593f4537ae 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -224,7 +224,7 @@
ldo13_reg: LDO13 {
regulator-name = "vddq_mmc2";
- regulator-min-microvolt = <2800000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
};
--
2.17.1
set the max-frequency to 200MHz for optimal performace.
Signed-off-by: Anand Moon <[email protected]>
---
This patch is new to this series.
microSD card.
root@odroid:~# sudo cat /sys/kernel/debug/mmc1/ios
clock: 200000000 Hz
actual clock: 200000000 Hz
vdd: 16 (2.8 ~ 2.9 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 01593f4537ae..914ee08c7eb2 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -368,6 +368,7 @@
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
cap-sd-highspeed;
+ max-frequency = <200000000>;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
sd-uhs-sdr50;
--
2.17.1
add the Card Detect GPIO property for sdcard detect, to fix
the warning message during boot time.
of_get_named_gpiod_flags: can't parse 'cp-gpios' property of node '/soc/mmc@12220000[0]'
Signed-off-by: Anand Moon <[email protected]>
---
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/376261.html
Fixed the commit message.
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 914ee08c7eb2..03fe02ceae66 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -369,6 +369,7 @@
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <200000000>;
+ cd-gpios = <&gpc2 2 GPIO_ACTIVE_LOW>;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
sd-uhs-sdr50;
--
2.17.1
add the Write Protect GPIO property for sdcard, to fix
the warning message during boot time.
of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/soc/mmc@12220000[0]'
Signed-off-by: Anand Moon <[email protected]>
---
New patch to this series.
If we keep the wp-gpio GPIO_ACTIVE_LOW sdcard boot into RO mode.
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 03fe02ceae66..475c38bbc99e 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -370,6 +370,7 @@
cap-sd-highspeed;
max-frequency = <200000000>;
cd-gpios = <&gpc2 2 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpc4 0 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
sd-uhs-sdr50;
--
2.17.1
set the max-frequency to 200MHz for optimal performace of eMMC.
Signed-off-by: Anand Moon <[email protected]>
---
This patch is new to this series.
MMC
root@odroid:~# sudo cat /sys/kernel/debug/mmc0/ios
clock: 200000000 Hz
actual clock: 200000000 Hz
vdd: 7 (1.65 - 1.95 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 10 (mmc HS400)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
---
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 96e281c0a118..5748f840becc 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -386,6 +386,7 @@
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
+ max-frequency = <200000000>;
vmmc-supply = <&ldo18_reg>;
vqmmc-supply = <&ldo3_reg>;
};
--
2.17.1
Added support for UHS-I bus speed tuning for SDR50, DDR50 SDR104.
Signed-off-by: Anand Moon <[email protected]>
---
[0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/376263.html
Changes from above.
Fix the subject and commit message.
drop sd-uhs-sdr12 and sd-uhs-sdr25 as host driver is not enable as of now
---
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 2f4f40882dab..3a58c935c52a 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -370,6 +370,9 @@
cap-sd-highspeed;
vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
};
&nocp_mem0_0 {
--
2.17.1
Add tuning for sdr and ddr timing for USH-I mode sdr104/sdr50/ddr50
for host controller.
CC: Jaehoon Chung <[email protected]>
CC: Marek Szyprowski <[email protected]>
Signed-off-by: Anand Moon <[email protected]>
---
This patch is new to this series
---
drivers/mmc/host/dw_mmc-exynos.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index ab47b018716a..d46c3439b508 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -253,6 +253,8 @@ static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
if (timing == MMC_TIMING_MMC_HS400) {
dqs |= DATA_STROBE_EN;
strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
+ } else if (timing == MMC_TIMING_UHS_SDR104) {
+ dqs &= 0xffffff00;
} else {
dqs &= ~DATA_STROBE_EN;
}
@@ -312,6 +314,15 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
if (ios->bus_width == MMC_BUS_WIDTH_8)
wanted <<= 1;
break;
+ case MMC_TIMING_UHS_SDR104:
+ case MMC_TIMING_UHS_SDR50:
+ clksel = (priv->sdr_timing & 0xfff8ffff) |
+ (priv->ciu_div << 16);
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ clksel = (priv->ddr_timing & 0xfff8ffff) |
+ (priv->ciu_div << 16);
+ break;
default:
clksel = priv->sdr_timing;
}
--
2.17.1
On Thu, 20 Sep 2018 at 19:58, Anand Moon <[email protected]> wrote:
>
> This is series v3 since my previous patches we incomplete with driver
> changes missing.
>
> These changes add UHS-I tuning for dw_mmc-exynos driver.
> Some new patches are added to enhance the performace.
Patches look like based on some older version of kernel tree (or
current mainline) and probably they will not apply on my tree. The
easiest is to base on top of linux-next or, for DTS patches, on my
next/dt branch.
Best regards,
Krzysztof
>
> Anand Moon (7):
> ARM: dts: exynos5422: Added UHS-I bus speed support
> ARM: dts: exynos5422: fix regulator min values of LDO13 for Odroid
> XU3/XU4
> ARM: dts: exynos5422: update maximum frequency for sdcard to 200MHz
> ARM: dts: exynos5422: use cd-gpio method to detect sd-card
> ARM: dts: exynos5422: use wp-gpio method to detect sd-card
> ARM: dts: exynos5422: update maximum frequency for emmc to 200MHz
> mmc: dw_mmc-exynos: Add tuning for sdr and ddr timing for USH-I mode
>
> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 8 +++++++-
> arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 +
> drivers/mmc/host/dw_mmc-exynos.c | 11 +++++++++++
> 3 files changed, 19 insertions(+), 1 deletion(-)
>
> --
> 2.17.1
>
On Thu, 20 Sep 2018 at 19:59, Anand Moon <[email protected]> wrote:
>
> add the Write Protect GPIO property for sdcard, to fix
> the warning message during boot time.
> of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/soc/mmc@12220000[0]'
>
> Signed-off-by: Anand Moon <[email protected]>
> ---
> New patch to this series.
> If we keep the wp-gpio GPIO_ACTIVE_LOW sdcard boot into RO mode.
> ---
> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> index 03fe02ceae66..475c38bbc99e 100644
> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> @@ -370,6 +370,7 @@
> cap-sd-highspeed;
> max-frequency = <200000000>;
> cd-gpios = <&gpc2 2 GPIO_ACTIVE_LOW>;
> + wp-gpios = <&gpc4 0 GPIO_ACTIVE_HIGH>;
Two issues here:
1. You need also proper pinctrl setting.
2. On schematics the WP is not connected... so how do you know that it
is active high? How did you test it? How do you want to test it on
microSD?
Best regards,
Krzysztof
> vmmc-supply = <&ldo19_reg>;
> vqmmc-supply = <&ldo13_reg>;
> sd-uhs-sdr50;
> --
> 2.17.1
>
Hi Krzysztof,
On Fri, 21 Sep 2018 at 16:26, Krzysztof Kozlowski <[email protected]> wrote:
>
> On Thu, 20 Sep 2018 at 19:58, Anand Moon <[email protected]> wrote:
> >
> > This is series v3 since my previous patches we incomplete with driver
> > changes missing.
> >
> > These changes add UHS-I tuning for dw_mmc-exynos driver.
> > Some new patches are added to enhance the performace.
>
> Patches look like based on some older version of kernel tree (or
> current mainline) and probably they will not apply on my tree. The
> easiest is to base on top of linux-next or, for DTS patches, on my
> next/dt branch.
>
> Best regards,
> Krzysztof
>
Yes this patch is based on current mainline.
I will try to re-base on your next/dt branch and resend them.
Best Regards
-Anand
> >
> > Anand Moon (7):
> > ARM: dts: exynos5422: Added UHS-I bus speed support
> > ARM: dts: exynos5422: fix regulator min values of LDO13 for Odroid
> > XU3/XU4
> > ARM: dts: exynos5422: update maximum frequency for sdcard to 200MHz
> > ARM: dts: exynos5422: use cd-gpio method to detect sd-card
> > ARM: dts: exynos5422: use wp-gpio method to detect sd-card
> > ARM: dts: exynos5422: update maximum frequency for emmc to 200MHz
> > mmc: dw_mmc-exynos: Add tuning for sdr and ddr timing for USH-I mode
> >
> > arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 8 +++++++-
> > arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 +
> > drivers/mmc/host/dw_mmc-exynos.c | 11 +++++++++++
> > 3 files changed, 19 insertions(+), 1 deletion(-)
> >
> > --
> > 2.17.1
> >
Hi Krzysztof,
On Fri, 21 Sep 2018 at 16:42, Krzysztof Kozlowski <[email protected]> wrote:
>
> On Thu, 20 Sep 2018 at 19:59, Anand Moon <[email protected]> wrote:
> >
> > add the Write Protect GPIO property for sdcard, to fix
> > the warning message during boot time.
> > of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/soc/mmc@12220000[0]'
> >
> > Signed-off-by: Anand Moon <[email protected]>
> > ---
> > New patch to this series.
> > If we keep the wp-gpio GPIO_ACTIVE_LOW sdcard boot into RO mode.
> > ---
> > arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> > index 03fe02ceae66..475c38bbc99e 100644
> > --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> > +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> > @@ -370,6 +370,7 @@
> > cap-sd-highspeed;
> > max-frequency = <200000000>;
> > cd-gpios = <&gpc2 2 GPIO_ACTIVE_LOW>;
> > + wp-gpios = <&gpc4 0 GPIO_ACTIVE_HIGH>;
>
> Two issues here:
> 1. You need also proper pinctrl setting.
Thanks for pointing out. Yes proper pinctrl is needed to support this setting.
probably pinctrl sd2_wp is needed to support this feature.
> 2. On schematics the WP is not connected... so how do you know that it
From XU4_MAIN_REV0.1 schematics page 7 "Micro Socket" their is no
connection to WP pin.
but below schematics page "EXYNOS 5422 MMC UFS" it's shows
XMMC2WP/GPC4_0/EXT_INT13_0.
> is active high? How did you test it? How do you want to test it on
> microSD?
I just tested this with the DTS change to GPIO_ACTIVE_LOW which
resulted the microSD card booted into RO mode.
So I set this to GPIO_ACTIVE_HIGH just to avoid warning.
I will study the changes requires and then post proper separate patch
to support this feature.
Best Regards
-Anand
>
> Best regards,
> Krzysztof
>
> > vmmc-supply = <&ldo19_reg>;
> > vqmmc-supply = <&ldo13_reg>;
> > sd-uhs-sdr50;
> > --
> > 2.17.1
> >
On Fri, Sep 21, 2018 at 06:01:07PM +0530, Anand Moon wrote:
> Hi Krzysztof,
>
> On Fri, 21 Sep 2018 at 16:42, Krzysztof Kozlowski <[email protected]> wrote:
> >
> > On Thu, 20 Sep 2018 at 19:59, Anand Moon <[email protected]> wrote:
> > >
> > > add the Write Protect GPIO property for sdcard, to fix
> > > the warning message during boot time.
> > > of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/soc/mmc@12220000[0]'
> > >
> > > Signed-off-by: Anand Moon <[email protected]>
> > > ---
> > > New patch to this series.
> > > If we keep the wp-gpio GPIO_ACTIVE_LOW sdcard boot into RO mode.
> > > ---
> > > arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> > > index 03fe02ceae66..475c38bbc99e 100644
> > > --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> > > +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> > > @@ -370,6 +370,7 @@
> > > cap-sd-highspeed;
> > > max-frequency = <200000000>;
> > > cd-gpios = <&gpc2 2 GPIO_ACTIVE_LOW>;
> > > + wp-gpios = <&gpc4 0 GPIO_ACTIVE_HIGH>;
> >
> > Two issues here:
> > 1. You need also proper pinctrl setting.
>
> Thanks for pointing out. Yes proper pinctrl is needed to support this setting.
> probably pinctrl sd2_wp is needed to support this feature.
>
> > 2. On schematics the WP is not connected... so how do you know that it
> From XU4_MAIN_REV0.1 schematics page 7 "Micro Socket" their is no
> connection to WP pin.
> but below schematics page "EXYNOS 5422 MMC UFS" it's shows
> XMMC2WP/GPC4_0/EXT_INT13_0.
>
> > is active high? How did you test it? How do you want to test it on
> > microSD?
>
> I just tested this with the DTS change to GPIO_ACTIVE_LOW which
> resulted the microSD card booted into RO mode.
> So I set this to GPIO_ACTIVE_HIGH just to avoid warning.
>
> I will study the changes requires and then post proper separate patch
> to support this feature.
Please squash it with cd-gpios change and send it only for the purpose
of describing the hardware. They do not have any meaningful change from
functional point of view (maybe except slower code as now it goes
through gpio subsystem instead of just reading dw-mmc registers).
Please use full sentences in commit msg (so start with capital letter)
and remove reference for warning because there is no warning.
You can follow up on my change for XU:
https://patchwork.kernel.org/patch/10610985/
Best regards,
Krzysztof
Hi Krzysztof,
On Sat, 22 Sep 2018 at 02:39, Krzysztof Kozlowski <[email protected]> wrote:
>
> On Fri, Sep 21, 2018 at 06:01:07PM +0530, Anand Moon wrote:
> > Hi Krzysztof,
> >
> > On Fri, 21 Sep 2018 at 16:42, Krzysztof Kozlowski <[email protected]> wrote:
> > >
> > > On Thu, 20 Sep 2018 at 19:59, Anand Moon <[email protected]> wrote:
> > > >
> > > > add the Write Protect GPIO property for sdcard, to fix
> > > > the warning message during boot time.
> > > > of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/soc/mmc@12220000[0]'
> > > >
> > > > Signed-off-by: Anand Moon <[email protected]>
> > > > ---
> > > > New patch to this series.
> > > > If we keep the wp-gpio GPIO_ACTIVE_LOW sdcard boot into RO mode.
> > > > ---
> > > > arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 1 +
> > > > 1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> > > > index 03fe02ceae66..475c38bbc99e 100644
> > > > --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> > > > +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> > > > @@ -370,6 +370,7 @@
> > > > cap-sd-highspeed;
> > > > max-frequency = <200000000>;
> > > > cd-gpios = <&gpc2 2 GPIO_ACTIVE_LOW>;
> > > > + wp-gpios = <&gpc4 0 GPIO_ACTIVE_HIGH>;
> > >
> > > Two issues here:
> > > 1. You need also proper pinctrl setting.
> >
> > Thanks for pointing out. Yes proper pinctrl is needed to support this setting.
> > probably pinctrl sd2_wp is needed to support this feature.
> >
> > > 2. On schematics the WP is not connected... so how do you know that it
> > From XU4_MAIN_REV0.1 schematics page 7 "Micro Socket" their is no
> > connection to WP pin.
> > but below schematics page "EXYNOS 5422 MMC UFS" it's shows
> > XMMC2WP/GPC4_0/EXT_INT13_0.
> >
> > > is active high? How did you test it? How do you want to test it on
> > > microSD?
> >
> > I just tested this with the DTS change to GPIO_ACTIVE_LOW which
> > resulted the microSD card booted into RO mode.
> > So I set this to GPIO_ACTIVE_HIGH just to avoid warning.
> >
> > I will study the changes requires and then post proper separate patch
> > to support this feature.
>
> Please squash it with cd-gpios change and send it only for the purpose
> of describing the hardware. They do not have any meaningful change from
> functional point of view (maybe except slower code as now it goes
> through gpio subsystem instead of just reading dw-mmc registers).
>
> Please use full sentences in commit msg (so start with capital letter)
> and remove reference for warning because there is no warning.
> You can follow up on my change for XU:
> https://patchwork.kernel.org/patch/10610985/
>
Ok I have tried to squash the changes into single patch.
> Best regards,
> Krzysztof
Best Regards
-Anand