Hi Kishon, Tejun,
This patch series adds support for the SATA AHCI and PHY found on the
ARM-basd BCM63138 DSL SoCs.
It would probably make sense for patches 1-3 to go through Kishon's
tree, patches 4-7 through Tejun's tree, and I would be merging the last
two patches through the Broadcom ARM-SoC tree.
Let me know if this is not a workable plan, thank you very much!
Florian Fainelli (9):
dt-bindings: phy: Document BCM63138 compatible string
phy: brcm-sata: allow PHY_BRCM_SATA driver to be built for DSL SoCs
phy: brcm-sata: Add BCM63138 (DSL) PHY init sequence
dt-bindings: ata: Document BCM63138 compatible string
ata: ahci_brcm: Allow optional reset controller to be used
ata: ahci_brcm: Match BCM63138 compatible strings
ata: ahci_brcm: Allow using driver or DSL SoCs
ARM: dts: BCM63xx: enable SATA PHY and AHCI controller
ARM: bcm63138: Enable SATA AHCI and PHY
.../bindings/ata/brcm,sata-brcm.txt | 1 +
.../devicetree/bindings/phy/brcm-sata-phy.txt | 1 +
arch/arm/boot/dts/bcm63138.dtsi | 30 ++++++++
arch/arm/boot/dts/bcm963138dvt.dts | 8 +++
drivers/ata/Kconfig | 3 +-
drivers/ata/ahci_brcm.c | 10 +++
drivers/phy/broadcom/Kconfig | 3 +-
drivers/phy/broadcom/phy-brcm-sata.c | 70 +++++++++++++++++++
8 files changed, 124 insertions(+), 2 deletions(-)
--
2.17.1
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same
Broadcom SATA PHY that other SoCs are using, make it possible to select
that driver on these platforms.
Signed-off-by: Florian Fainelli <[email protected]>
---
drivers/phy/broadcom/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/broadcom/Kconfig b/drivers/phy/broadcom/Kconfig
index 8786a9674471..aa917a61071d 100644
--- a/drivers/phy/broadcom/Kconfig
+++ b/drivers/phy/broadcom/Kconfig
@@ -60,7 +60,8 @@ config PHY_NS2_USB_DRD
config PHY_BRCM_SATA
tristate "Broadcom SATA PHY driver"
- depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || COMPILE_TEST
+ depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || \
+ ARCH_BCM_63XX || COMPILE_TEST
depends on OF
select GENERIC_PHY
default ARCH_BCM_IPROC
--
2.17.1
Add Device Tree entries for the Broadcom AHCI and SATA PHY controller
found on BCM63138 SoCs
Signed-off-by: Florian Fainelli <[email protected]>
---
arch/arm/boot/dts/bcm63138.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index 6df61518776f..546aabc6f965 100644
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -143,6 +143,36 @@
reg = <0x4800e0 0x10>;
#reset-cells = <2>;
};
+
+ ahci: sata@8000 {
+ compatible = "brcm,bcm63138-ahci", "brcm,sata3-ahci";
+ reg-names = "ahci", "top-ctrl";
+ reg = <0xa000 0x9ac>, <0x8040 0x24>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&pmb0 3 1>;
+ status = "disabled";
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy0>;
+ };
+ };
+
+ sata_phy: sata-phy@8100 {
+ compatible = "brcm,bcm63138-sata-phy", "brcm,phy-sata3";
+ reg = <0x8100 0x1e00>;
+ reg-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata_phy0: sata-phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+ };
};
/* Legacy UBUS base */
--
2.17.1
The Broadcom BCM963138DVT board has an eSATA port which is fully
functional, turn on the AHCI controller and the companion SATA PHY.
Signed-off-by: Florian Fainelli <[email protected]>
---
arch/arm/boot/dts/bcm963138dvt.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts
index c61673638fa8..8dca97eeaf57 100644
--- a/arch/arm/boot/dts/bcm963138dvt.dts
+++ b/arch/arm/boot/dts/bcm963138dvt.dts
@@ -41,3 +41,11 @@
brcm,nand-oob-sectors-size = <16>;
};
};
+
+&ahci {
+ status = "okay";
+};
+
+&sata_phy {
+ status = "okay";
+};
--
2.17.1
Signed-off-by: Florian Fainelli <[email protected]>
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index d535e87151dc..43f4e4fe4742 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -383,6 +383,7 @@ static struct scsi_host_template ahci_platform_sht = {
static const struct of_device_id ahci_of_match[] = {
{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
+ {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
{},
};
--
2.17.1
Match the "brcm,bcm63138-ahci" compatible string in order to allow this
driver to probe on such platforms.
Signed-off-by: Florian Fainelli <[email protected]>
---
drivers/ata/ahci_brcm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index d535e87151dc..43f4e4fe4742 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -383,6 +383,7 @@ static struct scsi_host_template ahci_platform_sht = {
static const struct of_device_id ahci_of_match[] = {
{.compatible = "brcm,bcm7425-ahci", .data = (void *)BRCM_SATA_BCM7425},
{.compatible = "brcm,bcm7445-ahci", .data = (void *)BRCM_SATA_BCM7445},
+ {.compatible = "brcm,bcm63138-ahci", .data = (void *)BRCM_SATA_BCM7445},
{.compatible = "brcm,bcm-nsp-ahci", .data = (void *)BRCM_SATA_NSP},
{},
};
--
2.17.1
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli <[email protected]>
---
drivers/ata/ahci_brcm.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index f3d557777d82..d535e87151dc 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -25,6 +25,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <linux/string.h>
#include "ahci.h"
@@ -94,6 +95,7 @@ struct brcm_ahci_priv {
u32 port_mask;
u32 quirks;
enum brcm_ahci_version version;
+ struct reset_control *rcdev;
};
static inline u32 brcm_sata_readreg(void __iomem *addr)
@@ -411,6 +413,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
if (IS_ERR(priv->top_ctrl))
return PTR_ERR(priv->top_ctrl);
+ priv->rcdev = of_reset_control_get(pdev->dev.of_node, NULL);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_deassert(priv->rcdev);
+
if ((priv->version == BRCM_SATA_BCM7425) ||
(priv->version == BRCM_SATA_NSP)) {
priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
@@ -464,6 +470,9 @@ static int brcm_ahci_remove(struct platform_device *pdev)
brcm_sata_phys_disable(priv);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_assert(priv->rcdev);
+
return 0;
}
--
2.17.1
On BCM63138, we need to reset the AHCI core prior to start utilizing it,
grab the reset controller device cookie and do that.
Signed-off-by: Florian Fainelli <[email protected]>
---
drivers/ata/ahci_brcm.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index f3d557777d82..d535e87151dc 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -25,6 +25,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <linux/string.h>
#include "ahci.h"
@@ -94,6 +95,7 @@ struct brcm_ahci_priv {
u32 port_mask;
u32 quirks;
enum brcm_ahci_version version;
+ struct reset_control *rcdev;
};
static inline u32 brcm_sata_readreg(void __iomem *addr)
@@ -411,6 +413,10 @@ static int brcm_ahci_probe(struct platform_device *pdev)
if (IS_ERR(priv->top_ctrl))
return PTR_ERR(priv->top_ctrl);
+ priv->rcdev = of_reset_control_get(pdev->dev.of_node, NULL);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_deassert(priv->rcdev);
+
if ((priv->version == BRCM_SATA_BCM7425) ||
(priv->version == BRCM_SATA_NSP)) {
priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
@@ -464,6 +470,9 @@ static int brcm_ahci_remove(struct platform_device *pdev)
brcm_sata_phys_disable(priv);
+ if (!IS_ERR(priv->rcdev))
+ reset_control_assert(priv->rcdev);
+
return 0;
}
--
2.17.1
Document the compatible string "brcm,bcm63138-ahci" as a valid
compatible string for the standard Broadcom AHCI controller.
Signed-off-by: Florian Fainelli <[email protected]>
---
Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
index 0a5b3b47f217..7713a413c6a7 100644
--- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
@@ -9,6 +9,7 @@ Required properties:
"brcm,bcm7445-ahci"
"brcm,bcm-nsp-ahci"
"brcm,sata3-ahci"
+ "brcm,bcm63138-ahci"
- reg : register mappings for AHCI and SATA_TOP_CTRL
- reg-names : "ahci" and "top-ctrl"
- interrupts : interrupt mapping for SATA IRQ
--
2.17.1
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same
Broadcom SATA PHY that other SoCs are using, make it possible to select
that driver on these platforms.
Signed-off-by: Florian Fainelli <[email protected]>
---
drivers/phy/broadcom/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/broadcom/Kconfig b/drivers/phy/broadcom/Kconfig
index 8786a9674471..aa917a61071d 100644
--- a/drivers/phy/broadcom/Kconfig
+++ b/drivers/phy/broadcom/Kconfig
@@ -60,7 +60,8 @@ config PHY_NS2_USB_DRD
config PHY_BRCM_SATA
tristate "Broadcom SATA PHY driver"
- depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || COMPILE_TEST
+ depends on ARCH_BRCMSTB || ARCH_BCM_IPROC || BMIPS_GENERIC || \
+ ARCH_BCM_63XX || COMPILE_TEST
depends on OF
select GENERIC_PHY
default ARCH_BCM_IPROC
--
2.17.1
Document the compatible string "brcm,bcm63138-sata-phy" as a valid
compatible string describing the standard Broadcom SATA PHY block.
Signed-off-by: Florian Fainelli <[email protected]>
---
Documentation/devicetree/bindings/phy/brcm-sata-phy.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt
index 0aced97d8092..b640845fec67 100644
--- a/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt
+++ b/Documentation/devicetree/bindings/phy/brcm-sata-phy.txt
@@ -8,6 +8,7 @@ Required properties:
"brcm,iproc-nsp-sata-phy"
"brcm,phy-sata3"
"brcm,iproc-sr-sata-phy"
+ "brcm,bcm63138-sata-phy"
- address-cells: should be 1
- size-cells: should be 0
- reg: register ranges for the PHY PCB interface
--
2.17.1
The Broadcom STB AHCI controller is the same as the one found on DSL
SoCs, so we will utilize the same driver on these systems as well.
Signed-off-by: Florian Fainelli <[email protected]>
---
drivers/ata/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 39b181d6bd0d..99698d7fe585 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -121,7 +121,8 @@ config SATA_AHCI_PLATFORM
config AHCI_BRCM
tristate "Broadcom AHCI SATA support"
- depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_NSP
+ depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_NSP || \
+ ARCH_BCM_63XX
help
This option enables support for the AHCI SATA3 controller found on
Broadcom SoC's.
--
2.17.1
The BCM63138 SATA PHY requires a special initialization sequence in
order to operate correctly, mostly tuning incorrect default values.
Implement that sequence and match the documented compatible string as an
entry point into that sequence.
Signed-off-by: Florian Fainelli <[email protected]>
---
drivers/phy/broadcom/phy-brcm-sata.c | 70 ++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/drivers/phy/broadcom/phy-brcm-sata.c b/drivers/phy/broadcom/phy-brcm-sata.c
index 8708ea3b4d6d..218735305d85 100644
--- a/drivers/phy/broadcom/phy-brcm-sata.c
+++ b/drivers/phy/broadcom/phy-brcm-sata.c
@@ -47,6 +47,7 @@ enum brcm_sata_phy_version {
BRCM_SATA_PHY_IPROC_NS2,
BRCM_SATA_PHY_IPROC_NSP,
BRCM_SATA_PHY_IPROC_SR,
+ BRCM_SATA_PHY_DSL_28NM,
};
enum brcm_sata_phy_rxaeq_mode {
@@ -96,7 +97,10 @@ enum sata_phy_regs {
PLLCONTROL_0_FREQ_DET_RESTART = BIT(13),
PLLCONTROL_0_FREQ_MONITOR = BIT(12),
PLLCONTROL_0_SEQ_START = BIT(15),
+ PLL_CAP_CHARGE_TIME = 0x83,
+ PLL_VCO_CAL_THRESH = 0x84,
PLL_CAP_CONTROL = 0x85,
+ PLL_FREQ_DET_TIME = 0x86,
PLL_ACTRL2 = 0x8b,
PLL_ACTRL2_SELDIV_MASK = 0x1f,
PLL_ACTRL2_SELDIV_SHIFT = 9,
@@ -106,6 +110,9 @@ enum sata_phy_regs {
PLL1_ACTRL2 = 0x82,
PLL1_ACTRL3 = 0x83,
PLL1_ACTRL4 = 0x84,
+ PLL1_ACTRL5 = 0x85,
+ PLL1_ACTRL6 = 0x86,
+ PLL1_ACTRL7 = 0x87,
TX_REG_BANK = 0x070,
TX_ACTRL0 = 0x80,
@@ -119,6 +126,8 @@ enum sata_phy_regs {
AEQ_FRC_EQ_FORCE = BIT(0),
AEQ_FRC_EQ_FORCE_VAL = BIT(1),
AEQRX_REG_BANK_1 = 0xe0,
+ AEQRX_SLCAL0_CTRL0 = 0x82,
+ AEQRX_SLCAL1_CTRL0 = 0x86,
OOB_REG_BANK = 0x150,
OOB1_REG_BANK = 0x160,
@@ -168,6 +177,7 @@ static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
switch (priv->version) {
case BRCM_SATA_PHY_STB_28NM:
case BRCM_SATA_PHY_IPROC_NS2:
+ case BRCM_SATA_PHY_DSL_28NM:
size = SATA_PCB_REG_28NM_SPACE_SIZE;
break;
case BRCM_SATA_PHY_STB_40NM:
@@ -482,6 +492,61 @@ static int brcm_sr_sata_init(struct brcm_sata_port *port)
return 0;
}
+static int brcm_dsl_sata_init(struct brcm_sata_port *port)
+{
+ void __iomem *base = brcm_sata_pcb_base(port);
+ struct device *dev = port->phy_priv->dev;
+ unsigned int try;
+ u32 tmp;
+
+ brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
+
+ brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+ 0, 0x3089);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
+ 0, 0x3088);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
+ 0, 0x3000);
+
+ brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
+ 0, 0x3000);
+ usleep_range(1000, 2000);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
+
+ brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
+ usleep_range(1000, 2000);
+
+ /* Acquire PLL lock */
+ try = 50;
+ while (try) {
+ tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
+ BLOCK0_XGXSSTATUS);
+ if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
+ break;
+ msleep(20);
+ try--;
+ };
+
+ if (!try) {
+ /* PLL did not lock; give up */
+ dev_err(dev, "port%d PLL did not lock\n", port->portnum);
+ return -ETIMEDOUT;
+ }
+
+ dev_dbg(dev, "port%d initialized\n", port->portnum);
+
+ return 0;
+}
+
static int brcm_sata_phy_init(struct phy *phy)
{
int rc;
@@ -501,6 +566,9 @@ static int brcm_sata_phy_init(struct phy *phy)
case BRCM_SATA_PHY_IPROC_SR:
rc = brcm_sr_sata_init(port);
break;
+ case BRCM_SATA_PHY_DSL_28NM:
+ rc = brcm_dsl_sata_init(port);
+ break;
default:
rc = -ENODEV;
}
@@ -552,6 +620,8 @@ static const struct of_device_id brcm_sata_phy_of_match[] = {
.data = (void *)BRCM_SATA_PHY_IPROC_NSP },
{ .compatible = "brcm,iproc-sr-sata-phy",
.data = (void *)BRCM_SATA_PHY_IPROC_SR },
+ { .compatible = "brcm,bcm63138-sata-phy",
+ .data = (void *)BRCM_SATA_PHY_DSL_28NM },
{},
};
MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
--
2.17.1
On 09/20/2018 12:16 PM, Florian Fainelli wrote:
> Hi Kishon, Tejun,
>
> This patch series adds support for the SATA AHCI and PHY found on the
> ARM-basd BCM63138 DSL SoCs.
>
> It would probably make sense for patches 1-3 to go through Kishon's
> tree, patches 4-7 through Tejun's tree, and I would be merging the last
> two patches through the Broadcom ARM-SoC tree.
>
> Let me know if this is not a workable plan, thank you very much!
Looks like I had left patches with the incorrect subject, please
disregard the following patches:
[PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built for
DSL SoCs
[PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to be used
[PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings
since they have incorrect/inconsistent titles, the other patches are
fine though. Sorry about that.
>
> Florian Fainelli (9):
> dt-bindings: phy: Document BCM63138 compatible string
> phy: brcm-sata: allow PHY_BRCM_SATA driver to be built for DSL SoCs
> phy: brcm-sata: Add BCM63138 (DSL) PHY init sequence
> dt-bindings: ata: Document BCM63138 compatible string
> ata: ahci_brcm: Allow optional reset controller to be used
> ata: ahci_brcm: Match BCM63138 compatible strings
> ata: ahci_brcm: Allow using driver or DSL SoCs
> ARM: dts: BCM63xx: enable SATA PHY and AHCI controller
> ARM: bcm63138: Enable SATA AHCI and PHY
>
> .../bindings/ata/brcm,sata-brcm.txt | 1 +
> .../devicetree/bindings/phy/brcm-sata-phy.txt | 1 +
> arch/arm/boot/dts/bcm63138.dtsi | 30 ++++++++
> arch/arm/boot/dts/bcm963138dvt.dts | 8 +++
> drivers/ata/Kconfig | 3 +-
> drivers/ata/ahci_brcm.c | 10 +++
> drivers/phy/broadcom/Kconfig | 3 +-
> drivers/phy/broadcom/phy-brcm-sata.c | 70 +++++++++++++++++++
> 8 files changed, 124 insertions(+), 2 deletions(-)
>
--
Florian
On Friday 21 September 2018 12:49 AM, Florian Fainelli wrote:
> On 09/20/2018 12:16 PM, Florian Fainelli wrote:
>> Hi Kishon, Tejun,
>>
>> This patch series adds support for the SATA AHCI and PHY found on the
>> ARM-basd BCM63138 DSL SoCs.
>>
>> It would probably make sense for patches 1-3 to go through Kishon's
>> tree, patches 4-7 through Tejun's tree, and I would be merging the last
>> two patches through the Broadcom ARM-SoC tree.
>>
>> Let me know if this is not a workable plan, thank you very much!
>
> Looks like I had left patches with the incorrect subject, please
> disregard the following patches:
>
> [PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built for
> DSL SoCs
> [PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to be used
> [PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings
>
> since they have incorrect/inconsistent titles, the other patches are
> fine though. Sorry about that.
merged the first 3 patches to linux-phy tree.
Thanks
Kishon
On 09/24/2018 11:19 PM, Kishon Vijay Abraham I wrote:
>
>
> On Friday 21 September 2018 12:49 AM, Florian Fainelli wrote:
>> On 09/20/2018 12:16 PM, Florian Fainelli wrote:
>>> Hi Kishon, Tejun,
>>>
>>> This patch series adds support for the SATA AHCI and PHY found on the
>>> ARM-basd BCM63138 DSL SoCs.
>>>
>>> It would probably make sense for patches 1-3 to go through Kishon's
>>> tree, patches 4-7 through Tejun's tree, and I would be merging the last
>>> two patches through the Broadcom ARM-SoC tree.
>>>
>>> Let me know if this is not a workable plan, thank you very much!
>>
>> Looks like I had left patches with the incorrect subject, please
>> disregard the following patches:
>>
>> [PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built for
>> DSL SoCs
>> [PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to be used
>> [PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings
>>
>> since they have incorrect/inconsistent titles, the other patches are
>> fine though. Sorry about that.
>
> merged the first 3 patches to linux-phy tree.
Thanks a lot Kishon!
>
> Thanks
> Kishon
>
--
Florian
On 09/25/2018 09:12 AM, Florian Fainelli wrote:
> On 09/24/2018 11:19 PM, Kishon Vijay Abraham I wrote:
>>
>>
>> On Friday 21 September 2018 12:49 AM, Florian Fainelli wrote:
>>> On 09/20/2018 12:16 PM, Florian Fainelli wrote:
>>>> Hi Kishon, Tejun,
>>>>
>>>> This patch series adds support for the SATA AHCI and PHY found on the
>>>> ARM-basd BCM63138 DSL SoCs.
>>>>
>>>> It would probably make sense for patches 1-3 to go through Kishon's
>>>> tree, patches 4-7 through Tejun's tree, and I would be merging the last
>>>> two patches through the Broadcom ARM-SoC tree.
>>>>
>>>> Let me know if this is not a workable plan, thank you very much!
>>>
>>> Looks like I had left patches with the incorrect subject, please
>>> disregard the following patches:
>>>
>>> [PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built for
>>> DSL SoCs
>>> [PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to be used
>>> [PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings
>>>
>>> since they have incorrect/inconsistent titles, the other patches are
>>> fine though. Sorry about that.
>>
>> merged the first 3 patches to linux-phy tree.
>
> Thanks a lot Kishon!
Tejun, are you good with picking up patches 4-7 and I take the last two?
Can you make sure you pick up the ones that contain "ahci_brcm" in their
subject, I had incorrectly formatted them initially, sorry again about that.
Thank you!
--
Florian
On Fri, Sep 28, 2018 at 03:41:23PM -0700, Florian Fainelli wrote:
> On 09/25/2018 09:12 AM, Florian Fainelli wrote:
> > On 09/24/2018 11:19 PM, Kishon Vijay Abraham I wrote:
> >> On Friday 21 September 2018 12:49 AM, Florian Fainelli wrote:
> >>> On 09/20/2018 12:16 PM, Florian Fainelli wrote:
> >>>> Hi Kishon, Tejun,
> >>>>
> >>>> This patch series adds support for the SATA AHCI and PHY found on the
> >>>> ARM-basd BCM63138 DSL SoCs.
> >>>>
> >>>> It would probably make sense for patches 1-3 to go through Kishon's
> >>>> tree, patches 4-7 through Tejun's tree, and I would be merging the last
> >>>> two patches through the Broadcom ARM-SoC tree.
> >>>>
> >>>> Let me know if this is not a workable plan, thank you very much!
> >>>
> >>> Looks like I had left patches with the incorrect subject, please
> >>> disregard the following patches:
> >>>
> >>> [PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built for
> >>> DSL SoCs
> >>> [PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to be used
> >>> [PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings
> >>>
> >>> since they have incorrect/inconsistent titles, the other patches are
> >>> fine though. Sorry about that.
> >>
> >> merged the first 3 patches to linux-phy tree.
> >
> > Thanks a lot Kishon!
>
> Tejun, are you good with picking up patches 4-7 and I take the last two?
> Can you make sure you pick up the ones that contain "ahci_brcm" in their
> subject, I had incorrectly formatted them initially, sorry again about that.
Jens is running the libata tree now. Jens?
Thanks.
--
tejun
On 9/29/18 2:56 AM, Tejun Heo wrote:
> On Fri, Sep 28, 2018 at 03:41:23PM -0700, Florian Fainelli wrote:
>> On 09/25/2018 09:12 AM, Florian Fainelli wrote:
>>> On 09/24/2018 11:19 PM, Kishon Vijay Abraham I wrote:
>>>> On Friday 21 September 2018 12:49 AM, Florian Fainelli wrote:
>>>>> On 09/20/2018 12:16 PM, Florian Fainelli wrote:
>>>>>> Hi Kishon, Tejun,
>>>>>>
>>>>>> This patch series adds support for the SATA AHCI and PHY found on the
>>>>>> ARM-basd BCM63138 DSL SoCs.
>>>>>>
>>>>>> It would probably make sense for patches 1-3 to go through Kishon's
>>>>>> tree, patches 4-7 through Tejun's tree, and I would be merging the last
>>>>>> two patches through the Broadcom ARM-SoC tree.
>>>>>>
>>>>>> Let me know if this is not a workable plan, thank you very much!
>>>>>
>>>>> Looks like I had left patches with the incorrect subject, please
>>>>> disregard the following patches:
>>>>>
>>>>> [PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built for
>>>>> DSL SoCs
>>>>> [PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to be used
>>>>> [PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings
>>>>>
>>>>> since they have incorrect/inconsistent titles, the other patches are
>>>>> fine though. Sorry about that.
>>>>
>>>> merged the first 3 patches to linux-phy tree.
>>>
>>> Thanks a lot Kishon!
>>
>> Tejun, are you good with picking up patches 4-7 and I take the last two?
>> Can you make sure you pick up the ones that contain "ahci_brcm" in their
>> subject, I had incorrectly formatted them initially, sorry again about that.
>
> Jens is running the libata tree now. Jens?
I looked over them, but the series seems somewhat messed up. Can you
resend 4-7?
--
Jens Axboe
On September 29, 2018 7:35:14 PM PDT, Jens Axboe <[email protected]> wrote:
>On 9/29/18 2:56 AM, Tejun Heo wrote:
>> On Fri, Sep 28, 2018 at 03:41:23PM -0700, Florian Fainelli wrote:
>>> On 09/25/2018 09:12 AM, Florian Fainelli wrote:
>>>> On 09/24/2018 11:19 PM, Kishon Vijay Abraham I wrote:
>>>>> On Friday 21 September 2018 12:49 AM, Florian Fainelli wrote:
>>>>>> On 09/20/2018 12:16 PM, Florian Fainelli wrote:
>>>>>>> Hi Kishon, Tejun,
>>>>>>>
>>>>>>> This patch series adds support for the SATA AHCI and PHY found
>on the
>>>>>>> ARM-basd BCM63138 DSL SoCs.
>>>>>>>
>>>>>>> It would probably make sense for patches 1-3 to go through
>Kishon's
>>>>>>> tree, patches 4-7 through Tejun's tree, and I would be merging
>the last
>>>>>>> two patches through the Broadcom ARM-SoC tree.
>>>>>>>
>>>>>>> Let me know if this is not a workable plan, thank you very much!
>>>>>>
>>>>>> Looks like I had left patches with the incorrect subject, please
>>>>>> disregard the following patches:
>>>>>>
>>>>>> [PATCH 2/9] phy: broadcom: allow PHY_BRCM_SATA driver to be built
>for
>>>>>> DSL SoCs
>>>>>> [PATCH 5/9] ata: sata_brcmstb: Allow optional reset controller to
>be used
>>>>>> [PATCH 6/9] ata: ahci_brcmstb: Match 63138 compatible strings
>>>>>>
>>>>>> since they have incorrect/inconsistent titles, the other patches
>are
>>>>>> fine though. Sorry about that.
>>>>>
>>>>> merged the first 3 patches to linux-phy tree.
>>>>
>>>> Thanks a lot Kishon!
>>>
>>> Tejun, are you good with picking up patches 4-7 and I take the last
>two?
>>> Can you make sure you pick up the ones that contain "ahci_brcm" in
>their
>>> subject, I had incorrectly formatted them initially, sorry again
>about that.
>>
>> Jens is running the libata tree now. Jens?
>
>I looked over them, but the series seems somewhat messed up. Can you
>resend 4-7?
Certainly, I accidentally sent duplicates that I had left in the directory.
--
Florian
On 09/20/2018 12:16 PM, Florian Fainelli wrote:
> Add Device Tree entries for the Broadcom AHCI and SATA PHY controller
> found on BCM63138 SoCs
>
> Signed-off-by: Florian Fainelli <[email protected]>
Applied to devicetree/next.
--
Florian
On 09/20/2018 12:16 PM, Florian Fainelli wrote:
> The Broadcom BCM963138DVT board has an eSATA port which is fully
> functional, turn on the AHCI controller and the companion SATA PHY.
>
> Signed-off-by: Florian Fainelli <[email protected]>
Applied to devicetree/next
--
Florian