This is series v4 since my previous patches were incomplete with driver
changes missing.
v4 changes.
squash cd-gpios and wp-gpio changes into single patch.
change the subject prefix to "ARM: dts: exynos:"
These changes add UHS-I tuning for dw_mmc-exynos driver.
Rebased on Krzysztof branch next/dt
[0] git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
Anand Moon (6):
ARM: dts: exynos: Added UHS-I bus speed support
ARM: dts: exynos: fix regulator min values of LDO13 for Odroid XU3/XU4
ARM: dts: exynos: update maximum frequency for sdcard to 200MHz
ARM: dts: exynos: Add CD and WP pins to Odroid XU3/XU4 SD card
ARM: dts: exynos: update maximum frequency for emmc to 200MHz
mmc: dw_mmc-exynos: Add tuning for sdr and ddr timing for USH-I mode
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 8 ++++++++
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 10 ++++++++--
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 +
drivers/mmc/host/dw_mmc-exynos.c | 11 +++++++++++
4 files changed, 28 insertions(+), 2 deletions(-)
--
2.17.1
Add tuning for sdr and ddr timing for USH-I mode sdr104/sdr50/ddr50
for host controller.
Cc: Jaehoon Chung <[email protected]>
Cc: Marek Szyprowski <[email protected]>
Signed-off-by: Anand Moon <[email protected]>
---
No changes from previous patch
---
drivers/mmc/host/dw_mmc-exynos.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index ab47b018716a..d46c3439b508 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -253,6 +253,8 @@ static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
if (timing == MMC_TIMING_MMC_HS400) {
dqs |= DATA_STROBE_EN;
strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
+ } else if (timing == MMC_TIMING_UHS_SDR104) {
+ dqs &= 0xffffff00;
} else {
dqs &= ~DATA_STROBE_EN;
}
@@ -312,6 +314,15 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
if (ios->bus_width == MMC_BUS_WIDTH_8)
wanted <<= 1;
break;
+ case MMC_TIMING_UHS_SDR104:
+ case MMC_TIMING_UHS_SDR50:
+ clksel = (priv->sdr_timing & 0xfff8ffff) |
+ (priv->ciu_div << 16);
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ clksel = (priv->ddr_timing & 0xfff8ffff) |
+ (priv->ciu_div << 16);
+ break;
default:
clksel = priv->sdr_timing;
}
--
2.17.1